[multiple changes]
2006-06-26 DJ Delorie <dj@redhat.com> * config/m32c/m32c.c (m32c_print_operand): Fix sign-merging logic. 2006-06-26 Naveen H.S <naveenh@kpitcummins.com> Jayant Sonar <jayants@kpitcummins.com> Jaydeep Vipradas <jaydeepv@kpitcummins.com> * config/m32c/addsub.md (addsi3, addsi3_1, addsi3_2): New. (subsi3, subsi3_1, subsi3_2): New. * config/m32c/bitops.md (andsi3, iorsi3, xorsi3): New. * config/m32c/mov.md (SI mov peephole): New. * config/m32c/m32.c (m32c_immd_dbl_mov): New. * config/m32c/m32c-protos.h (m32c_immd_dbl_mov): New. From-SVN: r115023
This commit is contained in:
DJ Delorie
parent
500c353d72
commit
ff485e71cf
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@ -1,3 +1,18 @@
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2006-06-26 DJ Delorie <dj@redhat.com>
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* config/m32c/m32c.c (m32c_print_operand): Fix sign-merging logic.
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2006-06-26 Naveen H.S <naveenh@kpitcummins.com>
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Jayant Sonar <jayants@kpitcummins.com>
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Jaydeep Vipradas <jaydeepv@kpitcummins.com>
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* config/m32c/addsub.md (addsi3, addsi3_1, addsi3_2): New.
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(subsi3, subsi3_1, subsi3_2): New.
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* config/m32c/bitops.md (andsi3, iorsi3, xorsi3): New.
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* config/m32c/mov.md (SI mov peephole): New.
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* config/m32c/m32.c (m32c_immd_dbl_mov): New.
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* config/m32c/m32c-protos.h (m32c_immd_dbl_mov): New.
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2006-06-26 Olivier Hainque <hainque@adacore.com>
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* function.c (aggregate_value_p): Honor DECL_BY_REFERENCE on
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@ -72,6 +72,56 @@
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[(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
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)
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24 ||TARGET_A16"
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""
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)
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(define_insn "addsi3_1"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
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(match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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"TARGET_A16"
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"*
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switch (which_alternative)
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{
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case 0:
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return \"add.w %X2,%h0\;adcf.w %H0\";
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case 1:
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return \"add.w %X2,%h0\;adcf.w %H0\";
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case 2:
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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case 3:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 4:
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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case 5:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 6:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 7:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x,x,x")]
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)
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(define_insn "addsi3_2"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24"
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"add.l\t%2,%0"
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[(set_attr "flags" "oszc")]
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)
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(define_insn "subqi3"
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[(set (match_operand:QI 0 "mra_or_sp_operand"
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"=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
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@ -111,6 +161,51 @@
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[(set_attr "flags" "oszc")]
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)
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(define_expand "subsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24 ||TARGET_A16"
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""
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)
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(define_insn "subsi3_1"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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"TARGET_A16"
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"*
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switch (which_alternative)
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{
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case 0:
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output_asm_insn (\"sub.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"sbb.w %X2,%H0\";
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case 1:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 2:
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output_asm_insn (\"sub.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"sbb.w %X2,%H0\";
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case 3:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 4:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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case 5:
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return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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(define_insn "subsi3_2"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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(minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
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"TARGET_A24"
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"sub.l\t%2,%0"
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[(set_attr "flags" "oszc,oszc,oszc,oszc")]
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)
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(define_insn "negqi2"
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[(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
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(neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
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@ -113,6 +113,33 @@
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[(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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)
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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""
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"*
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switch (which_alternative)
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{
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case 0:
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output_asm_insn (\"and.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"and.w %X2,%H0\";
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case 1:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 2:
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output_asm_insn (\"and.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"and.w %X2,%H0\";
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case 3:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 4:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 5:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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(define_insn "iorqi3_16"
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@ -264,6 +291,34 @@
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DONE;"
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)
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(define_insn "iorsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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""
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"*
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switch (which_alternative)
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{
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case 0:
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output_asm_insn (\"or.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"or.w %X2,%H0\";
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case 1:
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return \"or.w %h2,%h0\;or.w %H2,%H0\";
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case 2:
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output_asm_insn (\"or.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"or.w %X2,%H0\";
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case 3:
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return \"or.w %h2,%h0\;or.w %H2,%H0\";
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case 4:
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return \"or.w %h2,%h0\;or.w %H2,%H0\";
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case 5:
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return \"or.w %h2,%h0\;or.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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(define_insn "xorqi3"
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[(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
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(xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
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@ -282,6 +337,34 @@
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[(set_attr "flags" "sz,sz,sz,sz")]
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)
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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""
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"*
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switch (which_alternative)
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{
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case 0:
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output_asm_insn (\"xor.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"xor.w %X2,%H0\";
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case 1:
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return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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case 2:
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output_asm_insn (\"xor.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"xor.w %X2,%H0\";
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case 3:
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return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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case 4:
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return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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case 5:
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return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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(define_insn "one_cmplqi2"
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[(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
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(not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
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@ -72,6 +72,7 @@ int m32c_extra_constraint_p (rtx, char, const char *);
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int m32c_extra_constraint_p2 (rtx, char, const char *);
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int m32c_hard_regno_nregs (int, MM);
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int m32c_hard_regno_ok (int, MM);
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bool m32c_immd_dbl_mov (rtx *, MM);
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rtx m32c_incoming_return_addr_rtx (void);
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void m32c_initialize_trampoline (rtx, rtx, rtx);
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int m32c_legitimate_address_p (MM, rtx, int);
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@ -2301,6 +2301,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
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const char *comma;
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HOST_WIDE_INT ival;
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int unsigned_const = 0;
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int force_sign;
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/* Multiplies; constants are converted to sign-extended format but
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we need unsigned, so 'u' and 'U' tell us what size unsigned we
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@ -2463,6 +2464,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
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code = 0;
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encode_pattern (x);
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force_sign = 0;
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for (i = 0; conversions[i].pattern; i++)
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if (conversions[i].code == code
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&& streq (conversions[i].pattern, pattern))
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@ -2576,6 +2578,8 @@ m32c_print_operand (FILE * file, rtx x, int code)
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/* Integers used as addresses are unsigned. */
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ival &= (TARGET_A24 ? 0xffffff : 0xffff);
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}
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if (force_sign && ival >= 0)
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fputc ('+', file);
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
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break;
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}
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@ -2620,13 +2624,14 @@ m32c_print_operand (FILE * file, rtx x, int code)
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/* Signed displacements off symbols need to have signs
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blended cleanly. */
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if (conversions[i].format[j] == '+'
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&& (!code || code == 'I')
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&& (!code || code == 'D' || code == 'd')
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&& ISDIGIT (conversions[i].format[j + 1])
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&& GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
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== CONST_INT
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&& INTVAL (patternr[conversions[i].format[j + 1] - '0']) <
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0)
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continue;
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&& (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
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== CONST_INT))
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{
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force_sign = 1;
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continue;
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}
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fputc (conversions[i].format[j], file);
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}
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break;
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@ -2787,6 +2792,102 @@ m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
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return true;
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}
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/* Returns TRUE if two consecutive HImode mov instructions, generated
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for moving an immediate double data to a double data type variable
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location, can be combined into single SImode mov instruction. */
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bool
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m32c_immd_dbl_mov (rtx * operands,
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enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
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const char *str1;
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const char *str2;
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if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
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&& MEM_SCALAR_P (operands[0])
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&& !MEM_IN_STRUCT_P (operands[0])
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&& GET_CODE (XEXP (operands[2], 0)) == CONST
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&& GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
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&& MEM_SCALAR_P (operands[2])
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&& !MEM_IN_STRUCT_P (operands[2]))
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flag = 1;
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else if (GET_CODE (XEXP (operands[0], 0)) == CONST
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&& GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
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&& MEM_SCALAR_P (operands[0])
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&& !MEM_IN_STRUCT_P (operands[0])
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&& !(XINT (XEXP (XEXP (XEXP (operands[0], 0), 0), 1), 0) %4)
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&& GET_CODE (XEXP (operands[2], 0)) == CONST
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&& GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
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&& MEM_SCALAR_P (operands[2])
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&& !MEM_IN_STRUCT_P (operands[2]))
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flag = 2;
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else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
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&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
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&& GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
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&& MEM_SCALAR_P (operands[0])
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&& !MEM_IN_STRUCT_P (operands[0])
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&& !(XINT (XEXP (XEXP (operands[0], 0), 1), 0) %4)
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&& REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
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&& GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
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&& MEM_SCALAR_P (operands[2])
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&& !MEM_IN_STRUCT_P (operands[2]))
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flag = 3;
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else
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return false;
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switch (flag)
|
||||
{
|
||||
case 1:
|
||||
str1 = XSTR (XEXP (operands[0], 0), 0);
|
||||
str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
|
||||
if (strcmp (str1, str2) == 0)
|
||||
okflag = 1;
|
||||
else
|
||||
okflag = 0;
|
||||
break;
|
||||
case 2:
|
||||
str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
|
||||
str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
|
||||
if (strcmp(str1,str2) == 0)
|
||||
okflag = 1;
|
||||
else
|
||||
okflag = 0;
|
||||
break;
|
||||
case 3:
|
||||
offset1 = XINT (XEXP (XEXP (operands[0], 0), 1), 0);
|
||||
offset2 = XINT (XEXP (XEXP (operands[2], 0), 1), 0);
|
||||
offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
|
||||
if (((offset2-offset1) == 2) && offsetsign != 0)
|
||||
okflag = 1;
|
||||
else
|
||||
okflag = 0;
|
||||
break;
|
||||
default:
|
||||
okflag = 0;
|
||||
}
|
||||
|
||||
if (okflag == 1)
|
||||
{
|
||||
HOST_WIDE_INT val;
|
||||
operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
|
||||
|
||||
val = (XINT (operands[3], 0) << 16) + (XINT (operands[1], 0) & 0xFFFF);
|
||||
operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Expanders */
|
||||
|
||||
/* Subregs are non-orthogonal for us, because our registers are all
|
||||
|
|
|
|||
|
|
@ -135,6 +135,17 @@
|
|||
(match_dup 3))]
|
||||
"")
|
||||
|
||||
; Peephole to generate SImode mov instructions for storing an
|
||||
; immediate double data to a memory location.
|
||||
(define_peephole2
|
||||
[(set (match_operand:HI 0 "memory_operand" "")
|
||||
(match_operand 1 "const_int_operand" ""))
|
||||
(set (match_operand:HI 2 "memory_operand" "")
|
||||
(match_operand 3 "const_int_operand" ""))]
|
||||
"TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
|
||||
[(set (match_dup 4) (match_dup 5))]
|
||||
""
|
||||
)
|
||||
|
||||
; Some PSI moves must be split.
|
||||
(define_split
|
||||
|
|
|
|||
Loading…
Reference in New Issue