rs6000.h (MASK_MFCRF): New.
* config/rs6000/rs6000.h (MASK_MFCRF): New. (TARGET_MFCRF): Test target_flags, not processor type. (TARGET_SWITCHES): Add mfcrf and no-mfcrf. Change Don't to Do not. * config/rs6000/rs6000.c (processors_target_table): Add MASK_MFCRF to power4, 970, G5. From-SVN: r74012
This commit is contained in:
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@ -1,3 +1,12 @@
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2003-11-28 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.h (MASK_MFCRF): New.
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(TARGET_MFCRF): Test target_flags, not processor type.
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(TARGET_SWITCHES): Add mfcrf and no-mfcrf.
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Change Don't to Do not.
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* config/rs6000/rs6000.c (processors_target_table): Add MASK_MFCRF
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to power4, 970, G5.
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2003-11-27 J"orn Rennecke <joern.rennecke@superh.com>
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* cse.c (cse_set_around_loop): When changing a constant load
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@ -3598,7 +3607,7 @@
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* config/i386/i386.c (x86_this_parameter): Fix typo.
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203-10-11 Jan Hubicka <jh@suse.cz>
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203-10-11 Jan Hubicka <jh@suse.cz>
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* Makefile.in (web.o): New.
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* web.c: New file.
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@ -645,7 +645,7 @@ rs6000_override_options (const char *default_cpu)
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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POWER_MASKS},
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{"power4", PROCESSOR_POWER4,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
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MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS},
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{"powerpc", PROCESSOR_POWERPC,
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MASK_POWERPC | MASK_NEW_MNEMONICS,
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@ -753,10 +753,10 @@ rs6000_override_options (const char *default_cpu)
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MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
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POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
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{"970", PROCESSOR_POWER4,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS},
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{"G5", PROCESSOR_POWER4,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS,
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MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
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POWER_MASKS}};
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const size_t ptt_size = ARRAY_SIZE (processor_target_table);
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@ -187,7 +187,10 @@ extern int target_flags;
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/* Return small structures in memory (as the AIX ABI requires). */
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#define MASK_AIX_STRUCT_RET 0x00040000
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/* The only remaining free bits are 0x00780000. sysv4.h uses
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/* Use single field mfcr instruction. */
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#define MASK_MFCRF 0x00080000
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/* The only remaining free bits are 0x00700000. sysv4.h uses
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0x00800000 -> 0x40000000, and 0x80000000 is not available
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because target_flags is signed. */
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@ -210,6 +213,17 @@ extern int target_flags;
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#define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
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#define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
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/* Define TARGET_MFCRF if the target assembler supports the optional
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field operand for mfcr and the target processor supports the
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instruction. */
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#ifdef HAVE_AS_MFCRF
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#define TARGET_MFCRF (target_flags & MASK_MFCRF)
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#else
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#define TARGET_MFCRF 0
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#endif
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#define TARGET_32BIT (! TARGET_64BIT)
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#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
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#define TARGET_UPDATE (! TARGET_NO_UPDATE)
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@ -259,19 +273,19 @@ extern int target_flags;
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{"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
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N_("Use PowerPC General Purpose group optional instructions")},\
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{"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
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N_("Don't use PowerPC General Purpose group optional instructions")},\
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N_("Do not use PowerPC General Purpose group optional instructions")},\
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{"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
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N_("Use PowerPC Graphics group optional instructions")},\
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{"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
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N_("Don't use PowerPC Graphics group optional instructions")},\
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N_("Do not use PowerPC Graphics group optional instructions")},\
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{"powerpc64", MASK_POWERPC64, \
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N_("Use PowerPC-64 instruction set")}, \
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{"no-powerpc64", - MASK_POWERPC64, \
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N_("Don't use PowerPC-64 instruction set")}, \
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N_("Do not use PowerPC-64 instruction set")}, \
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{"altivec", MASK_ALTIVEC , \
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N_("Use AltiVec instructions")}, \
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{"no-altivec", - MASK_ALTIVEC , \
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N_("Don't use AltiVec instructions")}, \
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N_("Do not use AltiVec instructions")}, \
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{"new-mnemonics", MASK_NEW_MNEMONICS, \
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N_("Use new mnemonics for PowerPC architecture")},\
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{"old-mnemonics", -MASK_NEW_MNEMONICS, \
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@ -282,11 +296,11 @@ extern int target_flags;
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{"fp-in-toc", - MASK_NO_FP_IN_TOC, \
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N_("Place floating point constants in TOC")}, \
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{"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
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N_("Don't place floating point constants in TOC")},\
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N_("Do not place floating point constants in TOC")},\
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{"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
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N_("Place symbol+offset constants in TOC")}, \
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{"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
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N_("Don't place symbol+offset constants in TOC")},\
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N_("Do not place symbol+offset constants in TOC")},\
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{"minimal-toc", MASK_MINIMAL_TOC, \
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"Use only one TOC entry per procedure"}, \
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{"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
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@ -294,9 +308,9 @@ extern int target_flags;
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{"no-minimal-toc", - MASK_MINIMAL_TOC, \
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N_("Place variable addresses in the regular TOC")},\
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{"hard-float", - MASK_SOFT_FLOAT, \
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N_("Use hardware fp")}, \
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N_("Use hardware floating point")}, \
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{"soft-float", MASK_SOFT_FLOAT, \
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N_("Do not use hardware fp")}, \
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N_("Do not use hardware floating point")}, \
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{"multiple", MASK_MULTIPLE, \
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N_("Generate load/store multiple instructions")}, \
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{"no-multiple", - MASK_MULTIPLE, \
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@ -312,11 +326,11 @@ extern int target_flags;
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{"fused-madd", - MASK_NO_FUSED_MADD, \
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N_("Generate fused multiply/add instructions")},\
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{"no-fused-madd", MASK_NO_FUSED_MADD, \
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N_("Don't generate fused multiply/add instructions")},\
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N_("Do not generate fused multiply/add instructions")},\
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{"sched-prolog", MASK_SCHED_PROLOG, \
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""}, \
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{"no-sched-prolog", -MASK_SCHED_PROLOG, \
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N_("Don't schedule the start and end of the procedure")},\
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N_("Do not schedule the start and end of the procedure")},\
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{"sched-epilog", MASK_SCHED_PROLOG, \
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""}, \
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{"no-sched-epilog", -MASK_SCHED_PROLOG, \
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{"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
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N_("Return small structures in registers (SVR4 default)")},\
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{"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
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""},\
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""}, \
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{"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
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""},\
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""}, \
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{"mfcrf", MASK_MFCRF, \
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N_("Generate single field mfcr instruction")}, \
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{"no-mfcrf", - MASK_MFCRF, \
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N_("Do not generate single field mfcr instruction")},\
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SUBTARGET_SWITCHES \
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{"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
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""}}
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@ -529,16 +547,6 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
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#define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
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(rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
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/* Define TARGET_MFCRF if the target assembler supports the optional
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field operand for mfcr and the target processor supports the
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instruction. */
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#ifdef HAVE_AS_MFCRF
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#define TARGET_MFCRF (rs6000_cpu == PROCESSOR_POWER4)
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#else
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#define TARGET_MFCRF 0
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#endif
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#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
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#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
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#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
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defined, is executed once just after all the command options have
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been parsed.
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Don't use this macro to turn on various extra optimizations for
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Do not use this macro to turn on various extra optimizations for
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`-O'. That is what `OPTIMIZATION_OPTIONS' is for.
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On the RS/6000 this is used to define the target cpu type. */
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