In PR 69577 we have:
A: (set (reg:V2TI X) ...)
B: (set (subreg:TI (reg:V2TI X) 0) ...)
X gets allocated to an AVX register, as usual for V2TI. The problem is
that the movti for B doesn't then preserve the other half of X, even
though the subreg semantics are supposed to guarantee that.
If instead the same value had been set by:
A': (set (subreg:TI (reg:V2TI X) 16) ...)
B: (set (subreg:TI (reg:V2TI X) 0) ...)
the subreg in A' would have prevented the use of AVX registers for X,
since you can't directly access the high part.
IMO these are really the same thing. An alternative way to view it
is that the original sequence is equivalent to:
A: (set (reg:V2TI X) ...)
B1: (set (subreg:TI (reg:V2TI X) 0) ...)
B2: (set (subreg:TI (reg:V2TI X) 16) (subreg:TI (reg:V2TI X) 16))
in which B2 is a no-op and therefore implicit. The handling ought
to be the same regardless of whether there is an rtl insn that
explicitly assigns to (subreg:TI (reg:V2TI X) 16).
This patch implements that idea. Hopefully the comments explain
what's going on.
Tested on x86_64-linux-gnu, aarch64-linux-gnu and arm-linux-gnueabihf.
gcc/
PR rtl-optimization/69577
* reginfo.c (record_subregs_of_mode): Add a partial_def parameter.
(find_subregs_of_mode): Update accordingly. Iterate over partial
definitions.
gcc/testsuite/
PR rtl-optimization/69577
* gcc.target/i386/pr69577.c: New test.
From-SVN: r233143
PR target/65932
PR target/67714
* gcc.target/arm/wmul-3.c: Simplify test to generate just
a single smulbb instruction.
* gcc.target/amr/wmul-1.c: Add -mtune=cortex-a9 to dg-options.
* gcc.target/amr/wmul-2.c: Likewise.
From-SVN: r233134
PR target/65932
PR target/67714
* config/arm/arm.c (arm_new_rtx_costs, MULT case): Properly extract
the operands of the SIGN_EXTENDs from a SMUL[TB][TB] rtx.
From-SVN: r233132
2016-02-04 Jim Wilson <jim.wilson@linaro.org>
PR target/65932
PR target/67714
* config/arm/arm.h (PROMOTE_MODE): Don't set UNSIGNEDP for QImode and
HImode.
From-SVN: r233130
PR target/69454
* config/i386/i386.c (convert_scalars_to_vector): Remove
stack alignment fixes.
(ix86_option_override_internal): Disable TARGET_STV if stack
might not be aligned enough.
(ix86_minimum_alignment): Assert that TARGET_STV is false.
* gcc.target/i386/pr69454-1.c: New test.
* gcc.target/i386/pr69454-2.c: New test.
From-SVN: r233128
* gcc.target/i386/iamcu/test_passing_unions.c (check_union_passing6):
Define only if CHECK_FLOAT128 is defined.
(main): Properly initialize u5.
From-SVN: r233124
PR target/69644
* config/rs6000/rs6000.c (rs6000_expand_atomic_compare_and_swap):
Force oldval into register if it does not satisfy reg_or_short_operand
predicate. Fix up formatting.
* gcc.dg/pr69644.c: New test.
From-SVN: r233113
2016-02-03 Andreas Tobler <andreast@gcc.gnu.org>
PR bootstrap/69611
* config/rs6000/sfp-machine.h: Guard __sfp_exceptions with
__FLOAT128__ to compile only for __float128 capable targets.
From-SVN: r233111
gcc/cp/ChangeLog:
PR c++/69056
* pt.c (try_one_overload): Handle comparing argument packs so
that there is no conflict if we deduced more arguments of an
argument pack than were explicitly specified.
gcc/testsuite/ChangeLog:
PR c++/69056
g++.dg/cpp0x/pr69056.C: New test.
From-SVN: r233108
* lib/tsan-dg.exp (tsan_init): Move check if tsan executable
works from here ...
(check_effective_target_fsanitize_thread): ... to here. Do not
specify additional compile flags for the test source.
* lib/asan-dg.exp (check_effective_target_fsanitize_address): Do not
specify additional compile flags for the test source.
From-SVN: r233106
Fix the ccmp_1.c test back to use '0' as regular expressions don't work
correctly. '0' is right due to compare with zero now printing as
'CMP w0, 0' rather than 'CMP w0, wzr'.
2016-02-03 Wilco Dijkstra <wdijkstr@arm.com>
gcc/testsuite/
* gcc.target/aarch64/ccmp_1.c: Fix test issue.
From-SVN: r233102
gcc/testsuite/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* gfortran.dg/coarray_allocate_2.f08: New test.
* gfortran.dg/coarray_allocate_3.f08: New test.
* gfortran.dg/coarray_allocate_4.f08: New test.
gcc/fortran/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* trans-expr.c (gfc_copy_class_to_class): For coarrays just the
pointer is passed. Take it as is without trying to deref the
_data component.
* trans-stmt.c (gfc_trans_allocate): Take care of coarrays as
argument to source=-expression.
From-SVN: r233101
This fixes the long-standing bug in which the testing package misreports
the file/line of an error.
Reviewed-on: https://go-review.googlesource.com/19179
From-SVN: r233098
vector-compare-4.c
This testcase fails on 32-bit powerpc-linux with
Excess errors:
/home/segher/src/gcc/gcc/testsuite/c-c++-common/vector-compare-4.c:31:1: warning: GCC vector returned by reference: non-standard ABI extension with no compatibility guarantee
Fix this as in vector-compare-2.c .
testsuite/
* c-c++-common/vector-compare-4.c: Prune "non-standard ABI extension"
warning.
From-SVN: r233093
Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook. It turns out there
is another case where the register allocator uses the union of register classes
without checking that the cost of the resulting register class is lower than
both (see https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01765.html ). This
happens when the cost of the best and alternative class are both lower than the
memory cost. In this case we typically end up with ALL_REGS as the allocno
class, which almost invariably results in bad allocations with many redundant
int<->FP moves (which are expensive on various cores). AArch64 is affected by
this significantly due to supporting many scalar integer operations in SIMD.
Currently the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook forces the class to
GENERAL_REGS if the allocno class is ALL_REGS and the register has an integer
mode. This is bad if the best class happens to be FP_REGS. To handle this
case as well, an extra argument is needed in the hook to pass the best class.
If the allocno class is ALL_REGS, but the best class isn't, we use the best
class instead (rather than using the mode to force to GENERAL_REGS or FP_REGS).
Previously this might happen:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno GENERAL_REGS
a1 (r79,l0) best GENERAL_REGS, allocno GENERAL_REGS
a1(r79,l0) costs: CALLER_SAVE_REGS:5000,5000 GENERAL_REGS:5000,5000
FP_LO_REGS:0,0 FP_REGS:0,0 ALL_REGS:10000,10000 MEM:9000,9000
The proposed allocno is ALL_REGS (despite having the highest cost!) and is then
forced by the hook to GENERAL_REGS because r79 has integer mode. However
FP_REGS has the lowest cost. After this patch the choice is as follows:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno FP_REGS
a1 (r79,l0) best FP_REGS, allocno FP_REGS
As a result it is now no longer a requirement to use register move costs that
are larger than the memory move cost. So it will be feasible to use realistic
costs for both without a huge penalty.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* ira-costs.c (find_costs_and_classes): Add extra argument.
* target.def (ira_change_pseudo_allocno_class): Add parameter.
* targhooks.h (ira_change_pseudo_allocno_class): Likewise.
* targhooks.c (ira_change_pseudo_allocno_class): Likewise.
* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class)
Add best_class parameter, and return it if not ALL_REGS.
* config/mips/mips.c (mips_ira_change_pseudo_allocno_class):
Add parameter.
* doc/tm.texi (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS):
Update target hook.
From-SVN: r233084
When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* config/aarch64/aarch64.c
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
(aarch64_ira_change_pseudo_allocno_class): New function.
gcc/testsuite/
* gcc.target/aarch64/scalar_shift_1.c
(test_corners_sisd_di): Improve force to SIMD register.
(test_corners_sisd_si): Likewise.
* gcc.target/aarch64/vect-ld1r-compile-fp.c:
Remove scan-assembler check for ldr.
From-SVN: r233083
2016-02-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/69595
* match.pd: Add range test simplifications to true/false.
* gcc.dg/Warray-bounds-17.c: New testcase.
From-SVN: r233076
