This patch updates MOVE_RATIO cost for IA MCU from 6 to 9 so that we
can unroll the loop completely for DOM with -mtune=iamcu.
gcc/
PR target/67329
* config/i386/i386.c (iamcu_cost): Set MOVE_RATIO cost to 9.
gcc/testsuite/
PR target/67329
* gcc.target/i386/pr67329.c: New test.
From-SVN: r227132
2015-08-24 Tom de Vries <tom@codesourcery.com>
PR tree-optimization/65468
* omp-low.c (expand_omp_for_static_chunk): Remove inner loop if
chunk_size is one.
* gcc.dg/gomp/static-chunk-size-one.c: New test.
* testsuite/libgomp.c/static-chunk-size-one.c: New test.
From-SVN: r227124
* config/nvptx/nvptx.c (walk_args_for_param): Revert previous
change to nvptx_type_from_mode call. Use arg_promotion for both
split and non-split args.
From-SVN: r227123
gcc/
* target-insns.def (movstr): New pattern.
* builtins.c (HAVE_movstr, CODE_FOR_movstr): Delete.
(expand_movstr): Use targetm rather than HAVE_movstr/
CODE_FOR_movstr.
From-SVN: r227121
2015-08-24 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-tuning-flags.def: Remove all index to
AARCH64_EXTRA_TUNING_OPTION.
* config/aarch64/aarch64-protos.h (aarch64_extra_tuning_flags_index): New enum.
(aarch64_extra_tuning_flags): Base the shifted value on the index instead
of the argument to AARCH64_EXTRA_TUNING_OPTION.
* config/aarch64/aarch64.c: Remove the last argument to
AARCH64_EXTRA_TUNING_OPTION.
From-SVN: r227117
2015-08-23 Tom de Vries <tom@codesourcery.com>
* omp-low.c (expand_omp_taskreg): If in ssa, set rhs of parcopy stmt to
parm_decl, rather than generating a dummy default def in cfun.
* tree-cfg.c (replace_ssa_name): Assume no default defs. Make sure
ssa_name from cfun and child_fn do not share a stmt as def stmt.
(move_stmt_op): Handle PARM_DECl.
(gather_ssa_name_hash_map_from): New function.
(move_sese_region_to_fn): Add default defs for function params, and add
them to vars_map. Release copied ssa names.
* tree-cfg.h (gather_ssa_name_hash_map_from): Declare.
From-SVN: r227103
Instead of doing an explict index in aarch64-fusion-pairs.def, we
should have an enum which does the index instead. This allows
you to add/remove them without worrying about the order being
correct and having holes or worry about merge conficts.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
ChangeLog:
* aarch64-fusion-pairs.def: Remove all index to AARCH64_FUSION_PAIR.
* config/aarch64/aarch64-protos.h (aarch64_fusion_pairs_index): New enum.
(aarch64_fusion_pairs): Base the shifted value on the index instead
Rewrite AARCH64_FUSE_ALL to be based on the end index.
of the argument to AARCH64_FUSION_PAIR.
* config/aarch64/aarch64.c: Remove the last argument to AARCH64_FUSION_PAIR.
From-SVN: r227094
gcc/
* dominance.c (new_zero_array): Define.
(dom_info): Redefine as class with proper encapsulation.
(dom_info::m_n_basic_blocks, m_reverse, m_start_block, m_end_block):
Add new members.
(dom_info::dom_info, ~dom_info): Define. Use new/delete for memory
allocations/deallocations. Pass function as parameter (instead of
using cfun).
(dom_info::get_idom): Define accessor method.
(dom_info::calc_dfs_tree_nonrec, calc_dfs_tree, compress, eval,
link_roots, calc_idoms): Redefine as class members. Do not use cfun.
(calculate_dominance_info): Adjust to use dom_info class.
(verify_dominators): Likewise.
From-SVN: r227093
for gcc/ChangeLog
PR rtl-optimization/64164
PR rtl-optimization/67227
* alias.c (memrefs_conflict_p): Handle VALUEs in PLUS better.
(nonoverlapping_memrefs_p): Test offsets and sizes when given
identical gimple_reg exprs.
From-SVN: r227085
gcc/
* gencodes.c (gencodes): Print the comma for the preceding
enum value rather than the current one. Use aliased enum values
rather than #defines for compiled-out patterns.
(main): Update accordingly. Replace LAST_INSN_CODE with
NUM_INSN_CODES.
* lra.c (insn_code_data): Update accordingly.
(finish_insn_code_data_once, get_static_insn_data): Likewise.
* recog.h (target_recog): Likewise.
(preprocess_insn_constraints): Change parameter to unsigned int.
* recog.c (preprocess_insn_constraints): Likewise.
(recog_init): Replace LAST_INSN_CODE with NUM_INSN_CODES.
* tree-vect-stmts.c (vectorizable_operation): Simplify.
From-SVN: r227076
bootstrap-ubsan shows:
loop-iv.c:2626:14: runtime error: signed integer overflow: 9223372036854775806 - -9223372036854775808 cannot be represented in type 'long int'
Fixed by moving the variables in question from signed to unsigned.
PR rtl-optimization/61657
* loop-iv.c (iv_number_of_iterations): Declare up and down as
unsigned. Remove superflous uint64_t cast.
From-SVN: r227075
2015-08-21 Richard Biener <rguenther@suse.de>
PR middle-end/67285
* gimple-fold.c (replace_stmt_with_simplification): Assert
seq is empty when replacing a call with itself but different
arguments.
* gimple-match-head.c (maybe_push_res_to_seq): When pushing
a call require that it is const.
From-SVN: r227053
gcc/ChangeLog:
2015-08-20 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* reorg.c (relax_delay_slots): Don't use #if to check value of
HAVE_cc0.
From-SVN: r227050
[gcc]
2015-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.h (vec_pmsum_be): New #define.
(vec_shasigma_be): New #define.
* config/rs6000/rs6000-builtin.def (VPMSUMB): New BU_P8V_AV2_2.
(VPMSUMH): Likewise.
(VPMSUMW): Likewise.
(VPMSUMD): Likewise.
(VPMSUM): New BU_P8V_OVERLOAD_2.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): New
entries for VEC_MADD and VEC_VPMSUM.
[gcc/testsuite]
2015-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/altivec-35.c (foo): Add tests for vec_madd.
* gcc.target/powerpc/p8vector-builtin-8.c (foo): Add tests for
vec_vpmsum_be and vec_shasigma_be.
From-SVN: r227036
* config/avr/avr.c (avr_insert_attributes): In diagnostic essage:
Multiply argument avr_n_flash by 64 to match unit of "KiB".
(avr_pgm_check_var_decl): Same.
From-SVN: r227035
2015-08-20 Richard Biener <rguenther@suse.de>
* toplev.c (compile_file): Remove loop calling late_global_decl
on all symbols.
* varpool.c (varpool_node::assemble_decl): Call late_global_decl
on decls we assembled.
From-SVN: r227031
gcc/
* config/mips/mips.c (mips_expand_block_move): Enable inline memcpy
expansion when !ISA_HAS_LWL_LWR.
(mips_block_move_straight): Update the size of elements copied to
account for alignment when !ISA_HAS_LWL_LWR.
* config/mips/mips.h (MIPS_MIN_MOVE_MEM_ALIGN): New macro.
gcc/testsuite/
* inline-memcpy-1.c: Test for inline expansion of memcpy.
* inline-memcpy-2.c: Ditto.
* inline-memcpy-3.c: Ditto.
* inline-memcpy-4.c: Ditto.
* inline-memcpy-5.c: Ditto.
From-SVN: r227026
This patch improves LSHIFT_EXP expand if the shift operand comes from sign
extension and the shift result across word_mode_size boundary. See code
comments for details.
2015-08-19 Jiong.Wang <jiong.wang@arm.com>
gcc/
* expr.c (expand_expr_real_2): Check gimple statement during
LSHIFT_EXPR expand.
gcc/testsuite
* gcc.dg/wide_shift_64_1.c: New testcase.
* gcc.dg/wide_shift_128_1.c: Likewise.
* gcc.target/aarch64/ashlti3_1.c: Likewise.
From-SVN: r227018
Defer stack slot address assignment for all parms that can't live in
pseudos, and accept pseudos assignments in assign_param_setup_block.
for gcc/ChangeLog
PR rtl-optimization/64164
* cfgexpand.c (parm_maybe_byref_p): Renamed to...
(parm_in_stack_slot_p): ... this. Disregard mode, what
matters is whether the parm will live in a pseudo or a stack
slot.
(expand_one_ssa_partition): Deal with params without a default
def. Disregard mode.
* cfgexpand.h: Renamed function declaration.
* tree-ssa-coalesce.c: Adjust.
* function.c (split_complex_args): Allocate stack slot for
unassigned parms before splitting.
(parm_in_unassigned_mem_p): New. Use it instead of
parm_maybe_byref_p throughout this file.
(assign_parm_setup_block): Use it. Accept pseudos in the
expand-assigned rtl.
(assign_parm_setup_reg): Drop BLKmode requirement.
(assign_parm_setup_stack): Allocate and fill in the address of
unassigned MEM parms.
From-SVN: r227015
2015-08-19 David Sherwood <david.sherwood@arm.com>
gcc/
* genmodes.c (emit_mode_unit_size_inline): New function.
(emit_mode_unit_precision_inline): New function.
(emit_insn_modes_h): Emit new #define. Emit new functions.
(emit_mode_unit_size): New function.
(emit_mode_unit_precision): New function.
(emit_mode_adjustments): Add mode_unit_size adjustments.
(emit_insn_modes_c): Emit new arrays.
* machmode.h (GET_MODE_UNIT_SIZE, GET_MODE_UNIT_PRECISION): Update to
use new inline methods.
From-SVN: r227013
* config/aarch64/aarch64.c (bit_count): Delete prototype
and definition.
(aarch64_print_operand): Use popcount_hwi instead of the above.
From-SVN: r227012
gcc/
PR other/67042
* hwint.h (sext_hwi): Switch to unsigned for the left shift, and
conditionalize the whole on __GNUC__. Add fallback code
depending neither on undefined nor implementation-defined behaviour.
From-SVN: r227008
Due to PR67205, the deeply nested instantiations require trampolines,
which in turn requires an executable stack for the GNAT tools on
architectures such as x86_64.
From-SVN: r227004
Nathan Sidwell
H.J. Lu
Renlin Li
Tom de Vries
Nathan Sidwell
Richard Sandiford
Andrew Pinski
Mikhail Maltsev
Alexandre Oliva
Francois-Xavier Coudert
Markus Trippelsdorf
Felix Yang
Dominik Vogt
Naveen H.S
Bin Cheng
Yury Gribov
Richard Biener
Trevor Saunders
Bill Schmidt
Georg-Johann Lay
Alan Lawrence
James Greenhalgh
Simon Dardis
Jiong Wang
Magnus Granberg
David Sherwood
Kyrylo Tkachov
Marek Polacek
Mikael Morin
Florian Weimer
Uros Bizjak