PR c++/87386
* parser.c (cp_parser_primary_expression): Use
id_expression.get_location () instead of id_expr_token->location.
Adjust the range from id_expr_token->location to
id_expressio.get_finish ().
(cp_parser_operator_function_id): Pass location of the operator
token down to cp_parser_operator.
(cp_parser_operator): Add start_loc argument, always construct a
location with caret at start_loc and range from start_loc to the
finish of the last token.
gcc/testsuite/
* g++.dg/diagnostic/pr87386.C: New test.
* g++.dg/parse/error17.C: Adjust expected diagnostics.
libstdc++-v3/
* testsuite/20_util/scoped_allocator/69293_neg.cc: Adjust expected
line.
* testsuite/20_util/uses_allocator/cons_neg.cc: Likewise.
* testsuite/20_util/uses_allocator/69293_neg.cc: Likewise.
* testsuite/experimental/propagate_const/requirements2.cc: Likewise.
* testsuite/experimental/propagate_const/requirements3.cc: Likewise.
* testsuite/experimental/propagate_const/requirements4.cc: Likewise.
* testsuite/experimental/propagate_const/requirements5.cc: Likewise.
From-SVN: r266359
PR rtl-optimization/85925
* gcc.c-torture/execute/20181120-1.c: Require effective target
int32plus.
(u): New variable.
(main): Compare d against u.f1 rather than 0x101. Use 0x4030201
instead of 0x10101.
From-SVN: r266357
PR libstdc++/88111
* include/std/memory_resource (pool_options): Add Doxygen comments.
* src/c++17/memory_resource.cc (pool_sizes): Only use suitable values
on targets with 16-bit or 20-bit size_t type.
(munge_options): Make default values depend on width of size_t type.
From-SVN: r266353
On 16-bit msp430-elf size_t is either 16 bits or 20 bits, and so can't
represent all values of the uint32_t type used for bitset::size_type.
Using the smaller of size_t and uint32_t for size_type ensures it fits
in size_t.
PR libstdc++/88113
* src/c++17/memory_resource.cc (bitset::size_type): Use the smaller
of uint32_t and size_t.
(bitset::size(), bitset::free(), bitset::update_next_word())
(bitset::max_blocks_per_chunk(), bitset::max_word_index()): Use
size_type consistently instead of size_t.
(chunk): Adjust static_assert checking sizeof(chunk).
From-SVN: r266352
PR lto/87957
* tree.c (fld_decl_context): Break out from ...
(free_lang_data_in_decl): ... here; free TREE_PUBLIC, TREE_PRIVATE
DECL_ARTIFICIAL of TYPE_DECL; do not free TREE_TYPE of TYPE_DECL.
(fld_incomplete_type_of): Build copy of TYP_DECL.
* ipa-devirt.c (free_enum_values): Rename to ...
(free_odr_warning_data): ... this one; free also duplicated TYPE_DECLs
and TREE_TYPEs of TYPE_DECLs.
(get_odr_type): Initialize odr_vtable_hash if needed.
From-SVN: r266350
In some cases of overriding or resetting locations, we might retain
discriminator info from earlier locations, when we should take
discriminator information from the overriding location or reset it.
for gcc/ChangeLog
* final.c (compute_discriminator): Declare. Renamed from...
(maybe_set_discriminator): ... this. Set and return a local.
(override_discriminator): New.
(final_scan_insn_1): Set it.
(notice_source_line): Adjust. Always set discriminator.
From-SVN: r266349
PR target/87839
* config/aarch64/atomics.md (@aarch64_compare_and_swap<mode>): Use
rIJ constraint for aarch64_plus_operand rather than rn.
* gcc.target/aarch64/pr87839.c: New test.
From-SVN: r266346
As described in PR84877. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84877
The local copy of parameter on stack is not aligned.
For BLKmode paramters, a local copy on the stack will be saved.
There are three cases:
1) arguments passed partially on the stack, partially via registers.
2) arguments passed fully on the stack.
3) arguments passed via registers.
After the change here, in all three cases, the stack slot for the local
parameter copy is aligned by the data type.
The stack slot is the DECL_RTL of the parameter. All the references thereafter
in the function will refer to this RTL.
To populate the local copy on the stack,
For case 1) and 2), there are operations to move data from the caller's stack
(from incoming rtl) into callee's stack.
For case 3), the registers are directly saved into the stack slot.
In all cases, the destination address is properly aligned.
But for case 1) and case 2), the source address is not aligned by the type.
It is defined by the PCS how the arguments are prepared.
The block move operation is fulfilled by emit_block_move (). As far as I can see,
it will use the smaller alignment of source and destination.
This looks fine as long as we don't use instructions which requires a strict
larger alignment than the address actually has.
Here, it only changes receiving parameters.
The function assign_stack_local_1 will be called in various places.
Usually, the caller will constraint the ALIGN parameter.
For example via STACK_SLOT_ALIGNMENT macro.
assign_parm_setup_block will call assign_stack_local () with alignment from the
parameter type which in this case could be
larger than MAX_SUPPORTED_STACK_ALIGNMENT.
The alignment operation for parameter copy on the stack is similar to stack vars.
First, enough space is reserved on the stack. The size is fixed at compile time.
Instructions are emitted to dynamically get an aligned address at runtime
within this piece of memory.
This will unavoidably increase the usage of stack. However, it really depends on
how many over-aligned parameters are passed by value.
gcc/
2018-11-21 Renlin Li <renlin.li@arm.com>
PR middle-end/84877
* explow.h (get_dynamic_stack_size): Declare it as external.
* explow.c (record_new_stack_level): Remove function static attribute.
* function.c (assign_stack_local_1): Dynamically align the stack slot
addr for parameter copy on the stack.
gcc/testsuite/
2018-11-21 Renlin Li <renlin.li@arm.com>
PR middle-end/84877
* gcc.dg/pr84877.c: New.
From-SVN: r266345
PR rtl-optimization/87817
* config/i386/i386.md (bmi2_bzhi_<mode>3, *bmi2_bzhi_<mode>3,
*bmi2_bzhi_<mode>3_1, *bmi2_bzhi_<mode>3_1_ccz): Use IF_THEN_ELSE
in the pattern to avoid triggering UB when operands[2] is zero.
(tbm_bextri_<mode>): New expander. Renamed the old define_insn to ...
(*tbm_bextri_<mode>): ... this.
From-SVN: r266340
Factor out new function read_string in dwarf.c.
Bootstrapped and reg-tested on x86_64.
2018-11-21 Tom de Vries <tdevries@suse.de>
* dwarf.c (read_string): Factor out of ...
(read_attribute, read_line_header, read_line_program): ... here.
From-SVN: r266339
Ensure that gcc --help=params lines end with a period by:
- fixing the help message of param HOT_BB_COUNT_FRACTION, and
- adding a test-case.
Build and tested on x86_64.
2018-11-21 Tom de Vries <tdevries@suse.de>
PR driver/79855
* params.def (HOT_BB_COUNT_FRACTION): Terminate help message with
period.
* lib/options.exp (check_for_options_with_filter): New proc.
* gcc.misc-tests/help.exp: Check that --help=params lines end with
period.
From-SVN: r266338
* lang.opt (fdec-include): New option.
* options.c (set_dec_flags): Set also flag_dec_include.
* scanner.c (include_line): Change return type from bool to int.
In fixed form allow spaces in between include keyword letters.
For -fdec-include, allow in fixed form 0 in column 6. With
-fdec-include return -1 if the parsed line is not full include
statement and it could be successfully completed on continuation
lines.
(include_stmt): New function.
(load_file): Adjust include_line caller. If it returns -1, keep
trying include_stmt until it stops returning -1 whenever adding
further line of input.
* gfortran.dg/include_10.f: New test.
* gfortran.dg/include_10.inc: New file.
* gfortran.dg/include_11.f: New test.
* gfortran.dg/include_12.f: New test.
* gfortran.dg/include_13.f90: New test.
* gfortran.dg/gomp/include_1.f: New test.
* gfortran.dg/gomp/include_1.inc: New file.
* gfortran.dg/gomp/include_2.f90: New test.
Co-Authored-By: Mark Eggleston <mark.eggleston@codethink.com>
From-SVN: r266337
The IBM z14 POP adds an optional alignment operand to the vl, vst,
vlm, and vstm instruction (vector loads and stores). Vectors residing
on 8 or 16 byte boundaries might get loaded or stored faster on some
models given the instruction uses the proper hint operand. A wrong
hint will hurt performance though.
The attached testcase align-1 currently fails due to:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88085
gcc/ChangeLog:
2018-11-21 Andreas Krebbel <krebbel@linux.ibm.com>
* configure.ac: Add check for Binutils to determine whether vector
load/store alignments hints are being supported.
* config.in: Regenerate.
* configure: Regenerate.
* config/s390/s390.c (print_operand): Support new output
modifier A.
* config/s390/s390.md ("movti"): Append alignment hint output
using the new output modifier 'A'.
* config/s390/vector.md ("mov<mode>", "*vec_tf_to_v1tf")
("*vec_ti_to_v1ti"): Likewise.
gcc/testsuite/ChangeLog:
2018-11-21 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/vector/align-1.c: New test.
* gcc.target/s390/vector/align-2.c: New test.
From-SVN: r266336
PR go/88060
syscall: always define _AT_FDCWD and IPv6MTUInfo
They aren't defined by old versions of glibc, but are required by the
code in syscall_linux.go.
Reviewed-on: https://go-review.googlesource.com/c/150697
From-SVN: r266333
PR c++/88110
* constexpr.c (cxx_eval_constant_expression) <case OBJ_TYPE_REF>: Punt
if get_base_address of ADDR_EXPR operand is not a DECL_P.
* g++.dg/cpp2a/constexpr-virtual13.C: New test.
From-SVN: r266329
PR tree-optimization/87895
* omp-simd-clone.c (ipa_simd_modify_function_body): When removing
or replacing GIMPLE_RETURN, set EDGE_FALLTHRU on the edge to EXIT.
(simd_clone_adjust): Don't set EDGE_FALLTHRU here. In a loop that
redirects edges to EXIT to edges to incr_bb, iterate while EXIT
has any preds and always use EDGE_PRED (, 0).
* gcc.dg/gomp/pr87895-1.c: New test.
* gcc.dg/gomp/pr87895-2.c: New test.
* gcc.dg/gomp/pr87895-3.c: New test.
From-SVN: r266328
PR target/88070
* mode-switching.c (create_pre_exit): After reload, always split the
fallthrough edge to the exit block.
testsuite/ChangeLog:
PR target/88070
* gcc.target/i386/pr88070.c: New test.
From-SVN: r266326
PR lto/87957
* ipa-devirt.c (odr_subtypes_equivalent_p): Report ODR violation
when sybtype already violates ODR.
(get_odr_type): Do not ICE when insert is false and type duplicate
is not registered yet.
(register_odr_type): Be sure to register subtypes first.
From-SVN: r266322
The flogr instruction uses a 64 bit register pair target operand. In
the RTX we model this as a write to a TImode register. Unfortunately
the RTX's being assigned to the two parts of the target operand were
swapped. This is no problem if in the end the flogr instruction will
be emitted since the instruction still does what the clzdi expander
expects. However, a problem arises when the RTX is used to optimize
CLZ for a constant input operand. Even then it matters only if the
expression couldn't be folded on tree level already.
In the testcase this happened thanks to loop unrolling on RTL level.
The iteration variable is used as an argument to the clz
builtin. Due to the loop unrolling it becomes a constant and after
folding the broken RTX leads to a wrong assumption.
gcc/ChangeLog:
2018-11-20 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.md ("clztidi2"): Swap the RTX's written to the
DImode parts of the target operand.
gcc/testsuite/ChangeLog:
2018-11-20 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/flogr-1.c: New test.
From-SVN: r266321
PR ipa/87706
* ipa-fnsummary.c (pass_ipa_fnsummary): Do not remove functions
* ipa.c (possible_inline_candidate_p): Break out from ..
(process_references): ... here ; drop before_inlining_p;
cleanup handling of alises.
(walk_polymorphic_call_targets): Likewise.
(symbol_table::remove_unreachable_nodes): Likewise.
* passes.c (pass_data_ipa_remove_symbols): New structure.
(pass_ipa_remove_symbols): New pass.
(make_pass_ipa_remove_symbols): New function.
* tree-pass.h (make_pass_ipa_remove_symbols): Declare.
* passes.def (pass_ipa_remove_symbols): Schedule after early passes.
From-SVN: r266320
PR ipa/87706
* ipa-fnsummary.c (pass_ipa_fnsummary): Do not remove functions
* ipa.c (possible_inline_candidate_p): Break out from ..
(process_references): ... here ; drop before_inlining_p;
cleanup handling of alises.
(walk_polymorphic_call_targets): Likewise.
(symbol_table::remove_unreachable_nodes): Likewise.
* passes.c (pass_data_ipa_remove_symbols): New structure.
(pass_ipa_remove_symbols): New pass.
(make_pass_ipa_remove_symbols): New functoin.
* passes.def (pass_ipa_remove_symbols): Schedule after early passes.
From-SVN: r266315
2018-11-20 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.c (vectorizable_condition): Do not get
at else_clause vect def for EXTRACT_LAST_REDUCTION. Remove
pointless vect_is_simple_use calls.
From-SVN: r266314
2018-11-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/88074
* tree-ssa-dom.c (pass_dominator::execute): Do not walk
backedges.
* gcc.dg/pr88074.c: New testcase.
From-SVN: r266313
2018-11-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/88069
* tree-ssa-sccvn.c (visit_phi): Do not value-number to unvisited
virtual PHI arguments.
* gcc.dg/pr88069.c: New testcase.
From-SVN: r266308
By the time peephole optimizations run, we've already made up our mind
whether to use base-register or relative addressing for literal pool
entries. LT(G) supports only base-register addressing, and so it is
too late to convert L(G)RL + compare to LT(G). This change should not
make the code worse unless building with e.g. -fno-dce, since comparing
literal pool entries to zero should be optimized away during earlier
passes.
gcc/ChangeLog:
2018-11-20 Ilya Leoshkevich <iii@linux.ibm.com>
PR target/88083
* config/s390/s390.md: Skip LT(G) peephole when literal pool is
involved.
* rtl.h (contains_constant_pool_address_p): New function.
* rtlanal.c (contains_constant_pool_address_p): Likewise.
gcc/testsuite/ChangeLog:
2018-11-20 Ilya Leoshkevich <iii@linux.ibm.com>
PR target/88083
* gcc.target/s390/pr88083.c: New test.
From-SVN: r266306
2018-11-20 Richard Biener <rguenther@suse.de>
PR middle-end/83215
* alias.c (component_uses_parent_alias_set_from): Remove
alias-set zero and TYPE_TYPELESS_STORAGE case both already
handled in other ways.
* g++.dg/tree-ssa/pr83215.C: New testcase.
From-SVN: r266305
