Commit Graph

182263 Commits

Author SHA1 Message Date
Eric Botcazou
f3dd0581a5 [Ada] Implement part of System.Fat_Gen more efficiently
gcc/ada/

	* libgnat/s-fatgen.ads (Compose): Add pragma Inline.
	(Copy_Sign): Likewise.
	(Exponent): Likewise.
	(Fraction): Likewise.
	* libgnat/s-fatgen.adb: Remove with clause for System, add
	with and use clauses for System.Unsigned_Types.
	Add pragma Warnings (Off) for non-static constants.
	Remove precomputed tables of powers of radix and add a few
	constants describing the floating-point format.
	(Gradual_Scaling): Delete.
	(Copy_Sign): Reimplement directly.
	(Decompose): Likewise.
	(Scaling): Likewise.
	(Pred): Speed up.
	(Succ): Likewise.
	(Truncation): Tidy up.
	(Valid): Move constants to library level.
2020-12-14 10:51:52 -05:00
Piotr Trojanek
3cde9f1cc5 [Ada] Remove double initialization of the known value cache
gcc/ada/

	* sem_eval.adb (CV_Cache): Remove initialization at elaboration.
2020-12-14 10:51:52 -05:00
Gary Dismukes
a98c6ffa0b [Ada] Fix documentation of -gnatw.K switch (activates => disables)
gcc/ada/

	* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
	Correct documentation of the -gnatw.K switch to say that it
	disables rather than activates the warning.
	* gnat_ugn.texi: Regenerate.
2020-12-14 10:51:52 -05:00
Doug Rupp
e5e963ab2e [Ada] armhf-linux: symbolic tracebacks
gcc/ada/

	* tracebak.c: Add a section for ARM Linux.
2020-12-14 10:51:51 -05:00
Ghjuvan Lacambre
9189557557 [Ada] Implement AI12-0398-1/03
gcc/ada/

	* par-ch3.adb (P_Discriminant_Part_Opt): Parse aspects, update
	documentation.
	* par-ch6.adb (P_Return_Statement): Likewise.
	* par-ch9.adb (P_Entry_Index_Specification): Likewise.
2020-12-14 10:51:51 -05:00
Gary Dismukes
097826df0c [Ada] Additional fixes for Default_Initial_Condition
gcc/ada/

	* exp_aggr.adb (Build_Array_Aggr_Code.Gen_Assign): Move
	generation of the call for DIC check past the optional
	generation of calls to controlled Initialize procedures.
	* exp_ch3.adb
	(Build_Array_Init_Proc.Init_One_Dimension.Possible_DIC_Call):
	Suppress generation of a DIC call when the array component type
	is controlled.  The call will now be generated later inside the
	array's DI (Deep_Initialize) procedure.
	* exp_ch7.adb
	(Make_Deep_Array_Body.Build_Initialize_Statements): Generate a
	DIC call (when needed by the array component type) after any
	call to the component type's controlled Initialize procedure, or
	generate the DIC call by itself if there's no Initialize to
	call.
	* sem_aggr.adb (Resolve_Record_Aggregate.Add_Association):
	Simplify condition to only test Is_Box_Init_By_Default (previous
	condition was overkill, as well as incorrect in some cases).
	* sem_elab.adb (Active_Scenarios.Output_Call): For
	Default_Initial_Condition, suppress call to
	Output_Verification_Call when the subprogram is a partial DIC
	procedure.
2020-12-14 10:51:51 -05:00
Eric Botcazou
3254363745 [Ada] Fix couple of bugs in the implementation of Round attribute
gcc/ada/

	* exp_attr.adb (Expand_N_Attribute_Reference) <Attribute_Round>:
	Adjust commentary and set the Rounded_Result flag on the type
	conversion node when the node is needed.
	* exp_ch4.adb (Expand_N_Type_Conversion): Minor tweak.
	(Fixup_Universal_Fixed_Operation): Look through the type conversion
	only when it is to Universal_Real.
	* exp_fixd.adb: Remove with and use clauses for Snames.
	(Build_Divide): Remove redundant test.
	(Expand_Convert_Float_To_Fixed): Use Rounded_Result flag on the
	node to set the truncation parameter.
2020-12-14 10:51:50 -05:00
Piotr Trojanek
c2dc9fb661 [Ada] Simplify prevention of cascaded errors for Refined_State
gcc/ada/

	* sem_prag.adb (Analyze_Refinement_Clause): Simplify recently
	added code for preventing cascaded errors.
2020-12-14 10:51:50 -05:00
Bob Duff
2c40c60ecb [Ada] Compiler crash on call to function instance
gcc/ada/

	* exp_ch6.adb (Is_Build_In_Place_Result_Type): Further narrow
	the conditions under which we enable build-in-place for
	controlled types.
2020-12-14 10:51:50 -05:00
Yannick Moy
d983a9d050 [Ada] Fix warning control character for message on IN OUT parameter
gcc/ada/

	* sem_warn.adb (Output_Non_Modified_In_Out_Warnings): Use right
	warning control character 'k' in both comment and call to
	Errout_Msg_N.
2020-12-14 10:51:50 -05:00
Yannick Moy
758daef51b [Ada] Refine error messages on illegal Refined_State in SPARK
gcc/ada/

	* sem_prag.adb (Analyze_Refined_State_In_Decl_Part): Refine the
	error message for missing Part_Of on constituent. Avoid
	cascading error.
2020-12-14 10:51:49 -05:00
Piotr Trojanek
2a1a3fc67f [Ada] Avoid reanalysis of malformed dependency relations
gcc/ada/

	* sem_prag.adb (Analyze_Depends_In_Decl_Part): Replace early
	returns with goto Leave.
	(Collect_Subprogram_Inputs_Outputs): Fix style in comment.
2020-12-14 10:51:49 -05:00
Eric Botcazou
d494f9f037 [Ada] Tidy up implementation of System.Fat_Gen.Valid and inline it again
gcc/ada/

	* libgnat/s-fatgen.ads (Valid): Add again pragma Inline.
	* libgnat/s-fatgen.adb (Valid): Improve commentary, tidy up left
	and right, and remove superfluous trick for denormalized numbers.
2020-12-14 10:51:49 -05:00
Piotr Trojanek
efec136240 [Ada] Fix analysis of access objects in Depends contracts
gcc/ada/

	* sem_prag.adb (Find_Role): Constant object of
	access-to-constant and access-to-subprogram types are not
	writable.
	(Collect_Subprogram_Inputs_Outputs): In-parameters of
	access-to-variable type can act as outputs of the Depends
	contracts.
2020-12-14 10:51:49 -05:00
Piotr Trojanek
ae8c56262d [Ada] Update comment for processing of pragma Assertion_Policy
gcc/ada/

	* sa_messages.ads: Reference Subprogram_Variant in the comment
	for Assertion_Check.
	* sem_prag.adb (Analyze_Pragma): Add Subprogram_Variant as an
	ID_ASSERTION_KIND; move Default_Initial_Condition as an
	RM_ASSERTION_KIND.
2020-12-14 10:51:48 -05:00
Yannick Moy
3fcb8100aa [Ada] Correctly mark subprogram as not always inlined in GNATprove mode
gcc/ada/

	* inline.adb (Cannot_Inline): Add No_Info parameter to disable
	info message.
	* inline.ads (Cannot_Inline): When No_Info is set to True, do
	not issue info message in GNATprove mode, but still mark the
	subprogram as not always inlined.
	* sem_res.adb (Resolve_Call): Always call Cannot_Inline inside
	an assertion expression.
2020-12-14 10:51:48 -05:00
Eric Botcazou
49ea96b4d8 [Ada] Adjust documentation of System.Img_Util.Set_Decimal_Digits
gcc/ada/

	* libgnat/s-imguti.ads (Set_Decimal_Digits): Adjust documentation.
2020-12-14 10:51:48 -05:00
Nathan Sidwell
62c5ea5228 preprocessor: Deferred macro support
For deferred macros we also need a new field on the macro itself, so
that the module machinery can determine the macro was imported.  Also
the documentation for the hashnode's deferred field was incomplete.

	libcpp/
	* include/cpplib.h (struct cpp_macro): Add imported_p field.
	(struct cpp_hashnode): Tweak deferred field documentation.
	* macro.c (_cpp_new_macro): Clear new field.
	(cpp_get_deferred_macro, get_deferred_or_lazy_macro): Assert
	more.
2020-12-14 07:23:59 -08:00
Tamar Christina
159b0bd9ce middle-end: Exclude TOP permute from blend considerations
Similarly to UNKNOWN permutes, TOP needs to be excluded from being considered
for blends because it produces no permute to check.

gcc/ChangeLog:

	PR middle-end/98264
	* tree-vect-slp-patterns.c (linear_loads_p): Exclude TOP permute.

gcc/testsuite/ChangeLog:

	PR middle-end/98264
	* gcc.target/i386/pr98264.c: New test.
2020-12-14 15:20:11 +00:00
Ilya Leoshkevich
470a25b638 Limit perf data buffer during feature checking
Commit 2ead1ab911 ("Limit perf data buffer during profiling") added
-m8 to perf invocations during running tests, but the same problem
exists for checking whether perf is working in the first place.

gcc/testsuite/ChangeLog:

2020-12-08  Ilya Leoshkevich  <iii@linux.ibm.com>

	* lib/target-supports.exp(check_profiling_available): Limit
	perf data buffer.
2020-12-14 12:59:04 +01:00
Andrea Corallo
f60c1b3102 .dir-locals.el: Set 'fill-column' to 80 for c-mode
ChangeLog

2020-12-11  Andrea Corallo  <andrea.corallo@arm.com>

	* .dir-locals.el (c-mode): Set 'fill-column' to 80 columns.
2020-12-14 12:19:56 +01:00
Christophe Lyon
4cbb7cab47 arm: Auto-vectorization for MVE: vneg
This patch enables MVE vneg instructions for auto-vectorization.  MVE
vnegq insns in mve.md are modified to use 'neg' instead of unspec
expression.  The neg<mode>2 expander is added to vec-common.md.

Existing patterns in neon.md are prefixed with neon_.
It's not clear why we have different patterns for VDQW
and VH in neon.md, when WDQWH handles both, and patterns
with VDQ have provision for attributes for FP modes.

Another question is why <absneg_str><mode>2 always sets
neon_abs<q> type when it also handles neon_neq<q> cases.

2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/mve.md (mve_vnegq_f): Use 'neg' instead of unspec.
	(mve_vnegq_s): Likewise.
	* config/arm/neon.md (neg<mode>2): Rename into neon_neg<mode>2.
	(<absneg_str><mode>2): Rename into neon_<absneg_str><mode>2.
	(neon_v<absneg_str><mode>): Call gen_neon_<absneg_str><mode>2.
	(vashr<mode>3): Call gen_neon_neg<mode>2.
	(vlshr<mode>3): Call gen_neon_neg<mode>2.
	(neon_vneg<mode>): Call gen_neon_neg<mode>2.
	* config/arm/unspecs.md (VNEGQ_F, VNEGQ_S): Remove.
	* config/arm/vec-common.md (neg<mode>2): New expander.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vneg.c: Add tests for vneg.
2020-12-14 10:47:29 +00:00
Christophe Lyon
fd43603414 arm: Auto-vectorization for MVE: vmvn
This patch enables MVE vmvnq instructions for auto-vectorization.  MVE
vmvnq insns in mve.md are modified to use 'not' instead of unspec
expression to support one_cmpl<mode>2.  The one_cmpl<mode>2 expander
is added to vec-common.md.

2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (VDQNOTM2): New mode iterator.
	(supf): Remove VMVNQ_S and VMVNQ_U.
	(VMVNQ): Remove.
	* config/arm/mve.md (mve_vmvnq_u<mode>): New entry for vmvn
	instruction using expression not.
	(mve_vmvnq_s<mode>): New expander.
	* config/arm/neon.md (one_cmpl<mode>2): Renamed into
	one_cmpl<mode>2_neon.
	* config/arm/unspecs.md (VMVNQ_S, VMVNQ_U): Remove.
	* config/arm/vec-common.md (one_cmpl<mode>2): New expander.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vmvn.c: Add tests for vmvn.
2020-12-14 10:47:29 +00:00
Christophe Lyon
5391cf07be arm: Auto-vectorization for MVE: vbic
This patch enables MVE vbic instructions for auto-vectorization.  MVE
vbicq insns in mve.md are modified to use 'and not' instead of unspec
expression.

2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (supf): Remove VBICQ_S and VBICQ_U.
	(VBICQ): Remove.
	* config/arm/mve.md (mve_vbicq_u<mode>): New entry for vbic
	instruction using expression and not.
	(mve_vbicq_s<mode>): New expander.
	(mve_vbicq_f<mode>): Replace use of unspec by 'and not'.
	* config/arm/unspecs.md (VBICQ_S, VBICQ_U, VBICQ_F): Remove.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vbic.c: Add tests for vbic.
2020-12-14 10:47:29 +00:00
Christophe Lyon
434fb3b6cc arm: Auto-vectorization for MVE: veor
This patch enables MVE veorq instructions for auto-vectorization.  MVE
veorq insns in mve.md are modified to use xor instead of unspec
expression to support xor<mode>3.  The xor<mode>3 expander is added to
vec-common.md

2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/iterators.md (supf): Remove VEORQ_S and VEORQ_U.
	(VEORQ): Remove.
	* config/arm/mve.md (mve_veorq_u<mode>): New entry for veor
	instruction using expression xor.
	(mve_veorq_s<mode>): New expander.
	(mve_veorq_f<mode>): Use 'xor' code instead of unspec.
	* config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
	* config/arm/unspecs.md (VEORQ_S, VEORQ_U, VEORQ_F): Remove.
	* config/arm/vec-common.md (xor<mode>3): New expander.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-veor.c: Add tests for veor.
2020-12-14 10:47:29 +00:00
Christophe Lyon
ebc15a4e1e arm,testsuite: Fix vect-half-floats.c test
This patch fixes typos in effective targets which otherwise lead to
DejaGnu errors.

It also replaces dg-additional-options with dg-options to avoid
compiling with -ansi -pedantic-errors, resulting in
error: ISO C does not support the '_Float16' type [-Wpedantic]

2020-12-14  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	* gcc.target/arm/vect-half-floats.c: Fix typos.
2020-12-14 10:46:57 +00:00
Martin Liska
ab28eac607 sanitizer: do not ICE for pointer cmp/sub
gcc/c/ChangeLog:

	PR sanitizer/98204
	* c-typeck.c (pointer_diff): Do not emit a top-level
	sanitization.
	(build_binary_op): Likewise.

gcc/testsuite/ChangeLog:

	PR sanitizer/98204
	* c-c++-common/asan/pr98204.c: New test.
2020-12-14 10:49:27 +01:00
Przemyslaw Wirkus
cf7efe2d36 aarch64: Add support for Cortex-A78C
This patch adds support for -mcpu=cortex-a78c command line option.
For more information about this processor, see [0]:

[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c

gcc/ChangeLog:

	* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A78C core.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* doc/invoke.texi: Update docs.
2020-12-14 09:22:47 +00:00
Nikhil Benesch
0df5fa66b6 -fgo-dump-spec: skip typedefs that match struct tag
gcc/:
	* godump.c (go_output_typedef): Suppress typedefs whose name
	matches the tag of the underlying struct, union, or enum.
	Output declarations for enums that do not appear in typedefs.
gcc/testsuite:
	* gcc.misc-tests/godump-1.c: Add test cases.
2020-12-13 23:39:32 -08:00
François Dumont
8e56e4d956 libstdc++: Fix several _GLIBCXX_DEBUG tests
libstdc++-v3/ChangeLog:

	* testsuite/23_containers/array/debug/back2_neg.cc: target c++14 because assertion
	for constexpr is disabled in C++11.
	* testsuite/23_containers/array/debug/front2_neg.cc: Likewise.
	* testsuite/23_containers/array/debug/square_brackets_operator2_neg.cc: Likewise.
	* testsuite/23_containers/vector/debug/multithreaded_swap.cc: Include <memory>
	for shared_ptr.
2020-12-14 07:46:25 +01:00
GCC Administrator
b4cdc2a3d3 Daily bump. 2020-12-14 00:16:29 +00:00
Maciej W. Rozycki
2c3d487a9a VAX: Unify push operation selection
Avoid the possibility of code discrepancies like one fixed with the
previous change and improve the structure of code by selecting between
push and non-push operations in a single place in `vax_output_int_move'.

The PUSHAB/MOVAB address moves are never actually produced from this
code as the SImode invocation of this function is guarded with the
`nonsymbolic_operand' predicate, but let's not mess up with this code
too much on this occasion and keep the piece in place.

	* config/vax/vax.c (vax_output_int_move): Unify push operation
	selection.
2020-12-13 20:46:17 +00:00
Maciej W. Rozycki
d9ec27c1c3 VAX: Check the correct operand for constant 0 push operation
Check the output operand for representing pushing a value onto the stack
rather than the constant 0 input in determining whether to use the PUSHL
or the CLRL instruction for a SImode move.  The latter actually works by
means of using the predecrement addressing mode with the SP register and
the machine code produced even takes the same number of bytes, however
at least with some VAX implementations it incurs a performance penalty.
Besides, we don't want to check the wrong operand anyway and have code
that works by chance only.

Add a test case covering push operations; for operands different from
constant zero there is actually a code size advantage for using PUSHL
rather than the equivalent MOVL instruction.

	gcc/
	* config/vax/vax.c (vax_output_int_move): Check the correct
	operand for constant 0 push operation.

	gcc/testsuite/
	* gcc.target/vax/push.c: New test.
2020-12-13 20:46:17 +00:00
Maciej W. Rozycki
294ca9eca0 VAX: Handle subtracting from self with QMATH DImode add/sub
Remove an assertion the failure of which has not been actually observed,
but which appears clearly dangerous, for when the QMATH DImode add/sub
handler is invoked with the subtrahend and the minuend both the same.
Instead handle the operation by emitting a move of constant 0 to the
output operand.  Adjust the relevant inline comment accordingly.

	gcc/
	* config/vax/vax.c (vax_expand_addsub_di_operands): Handle equal
	input operands with subtraction.
2020-12-13 20:46:17 +00:00
Maciej W. Rozycki
ffb1dcf622 VAX: Handle constant 0 with QMATH DImode add/sub
Handle constant 0 passed to the QMATH DImode add/sub handler such as
with:

#2  0x0000000011d409b0 in gen_adddi3 (operand0=0x7ffff5c0a128,
    operand1=0x7ffff5c60480, operand2=0x7ffff5c60470)
    at .../gcc/config/vax/vax.md:755
755	  "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
(gdb) pr operand0
(reg:DI 31)
(gdb) pr operand1
(const_int 0 [0])
(gdb) pr operand2
(const_int -1 [0xffffffffffffffff])
(gdb)

causing an assertion in `vax_expand_addsub_di_operands':

      gcc_assert (operands[1] != const0_rtx || code == MINUS);

to trigger:

during RTL pass: expand
.../gcc/testsuite/gcc.c-torture/compile/sync-1.c: In function 'test_op_ignore':
.../gcc/testsuite/gcc.c-torture/compile/sync-1.c:33:10: internal compiler error: in vax_expand_addsub_di_operands, at config/vax/vax.c:2080
0x11815003 vax_expand_addsub_di_operands(rtx_def**, rtx_code)
	.../gcc/config/vax/vax.c:2080
0x11d409af gen_adddi3(rtx_def*, rtx_def*, rtx_def*)
	.../gcc/config/vax/vax.md:755
0x10ea2763 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*, rtx_def*>(rtx_def*, rtx_def*, rtx_def*) const
	.../gcc/recog.h:304
0x10f7fc8f maybe_gen_insn(insn_code, unsigned int, expand_operand*)
	.../gcc/optabs.c:7402
0x10f67f8b expand_binop_directly
	.../gcc/optabs.c:1122
0x10f684cf expand_binop(machine_mode, optab_tag, rtx_def*, rtx_def*, rtx_def*, int, optab_methods)
	.../gcc/optabs.c:1209
0x10f6fb4f expand_unop(machine_mode, optab_tag, rtx_def*, rtx_def*, int)
	.../gcc/optabs.c:3013
0x10f6c493 expand_simple_unop(machine_mode, rtx_code, rtx_def*, rtx_def*, int)
	.../gcc/optabs.c:2200
0x10f7e2f3 expand_atomic_fetch_op(rtx_def*, rtx_def*, rtx_def*, rtx_code, memmodel, bool)
	.../gcc/optabs.c:7021
0x107f7523 expand_builtin_sync_operation
	.../gcc/builtins.c:7605
0x107ff547 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
	.../gcc/builtins.c:9430
0x10acda63 expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool)
	.../gcc/expr.c:11249
0x10abeb9f expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool)
	.../gcc/expr.c:8486
0x1085606b expand_expr
	.../gcc/expr.h:282
0x1086157f expand_call_stmt
	.../gcc/cfgexpand.c:2709
0x10865ab7 expand_gimple_stmt_1
	.../gcc/cfgexpand.c:3713
0x108662fb expand_gimple_stmt
	.../gcc/cfgexpand.c:3877
0x10870387 expand_gimple_basic_block
	.../gcc/cfgexpand.c:5918
0x10872b6b execute
	.../gcc/cfgexpand.c:6602
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
compiler exited with status 1
FAIL: gcc.c-torture/compile/sync-1.c   -O0  (internal compiler error)

causing numerous failures in regression testing.

While requesting an addition operation to be produced for the constant
operands of 0 and -1 may seem silly, technically there is nothing wrong
with it, and non-QMATH code (as with the `-mno-qmath' option) has no
issues with that, so neither should QMATH code.  This operation will
normally be folded in later passes anyway.

Observe then, that adding or subtracting constant 0 amounts to a move
(and we even have a machine instruction available to do that with a
single operation) so handle the case explicitly, swapping the addends if
so required, removing the assertion failure and along with that 70 test
suite failures like:

FAIL: gcc.c-torture/compile/sync-1.c   -O0  (internal compiler error)
FAIL: gcc.c-torture/compile/sync-1.c   -O0  fetch_and_nand (test for warnings, line )
FAIL: gcc.c-torture/compile/sync-1.c   -O0  nand_and_fetch (test for warnings, line )
FAIL: gcc.c-torture/compile/sync-1.c   -O0  (test for excess errors)
FAIL: gcc.c-torture/compile/sync-2.c   -O0  (internal compiler error)
FAIL: gcc.c-torture/compile/sync-2.c   -O0   (test for warnings, line )
FAIL: gcc.c-torture/compile/sync-2.c   -O0  (test for excess errors)
FAIL: gcc.c-torture/compile/sync-3.c   -O0  (internal compiler error)
FAIL: gcc.c-torture/compile/sync-3.c   -O0   (test for warnings, line )
FAIL: gcc.c-torture/compile/sync-3.c   -O0  (test for excess errors)

and similarly across all the other optimization levels and compilation
options covered.

	gcc/
	* config/vax/vax.c (vax_expand_addsub_di_operands): Handle the
	addition or subtraction of 0.
2020-12-13 20:46:17 +00:00
Maciej W. Rozycki
3530ca075b VAX: Remove unused register allocation from QMATH DImode add/sub handler
An allocation is made for a temporary register, however it is unneeded,
as actually explained in the comment preceding the conditional block in
question, and consequently never used, so remove it.  The `temp' rtx is
already used elsewhere in the function, which is possibly why this dead
assignment has not been warned about.

	gcc/
	* config/vax/vax.c (vax_expand_addsub_di_operands): Remove
	unused register allocation.
2020-12-13 20:46:16 +00:00
Maciej W. Rozycki
20d68fa0d8 VAX: Fix lower bound adjustment with `casesi'
Fix an issue with the `casesi' expander using `GEN_INT' to produce the
constant rtx for lower bound adjustment.  This generates a VOIDmode
value which may overflow the SImode range required for the operand to
stay within to satisfy `general_operand', resulting in an ICE like:

.../gcc/testsuite/gcc.c-torture/compile/pr46934.c: In function 'caller':
.../gcc/testsuite/gcc.c-torture/compile/pr46934.c:17:1: error: unrecognizable insn:
(insn 5 2 6 2 (set (reg:SI 25)
        (plus:SI (mem/c:SI (reg/f:SI 17 virtual-incoming-args) [1 reg_type+0 S4 A32])
            (const_int 2147483648 [0x80000000]))) -1
     (nil))
during RTL pass: vregs
.../gcc/testsuite/gcc.c-torture/compile/pr46934.c:17:1: internal compiler error: in extract_insn, at recog.c:2315
0x110d4673 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
	.../gcc/rtl-error.c:108
0x110d46eb _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
	.../gcc/rtl-error.c:116
0x1106578b extract_insn(rtx_insn*)
	.../gcc/recog.c:2315
0x10b63f73 instantiate_virtual_regs_in_insn
	.../gcc/function.c:1609
0x10b65b2f instantiate_virtual_regs
	.../gcc/function.c:1979
0x10b65ca7 execute
	.../gcc/function.c:2028
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
compiler exited with status 1
FAIL: gcc.c-torture/compile/pr46934.c   -O0  (internal compiler error)

Use `gen_int_mode' to produce the rtx instead, requesting a SImode value
so that the constant gets correctly truncated:

@@ -199,7 +199,7 @@ caller (unsigned int reg_type)

 (insn 5 4 6 (set (reg:SI 25)
         (plus:SI (mem/c:SI (reg/f:SI 17 virtual-incoming-args) [1 reg_type+0 S4 A32])
-            (const_int 2147483648 [0x80000000]))) -1
+            (const_int -2147483648 [0xffffffff80000000]))) -1
      (nil))

 (jump_insn 6 5 7 (set (pc)

removing these test suite failures:

FAIL: gcc.c-torture/compile/pr46934.c   -O0  (internal compiler error)
FAIL: gcc.c-torture/compile/pr46934.c   -O0  (test for excess errors)

with the `vax-netbsdelf' target.

	gcc/
	* config/vax/vax.md (casesi): Use `gen_int_mode' rather than
	`GEN_INT' for the immediate used for lower bound adjustment.
2020-12-13 20:46:16 +00:00
Jakub Jelinek
49ec63666e widening_mul: Fix a > ~b to .ADD_OVERFLOW optimization [PR98256]
Unfortunately, my latest tree-ssa-math-opts.c patch broke the following
testcase.  The problem is that the code is adding .ADD_OVERFLOW or
.SUB_OVERFLOW before or after the stmt on which the function has been
called, which is normally a addition or subtraction that has all the
operands.
But in the a > ~b optimization that stmt is the ~b stmt and the other
comparison operand might be defined only after that ~b stmt, so we can't
insert the .ADD_OVERFLOW next to ~b that we want to delete, but need to
insert it before the a > temp comparison that uses it; and in that case
when removing the BIT_NOT_EXPR stmt we need to ensure the caller doesn't do
gsi_next because gsi_remove already points the iterator to the next stmt.

2020-12-13  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/98256
	* tree-ssa-math-opts.c (match_uaddsub_overflow): For BIT_NOT_EXPR,
	only handle a single use, and insert .ADD_OVERFLOW before the
	comparison rather than after the BIT_NOT_EXPR.  Return true iff
	it is BIT_NOT_EXPR and it has been removed.
	(math_opts_dom_walker::after_dom_children) <case BIT_NOT_EXPR>:
	If match_uaddsub_overflow returned true, continue instead of break.

	* gcc.c-torture/compile/pr98256.c: New test.
2020-12-13 19:28:07 +01:00
Tamar Christina
3cc4e183f1 Revert "Arm: Add NEON and MVE RTL patterns for Complex Addition, Multiply and FMA."
This reverts commit 3b8a82f97d.

Has a dependency on the AArch64 patch which hasn't been approved yet.
2020-12-13 16:49:55 +00:00
Jakub Jelinek
d88e2cb549 varasm: Reject soft frame or arg pointer registers for register vars [PR92469]
The following patch rejects frame, argp and retarg registers (unless they are equal
to hard frame pointer registers or if they aren't eliminable) from local or global
register vars.
These are just internal implementation details eliminated later into hard
frame pointer or stack pointer and using them as register variable leads
to numerous ICEs.

2020-12-13  Jakub Jelinek  <jakub@redhat.com>

	PR target/92469
	* varasm.c (eliminable_regno_p): New function.
	(make_decl_rtl): Reject asm vars for frame and argp
	if they are different from hard frame pointer.

	* gcc.target/i386/pr92469.c: New test.
	* gcc.target/i386/pr79804.c: Adjust expected diagnostics.
	* gcc.target/i386/pr88178.c: Expect an error.
2020-12-13 17:08:08 +01:00
Tamar Christina
3b8a82f97d Arm: Add NEON and MVE RTL patterns for Complex Addition, Multiply and FMA.
This adds implementation for the optabs for complex additions.  With this the
following C code:

  void f90 (float complex a[restrict N], float complex b[restrict N],
	    float complex c[restrict N])
  {
    for (int i=0; i < N; i++)
      c[i] = a[i] + (b[i] * I);
  }

generates

  f90:
	  add     r3, r2, #1600
  .L2:
	  vld1.32 {q8}, [r0]!
	  vld1.32 {q9}, [r1]!
	  vcadd.f32       q8, q8, q9, #90
	  vst1.32 {q8}, [r2]!
	  cmp     r3, r2
	  bne     .L2
	  bx      lr

instead of

  f90:
	  add     r3, r2, #1600
  .L2:
	  vld2.32 {d24-d27}, [r0]!
	  vld2.32 {d20-d23}, [r1]!
	  vsub.f32	q8, q12, q11
	  vadd.f32	q9, q13, q10
	  vst2.32 {d16-d19}, [r2]!
	  cmp     r3, r2
	  bne     .L2
	  bx      lr

gcc/ChangeLog:

	* config/arm/arm_mve.h (__arm_vcaddq_rot90_u8, __arm_vcaddq_rot270_u8,
	, __arm_vcaddq_rot90_s8, __arm_vcaddq_rot270_s8,
	__arm_vcaddq_rot90_u16, __arm_vcaddq_rot270_u16, __arm_vcaddq_rot90_s16,
	__arm_vcaddq_rot270_s16, __arm_vcaddq_rot90_u32,
	__arm_vcaddq_rot270_u32, __arm_vcaddq_rot90_s32,
	__arm_vcaddq_rot270_s32, __arm_vcmulq_rot90_f16,
	__arm_vcmulq_rot270_f16, __arm_vcmulq_rot180_f16,
	__arm_vcmulq_f16, __arm_vcaddq_rot90_f16, __arm_vcaddq_rot270_f16,
	__arm_vcmulq_rot90_f32, __arm_vcmulq_rot270_f32,
	__arm_vcmulq_rot180_f32, __arm_vcmulq_f32, __arm_vcaddq_rot90_f32,
	__arm_vcaddq_rot270_f32, __arm_vcmlaq_f16, __arm_vcmlaq_rot180_f16,
	__arm_vcmlaq_rot270_f16, __arm_vcmlaq_rot90_f16, __arm_vcmlaq_f32,
	__arm_vcmlaq_rot180_f32, __arm_vcmlaq_rot270_f32,
	__arm_vcmlaq_rot90_f32): Update builtin calls.
	* config/arm/arm_mve_builtins.def (vcaddq_rot90_u, vcaddq_rot270_u,
	vcaddq_rot90_s, vcaddq_rot270_s, vcaddq_rot90_f, vcaddq_rot270_f,
	vcmulq_f, vcmulq_rot90_f, vcmulq_rot180_f, vcmulq_rot270_f,
	vcmlaq_f, vcmlaq_rot90_f, vcmlaq_rot180_f, vcmlaq_rot270_f): Removed.
	(vcaddq_rot90, vcaddq_rot270, vcmulq, vcmulq_rot90, vcmulq_rot180,
	vcmulq_rot270, vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270):
	New.
	* config/arm/constraints.md (Dz): Include MVE.
	* config/arm/iterators.md (mve_rotsplit1, mve_rotsplit2): New.
	(rot): Add UNSPEC_VCMLS, UNSPEC_VCMUL and UNSPEC_VCMUL180.
	(rot_op, rotsplit1, rotsplit2, fcmac1, VCMLA_OP, VCMUL_OP): New.
	* config/arm/mve.md (VCADDQ_ROT270_S, VCADDQ_ROT90_S, VCADDQ_ROT270_U,
	VCADDQ_ROT90_U, VCADDQ_ROT270_F, VCADDQ_ROT90_F, VCMULQ_F,
	VCMULQ_ROT180_F, VCMULQ_ROT270_F, VCMULQ_ROT90_F, VCMLAQ_F,
	VCMLAQ_ROT180_F, VCMLAQ_ROT90_F, VCMLAQ_ROT270_F, VCADDQ_ROT270_S,
	VCADDQ_ROT270, VCADDQ_ROT90): Removed.
	(mve_rot, VCMUL): New.
	(mve_vcaddq_rot270_<supf><mode, mve_vcaddq_rot90_<supf><mode>,
	mve_vcaddq_rot270_f<mode>, mve_vcaddq_rot90_f<mode>, mve_vcmulq_f<mode,
	mve_vcmulq_rot180_f<mode>, mve_vcmulq_rot270_f<mode>,
	mve_vcmulq_rot90_f<mode>, mve_vcmlaq_f<mode>, mve_vcmlaq_rot180_f<mode>,
	mve_vcmlaq_rot270_f<mode>, mve_vcmlaq_rot90_f<mode>): Removed.
	(mve_vcmlaq<mve_rot><mode>, mve_vcmulq<mve_rot><mode>,
	mve_vcaddq<mve_rot><mode>, cadd<rot><mode>3, mve_vcaddq<mve_rot><mode>):
	New.
	(cmul<rot_op><mode>3): Exclude MVE types.
	* config/arm/unspecs.md (UNSPEC_VCMUL90, UNSPEC_VCMUL270): New.
	* config/arm/vec-common.md (cadd<rot><mode>3, cmul<rot_op><mode>3,
	arm_vcmla<rot><mode>, cml<fcmac1><rot_op><mode>4): New.
	* config/arm/unspecs.md (UNSPEC_VCMUL, UNSPEC_VCMUL180, UNSPEC_VCMLS,
	UNSPEC_VCMLS180): New.
	* config/arm/neon.md (cmul<rot_op><mode>3): New.
2020-12-13 14:12:34 +00:00
Tamar Christina
2f05dadaed Arm: Add support for auto-vectorization using HF mode.
This adds support to the auto-vectorizer to support HFmode vectorization for
AArch32.  This is supported when +fp16 is used.  I wonder if I should disable
the returning of the type if the option isn't enabled.

At the moment it will be returned but the vectorizer will try and fail to use
it.  It wastes a few compile cycles but doesn't result in bad code.

gcc/ChangeLog:

	* config/arm/arm.c (arm_preferred_simd_mode): Add E_HFmode.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/vect-half-floats.c: New test.
2020-12-13 14:10:07 +00:00
Tamar Christina
3ed472af6b middle-end: Support complex Addition
This patch adds support for

  * Complex Addition with rotation of 90 and 270.

  Addition with rotation of the second argument around the Argand plane.
    Supported rotations are 90 and 180.

    c = a + (b * I) and c = a + (b * I * I * I)

gcc/ChangeLog:

	* tree-vect-slp-patterns.c: New file.
	* Makefile.in: Add it.
	* doc/passes.texi: Document it.
	* internal-fn.def (COMPLEX_ADD_ROT90, COMPLEX_ADD_ROT270): New.
	* optabs.def (cadd90_optab, cadd270_optab): New.
	* doc/md.texi: Document them.
	* tree-vect-loop.c (vect_analyze_loop_2): Add dissolve code.
	* tree-vect-slp.c:
	(vect_free_slp_instance, vect_create_new_slp_node): Export.
	(vect_match_slp_patterns_2, vect_match_slp_patterns): New.
	(vect_analyze_slp): Use it.
	* tree-vectorizer.h (vect_free_slp_tree): Export.
	(enum _complex_operation): Forward declare.
	(class vect_pattern): New

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp
	(check_effective_target_arm_v8_3a_complex_neon_ok_nocache): Fix it.
	(check_effective_target_vect_complex_add_byte
	,check_effective_target_vect_complex_add_int
	,check_effective_target_vect_complex_add_short
	,check_effective_target_vect_complex_add_long
	,check_effective_target_vect_complex_add_half
	,check_effective_target_vect_complex_add_float
	,check_effective_target_vect_complex_add_double): New.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-byte.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-int.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-long.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-short.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-byte.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-int.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-long.c: New test.
	* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-short.c: New test.
	* gcc.dg/vect/complex/complex-add-pattern-template.c: New test.
	* gcc.dg/vect/complex/complex-add-template.c: New test.
	* gcc.dg/vect/complex/complex-operations-run.c: New test.
	* gcc.dg/vect/complex/complex-operations.c: New test.
	* gcc.dg/vect/complex/complex.exp: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-double.c: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-float.c: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-half-float.c: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-double.c: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-float.c: New test.
	* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-half-float.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-double.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-float.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-half-float.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-pattern-double.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-pattern-float.c: New test.
	* gcc.dg/vect/complex/fast-math-complex-add-pattern-half-float.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-byte.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-int.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-long.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-short.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-byte.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-int.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-long.c: New test.
	* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-short.c: New test.
2020-12-13 14:09:11 +00:00
Tamar Christina
10bbba9145 middle-end: Refactor and expose some vectorizer helper functions.
This is a small refactoring which exposes some helper functions in the
vectorizer so they can be used in other places.

gcc/ChangeLog:

	* tree-vect-patterns.c (vect_mark_pattern_stmts): Remove static inline.
	* tree-vect-slp.c (vect_create_new_slp_node): Remove static and only
	set smts if valid.
	* tree-vectorizer.c (vec_info::add_pattern_stmt): New.
	(vec_info::set_vinfo_for_stmt): Optionally enforce read-only.
	* tree-vectorizer.h (struct _slp_tree): Use new types.
	(lane_permutation_t, lane_permutation_t): New.
	(vect_create_new_slp_node, vect_mark_pattern_stmts): New.
2020-12-13 13:53:48 +00:00
Thomas Koenig
501f470267 Show coarrays on parse tree dump, implement debug for array references.
gcc/fortran/ChangeLog:

	* dump-parse-tree.c (show_array_ref): Also show coarrays.
	(debug): Implement for array reference.
2020-12-13 12:55:56 +01:00
Rainer Orth
f1eeabc1fd testsuite: Fix various scan-assembler-symbol-section issues
This patch addresses some of the issues that I found when looking into the
failures of the scan-assembler-symbol-section tests on Solaris/SPARC.

* The first issue was that on Solaris/SPARC, section names are
  double-quoted, both with as and gas:

        .section        ".text"

  When using as, the section flag and type syntax is completely
  different from other ELF targets:

        .section        "my_named_section",#alloc,#execinstr,#progbits

  This patch fixes this by stripping double quotes from section names.

* However, this didn't work initially (only the leading quote was
  stripped), which is due to David's recent AIX patch: with the
  introduction of the new capturing group to handle both .section (ELF)
  and .csect (XCOFF), $full_section_directive would never be empty on
  ELF and Mach-O targets, so the extraction of the section name didn't
  work any longer.  This had also broken the Darwin tests completely.

* With working double quote stripping, all but one of the tests PASSed
  on Solaris/SPARC, the exception being:

FAIL: gcc.dg/20021029-1.c scan-assembler-symbol-section symbol ar (found __sparc_get_pc_thunk.l7) has section ^\\\\.(const|rodata)|\\\\[RO\\\\] (found .text.__sparc_get_pc_thunk.l7%__sparc_get_pc_thunk.l7)

  This is due to the symbol name (ar) not being anchored in the test and
  unexpectedly matchting __sparc_get_pc_thunk.l7.

* Next, I ran the tests on Darwin 11 and found two failing tests:

FAIL: gcc.dg/darwin-sections.c scan-assembler-symbol-section symbol ^_a\$ (symbol not found) has section \\\\.data
FAIL: gcc.dg/darwin-sections.c scan-assembler-symbol-section symbol ^_b\$ (symbol not found) has section \\\\.data

  is due to Iain's recent "Darwin : Begin rework of zero-fill sections."
  patch which emits

        .globl _a
        .zerofill __DATA,__common,_a,1,0

  This is already scanned for, so the two scans above can just go.

  The other failing test is

FAIL: g++.dg/gomp/tls-5.C  -std=c++14  scan-assembler-symbol-section symbol ^_?_ZGR2ir_\$ (symbol not found) has section ^\\\\.tdata|\\\\[TL\\\\]
FAIL: g++.dg/gomp/tls-5.C  -std=c++14  scan-assembler-symbol-section symbol ^_?ir\$ (symbol not found) has section ^\\\\.tbss|\\\\[TL\\\\]

  Other scans are guarded by target tls_native, and indeed the assembler
  output has

___emutls_v._ZGR2ir_:
___emutls_t._ZGR2ir_:

___emutls_v.ir:

  Unfortunately scan-assembler-symbol-section doesn't support selects
  yet, which this test implements both for the benefit of this test and
  for symmetry.

With those changes, test results are clean now on sparc-sun-solaris2.11,
i386-pc-solaris2.11, i386-apple-darwin11.4.2, and
powerpc-ibm-aix7.2.4.0.

2020-12-03  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	gcc:
	* doc/sourcebuild.texi (Commands for use in dg-final, Scan the
	assembly output, scan-assembler-symbol-section): Document.
	(scan-symbol-section): Document.

	gcc/testsuite:
	* lib/scanasm.exp (scan-symbol-section): Pass args to
	dg-scan-symbol-section.
	(scan-assembler-symbol-section): Likewise.
	(dg-scan-symbol-section): Handle selector from orig_args.
	Get patterns from orig_args.
	(parse_section_of_symbols): Fix section_pattern.
	Strip double quotes from section name.

	* g++.dg/gomp/tls-5.C: Restrict ir, _ZGR2ir_ scans to tls_native.
	* gcc.dg/20021029-1.c: Anchor ar symbol.
	* gcc.dg/darwin-sections.c: Remove obsolete scans for _a, _b in
	.data.
2020-12-13 12:48:26 +01:00
Richard Sandiford
1498b1a8fb Tweak the way that is_a is implemented
At the moment, class hierarchies that use is_a are expected
to define specialisations like:

  template <>
  template <>
  inline bool
  is_a_helper <cgraph_node *>::test (symtab_node *p)
  {
    return p->type == SYMTAB_FUNCTION;
  }

But this doesn't scale well to larger hierarchies, because it only
defines ::test for an argument that is exactly “symtab_node *”
(and not for example “const symtab_node *” or something that
comes between cgraph_node and symtab_node in the hierarchy).

For example:

  struct A { int x; };
  struct B : A {};
  struct C : B {};

  template <>
  template <>
  inline bool
  is_a_helper <C *>::test (A *a)
  {
    return a->x == 1;
  }

  bool f(B *b) { return is_a<C *> (b); }

gives:

  warning: inline function ‘static bool is_a_helper<T>::test(U*) [with U = B; T = C*]’ used but never defined

and:

  bool f(const A *a) { return is_a<const C *> (a); }

gives:

  warning: inline function ‘static bool is_a_helper<T>::test(U*) [with U = const A; T = const C*]’ used but never defined

This patch instead allows is_a to be implemented by specialising
is_a_helper as a whole, for example:

  template<>
  struct is_a_helper<C *> : static_is_a_helper<C *>
  {
    static inline bool test (const A *a) { return a->x == 1; }
  };

It also adds a general specialisation of is_a_helper for const
pointers.  Together, this makes both of the above examples work.

gcc/
	* is-a.h (reinterpret_is_a_helper): New class.
	(static_is_a_helper): Likewise.
	(is_a_helper): Inherit from reinterpret_is_a_helper.
	(is_a_helper<const T *>): New specialization.
2020-12-13 10:41:09 +00:00
Richard Sandiford
1751a78eca Move iterator_range to a new iterator-utils.h file
A later patch will add more iterator-related utilities.  Rather than
putting them all directly in coretypes.h, it seemed better to add a
new header file, here called "iterator-utils.h".  This preliminary
patch moves the existing iterator_range class there too.

I used the same copyright date range as coretypes.h “just to be sure”.

gcc/
	* coretypes.h (iterator_range): Move to...
	* iterator-utils.h: ...this new file.
2020-12-13 10:41:08 +00:00
Richard Sandiford
6ad972ece1 rtlanal: Remove noop_move_p REG_EQUAL condition
noop_move_p currently keeps any instruction that has a REG_EQUAL
note, on the basis that the equality might be useful in future.
But this creates a perverse incentive not to add potentially-useful
REG_EQUAL notes, in case they prevent an instruction from later being
removed as dead.

The condition originates from flow.c:life_analysis_1 and predates
the changes tracked by the current repository (1992).  It probably
made sense when most optimisations were done on RTL rather than FE
trees, but it seems counterproductive now.

gcc/
	* rtlanal.c (noop_move_p): Don't check for REG_EQUAL notes.
2020-12-13 10:41:07 +00:00
Richard Sandiford
da40a69c9e vec: Silence clang warning
I noticed during compatibility testing that clang warns that this
operator won't be implicitly const in C++14 onwards.

gcc/
	* vec.h (vnull::operator vec<T, A, L>): Make const.
2020-12-13 10:41:06 +00:00