Commit Graph

174701 Commits

Author SHA1 Message Date
Iain Sandoe
5bc9d2f5ed coroutines: Prevent repeated error messages for missing promise.
If the user's coroutine return type omits the mandatory promise
type then we will currently restate that error each time we see
a coroutine keyword, which doesn't provide any new information.
This suppresses all but the first instance in each coroutine.

gcc/cp/ChangeLog:

2020-02-04  Iain Sandoe  <iain@sandoe.co.uk>

	* coroutines.cc (find_promise_type): Delete unused forward
	declaration.
	(struct coroutine_info): Add a bool for no promise type error.
	(coro_promise_type_found_p): Only emit the error for a missing
	promise once in each affected coroutine.

gcc/testsuite/ChangeLog:

2020-02-04  Iain Sandoe  <iain@sandoe.co.uk>

	* g++.dg/coroutines/coro-missing-promise.C: New test.
2020-02-04 09:37:18 +00:00
Richard Biener
5f0653a8b7 tree-optimization/91123 - restore redundant store removal
Redundant store removal in FRE was restricted for correctness reasons.
The following extends correctness fixes required to memcpy/aggregate
copy translation.  The main change is that we no longer insert
references rewritten to cover such aggregate copies into the hashtable
but the original one.

2020-02-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/91123
	* tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
	(vn_walk_cb_data::last_vuse): New member.
	(vn_walk_cb_data::saved_operands): Likewsie.
	(vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
	(vn_walk_cb_data::push_partial_def): Use finish.
	(vn_reference_lookup_2): Update last_vuse and use finish if
	we've saved operands.
	(vn_reference_lookup_3): Use finish and update calls to
	push_partial_defs everywhere.  When translating through
	memcpy or aggregate copies save off operands and alias-set.
	(eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
	operation for redundant store removal.

	* gcc.dg/tree-ssa/ssa-fre-85.c: New testcase.
2020-02-04 10:08:05 +01:00
Richard Biener
fc98d03861 tree-optimization/92819 restrict new vector CTOR canonicalization
The PR shows that code generation ends up pessimized by the new
canonicalization rules that end up nailing do-not-care elements
to specific values making it hard to generate good code later.

The temporary solution is to avoid this for the cases we also
obviously know the canonicalization will create more GIMPLE stmts than
before.

2020-02-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/92819
	* tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
	generating more stmts than before.

	* gcc.target/i386/pr92819.c: New testcase.
	* gcc.target/i386/pr92803.c: Adjust.
2020-02-04 10:07:47 +01:00
Martin Liska
9a4d502421
Fix release checking build of ARM.
* config/arm/arm.c (arm_gen_far_branch): Move the function
	outside of selftests.
2020-02-04 09:23:22 +01:00
Ian Lance Taylor
79530f94e9 syscall: fix riscv64 GNU/Linux build
Make syscall_linux_riscv64.go, new in the 1.14beta1 release, look like
the other syscall_linux_GOARCH.go files.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/217577
2020-02-03 18:14:19 -08:00
Ian Lance Taylor
628ee3c2f3 libbacktrace: always pass -g when compiling test code
This approach required adding a few casts to ztest.c, as it is now
compiled with -Wall.

Fixes PR libbacktrace/90636
2020-02-03 18:13:28 -08:00
GCC Administrator
8b117ad0c3 Daily bump. 2020-02-04 00:16:49 +00:00
Michael Meissner
e181ffc92a Optimize vec_extract of vectors in memory with a PC-relative address.
2020-02-03  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
	function to adjust PC-relative vector addresses.
	(rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
	handle vectors with PC-relative addresses.
2020-02-03 18:25:07 -05:00
Michael Meissner
fb47dc28d2 Rewrite convulated code to avoid adding r0.
2020-02-03  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
	reference.
	(hard_reg_and_mode_to_addr_mask): Delete.
	(rs6000_adjust_vec_address): If the original vector address
	was REG+REG or REG+OFFSET and the element is not zero, do the add
	of the elements in the original address before adding the offset
	for the vector element.  Use address_to_insn_form to validate the
	address using the register being loaded, rather than guessing
	whether the address is a DS-FORM or DQ-FORM address.
2020-02-03 18:22:18 -05:00
Michael Meissner
e7f3e07528 Adjust how variable vector extraction is done.
2020-02-03  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (get_vector_offset): New helper function
	to calculate the offset in memory from the start of a vector of a
	particular element.  Add code to keep the element number in
	bounds if the element number is variable.
	(rs6000_adjust_vec_address): Move calculation of offset of the
	vector element to get_vector_offset.
	(rs6000_split_vec_extract_var): Do not do the initial AND of
	element here, move the code to get_vector_offset.
2020-02-03 17:57:57 -05:00
Jason Merrill
87fbd5347b c++: Fix constexpr vs. reference parameter.
[expr.const] specifically rules out mentioning a reference even if its
address is never used, because it implies indirection that is similarly
non-constant for a pointer variable.

	PR c++/66477
	* constexpr.c (cxx_eval_constant_expression) [PARM_DECL]: Don't
	defer loading the value of a reference.
2020-02-03 17:52:17 -05:00
Jason Merrill
8fda2c274a c++: Allow parm of empty class type in constexpr.
Since copying a class object is defined in terms of the copy constructor,
copying an empty class is OK even if it would otherwise not be usable in a
constant expression.  Relatedly, using a parameter as an lvalue is no more
problematic than a local variable, and calling a member function uses the
object as an lvalue.

	PR c++/91953
	* constexpr.c (potential_constant_expression_1) [PARM_DECL]: Allow
	empty class type.
	[COMPONENT_REF]: A member function reference doesn't use the object
	as an rvalue.
2020-02-03 17:50:36 -05:00
Michael Meissner
19e43cbce3 Add some gcc_asserts for vector extract processing.
2020-02-03  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
	gcc_asserts.
2020-02-03 15:50:39 -05:00
Iain Sandoe
d60c25fa02 coroutines: Fix ICE on invalid (PR93458).
Since coroutine-ness is discovered lazily, we encounter the diagnostics
during each keyword parse.  We were not handling the case where a user code
failed to include fundamental information (e.g. the traits) in a graceful
manner.

Once we've emitted an error for this level of fail, then we suppress
additional copies (otherwise the same thing will be reported for every
coroutine keyword seen).

gcc/cp/ChangeLog:

2020-02-03  Iain Sandoe  <iain@sandoe.co.uk>

	* coroutines.cc (struct coroutine_info): Add a bool flag to note
	that we emitted an error for a bad function return type.
	(get_coroutine_info): Tolerate an unset info table in case of
	missing traits.
	(find_coro_traits_template_decl): In case of error or if we didn't
	find a type template, note we emitted the error and suppress
	duplicates.
	(find_coro_handle_template_decl): Likewise.
	(instantiate_coro_traits): Only check for error_mark_node in the
	return from lookup_qualified_name.
	(coro_promise_type_found_p): Reorder initialization so that we check
	for the traits and their usability before allocation of the info
	table.  Check for a suitable return type and emit a diagnostic for
	here instead of relying on the lookup machinery.  This allows the
	error to have a better location, and means we can suppress multiple
	copies.
	(coro_function_valid_p): Re-check for a valid promise (and thus the
	traits) before proceeding.  Tolerate missing info as a fatal error.

gcc/testsuite/ChangeLog:

2020-02-03  Iain Sandoe  <iain@sandoe.co.uk>

	* g++.dg/coroutines/pr93458-1-missing-traits.C: New test.
	* g++.dg/coroutines/pr93458-2-bad-traits.C: New test.
	* g++.dg/coroutines/pr93458-3-missing-handle.C: New test.
	* g++.dg/coroutines/pr93458-4-bad-coro-handle.C: New test.
	* g++.dg/coroutines/pr93458-5-bad-coro-type.C: New test.
2020-02-03 19:48:23 +00:00
David Malcolm
833f1e66e3 analyzer: avoid use of fold_build2
Various places in the analyzer use fold_build2, test the result, then
discard it.  It's more efficient to use fold_binary, which avoids
building and GC-ing a redundant tree for the cases where folding fails.

gcc/analyzer/ChangeLog:
	* constraint-manager.cc (range::constrained_to_single_element):
	Replace fold_build2 with fold_binary.  Remove unnecessary newline.
	(constraint_manager::get_or_add_equiv_class): Replace fold_build2
	with fold_binary in two places, and remove out-of-date comment.
	(constraint_manager::eval_condition): Replace fold_build2 with
	fold_binary.
	* region-model.cc (constant_svalue::eval_condition): Likewise.
	(region_model::on_assignment): Likewise.
2020-02-03 14:31:15 -05:00
David Malcolm
8525d1f5f5 analyzer: detect zero-assignment in phis (PR 93544)
PR analyzer/93544 reports an ICE when attempting to report a double-free
within diagnostic_manager::prune_for_sm_diagnostic, in which the
variable of interest has become an INTEGER_CST.  Additionally, it picks
a nonsensical path through the function in which the pointer being
double-freed is known to be NULL, which we shouldn't complain about.

The dump shows that it picks the INTEGER_CST when updating var at a phi
node:
    considering event 4, with var: ‘iftmp.0_2’, state: ‘start’
    updating from ‘iftmp.0_2’ to ‘0B’ based on phi node
      phi: iftmp.0_2 = PHI <iftmp.0_6(3), 0B(2)>
    considering event 3, with var: ‘0B’, state: ‘start’
and that it has picked the shortest path through the exploded graph,
and on this path the pointer has been assigned NULL.

The root cause is that the state machine's on_stmt isn't called for phi
nodes (and wouldn't make much sense, as we wouldn't know which arg to
choose).  malloc state machine::on_stmt "sees" a GIMPLE_ASSIGN to NULL
and handles it by transitioning the lhs to the "null" state, but never
"sees" GIMPLE_PHI nodes.

This patch fixes the ICE by wiring up phi-handling with state machines,
so that state machines have an on_phi vfunc.  It updates the only current
user of "is_zero_assignment" (the malloc sm) to implement equivalent
logic for phi nodes.  Doing so ensures that the pointer is in a separate
sm-state for the NULL vs non-NULL cases, and so gets separate exploded
nodes, and hence the path-finding logic chooses the correct path, and
the correct non-NULL phi argument.

The patch also adds some bulletproofing to prune_for_sm_diagnostic to
avoid crashing in the event of a bad path.

gcc/analyzer/ChangeLog:
	PR analyzer/93544
	* diagnostic-manager.cc
	(diagnostic_manager::prune_for_sm_diagnostic): Bulletproof
	against bad choices due to bad paths.
	* engine.cc (impl_region_model_context::on_phi): New.
	* exploded-graph.h (impl_region_model_context::on_phi): New decl.
	* region-model.cc (region_model::on_longjmp): Likewise.
	(region_model::handle_phi): Add phi param.  Call the ctxt's on_phi
	vfunc.
	(region_model::update_for_phis): Pass phi to handle_phi.
	* region-model.h (region_model::handle_phi): Add phi param.
	(region_model_context::on_phi): New vfunc.
	(test_region_model_context::on_phi): New.
	* sm-malloc.cc (malloc_state_machine::on_phi): New.
	(malloc_state_machine::on_zero_assignment): New.
	* sm.h (state_machine::on_phi): New vfunc.

gcc/testsuite/ChangeLog:
	PR analyzer/93544
	* gcc.dg/analyzer/torture/pr93544.c: New test.
2020-02-03 14:29:08 -05:00
David Malcolm
73f386581b analyzer: show BBs in .dot dumps
gcc/analyzer/ChangeLog:
	* engine.cc (supernode_cluster::dump_dot): Show BB index as
	well as SN index.
	* supergraph.cc (supernode::dump_dot): Likewise.
2020-02-03 14:27:04 -05:00
David Malcolm
5e10b9a28b analyzer: fix ICE merging models containing label pointers (PR 93546)
PR analyzer/93546 reports an ICE within region_model::add_region_for_type
when merging two region_models each containing a label pointer.  The
two labels are stored as pointers to symbolic_regions, but these regions
were created with NULL type, leading to an assertion failure when a
merged copy is created.

The labels themselves have void (but not NULL) type.

This patch updates make_region_for_type to use the type of the decl when
creating such regions, rather than implicitly setting the region's type
to NULL, fixing the ICE.

gcc/analyzer/ChangeLog:
	PR analyzer/93546
	* region-model.cc (region_model::on_call_pre): Update for new
	param of symbolic_region ctor.
	(region_model::deref_rvalue): Likewise.
	(region_model::add_new_malloc_region): Likewise.
	(make_region_for_type): Likewise, preserving type.
	* region-model.h (symbolic_region::symbolic_region): Add "type"
	param and pass it to base class ctor.

gcc/testsuite/ChangeLog:
	PR analyzer/93546
	* gcc.dg/analyzer/pr93546.c: New test.
2020-02-03 14:25:39 -05:00
David Malcolm
287ccd3bd6 analyzer: fix ICE due to comparing int and real constants (PR 93547)
gcc/analyzer/ChangeLog:
	PR analyzer/93547
	* constraint-manager.cc
	(constraint_manager::get_or_add_equiv_class): Ensure types are
	compatible before comparing constants.

gcc/testsuite/ChangeLog:
	PR analyzer/93547
	* gcc.dg/analyzer/pr93547.c: New test.
2020-02-03 14:23:27 -05:00
Segher Boessenkool
e01975f97c rs6000: Update constraint documentation
This un-documents constraints that cannot (or should not) be used in
inline assembler.  It also improves markup, and presentation in general.

More work is needed, but gradual improvement is easier to do.

	* config/rs6000/constraints.md: Improve documentation.
/
	* doc/md.texi (PowerPC and IBM RS6000): Improve documentation.
2020-02-03 18:23:51 +00:00
Richard Earnshaw
492c63e5b7 arm: Use move-if-change for updating regenerated files [PR93548]
The t-arm make fragment currently uses 'mv' to update some files that
are automatically regenerated, but this causes problems on read-only
filesystems if the date stamps are incorrect and the files have not
really changed.  So use move-if-change instead.

	PR target/93548
	* config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md,
	$(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
2020-02-03 17:40:55 +00:00
Andrew Stubbs
591f869ad7 Remove gfx801 "carrizo" support
2020-02-03  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config.gcc: Remove "carrizo" support.
	* config/gcn/gcn-opts.h (processor_type): Likewise.
	* config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
	* config/gcn/gcn.opt (gpu_type): Likewise.
	* config/gcn/t-omp-device: Likewise.

	libgomp/
	* plugin/plugin-gcn.c (EF_AMDGPU_MACH_AMDGCN_GFX801): Remove.
	(gcn_gfx801_s): Remove.
	(isa_hsa_name): Remove gfx801.
	(isa_gcc_name): Remove gfx801/carizzo.
	(isa_code): Remove gfx801.
2020-02-03 17:23:18 +00:00
Jason Merrill
3539fc1317 c++: Fix cast to pointer to VLA.
The C front-end fixed this issue in r257620 by adding a DECL_EXPR from
grokdeclarator.  We don't have an easy way to do that in the C++ front-end,
but it works fine to create and prepend a DECL_EXPR when we are genericizing
the NOP_EXPR for the cast.

The C patch wraps the DECL_EXPR in a BIND_EXPR, but that seems unnecessary
in C++; this is just a hook to run gimplify_type_sizes, we aren't actually
declaring anything that we need to worry about scoping for.

	PR c++/88256
	* cp-gimplify.c (predeclare_vla): New.
	(cp_genericize_r) [NOP_EXPR]: Call it.
2020-02-03 09:21:06 -05:00
Stam Markianos-Wright
44f77a6dea This patch is for PR target/91816
This is a patch for an issue where the compiler was generating a conditional
branch in Thumb2, which was too far for b{cond} to handle.

This was originally reported at binutils:
https://sourceware.org/bugzilla/show_bug.cgi?id=24991

And then raised for GCC:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91816

As can be seen here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cihfddaf.html

the range of a 32-bit Thumb B{cond} is +/-1MB.

This is now checked for in arm.md and an unconditional branch is generated if
the jump would be greater than 1MB.

gcc/ChangeLog

2020-02-03  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	PR target/91816
	* config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
	* config/arm/arm.c (arm_gen_far_branch): New function
	arm_gen_far_branch.
	* config/arm/arm.md: Update b<cond> for Thumb2 range checks.

gcc/testsuite/ChangeLog

2020-02-03  Stam Markianos-Wright  <stam.markianos-wright@arm.com>

	PR target/91816
	* gcc.target/arm/pr91816.c: New test.
2020-02-03 10:30:59 +00:00
Tobias Burnus
e464fc9035 [OpenACC] bump version for 2.6 plus libgomp.texi update
2020-02-03  Julian Brown  <julian@codesourcery.com>
            Tobias Burnus  <tobias@codesourcery.com>

	gcc/c-family/
	* c-cppbuiltin.c (c_cpp_builtins): Update _OPENACC define to 201711.

	gcc/
	* doc/invoke.texi: Update mention of OpenACC version to 2.6.

	gcc/fortran/
	* cpp.c (cpp_define_builtins): Update _OPENACC define to 201711.
	* intrinsic.texi: Update mentions of OpenACC version to 2.6.
	* gfortran.texi: Likewise. Remove experimental disclamer for OpenACC.
	* invoke.texi: Remove experimental disclamer for OpenACC.

	gcc/testsuite/
	* c-c++-common/cpp/openacc-define-3.c: Update expected value for
	_OPENACC define.
	* gfortran.dg/openacc-define-3.f90: Likewise.

	libgomp/
	* libgomp.texi (OpenACC Runtime Library Routines): Document *_async
	and *_finalize variants; document acc_attach and acc_detach; update
	references from OpenACC 2.0 to 2.6.
	* openacc.f90 (openacc_version): Update to 201711.
	* openacc_lib.h (openacc_version): Update to 201711.
	* testsuite/libgomp.oacc-fortran/openacc_version-1.f: Update expected
	openacc_version to 201711.
	* testsuite/libgomp.oacc-fortran/openacc_version-2.f90: Likewise.
2020-02-03 10:10:37 +01:00
Tobias Burnus
7c8e1f920a [OpenMP] Add missing parameters to omp_lib documentation (PR fortran/93541)
PR fortran/93541
	* intrinisic.texi (OpenMP Modules OMP_LIB and OMP_LIB_KINDS):
	Add undocumented parameters from omp_lib.f90.in.
2020-02-03 10:02:47 +01:00
Tobias Burnus
ae86ede8e9 [Fortran] Fix to strict associate check (PR93427)
PR fortran/93427
        * resolve.c (resolve_assoc_var): Remove too strict check.
        * gfortran.dg/associate_51.f90: Update test case.

        PR fortran/93427
        * gfortran.dg/associate_52.f90: New.
2020-02-03 10:00:07 +01:00
Jakub Jelinek
f626ae5478 s390x: Fix popcounthi2_z196 expander [PR93533]
The following testcase started to ICE when .POPCOUNT matching has been added
to match.pd; we had __builtin_popcount*, but nothing would use the
popcounthi2 expander before.

The problem is that the popcounthi2_z196 expander doesn't emit valid RTL:
error: unrecognizable insn:
(insn 138 137 139 27 (set (reg:SI 190)
        (ashift:SI (reg:HI 95 [ _105 ])
            (const_int 8 [0x8]))) -1
     (nil))
during RTL pass: vregs
The following patch is an attempt to fix that, furthermore I've tried to
slightly simplify it as well, it makes no sense to me to perform
(x + (x << 8)) >> 8 when we need to either zero extend or mask the result
at the end in order to avoid bits from above HImode to affect it, when we
can do
(x + (x >> 8)) & 0xff (or zero extension).

2020-02-03  Jakub Jelinek  <jakub@redhat.com>

	PR target/93533
	* config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
	valid RTL to sum up the lowest and second lowest bytes of the popcnt
	result.

	* gcc.c-torture/compile/pr93533.c: New test.
	* gcc.target/s390/pr93533.c: New test.
2020-02-03 09:03:12 +01:00
JunMa
c3ccce5b47 coroutines: Bind label_decl of original function to actor function
gcc/cp
    * coroutines.cc (transform_await_wrapper): Set actor funcion as
    new context of label_decl.
    (build_actor_fn): Fill new field of await_xform_data.

gcc/testsuite
    * g++.dg/coroutines/co-await-04-control-flow.C: Add label.
2020-02-03 09:24:27 +08:00
GCC Administrator
75201e825d Daily bump. 2020-02-03 00:16:55 +00:00
Marek Polacek
b817be038d c++: Fix ICE on invalid alignas in a template [PR93530]
This fixes an ICE taking place in cp_default_conversion because we got
a SCOPE_REF that doesn't have a type and so checking
INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (TREE_TYPE (exp)) will crash.
This happens since the recent Joseph's change in decl_attributes whereby
we don't skip C++11 attributes on types.

[dcl.align] is clear that alignas applied to a function is ill-formed.
That should be fixed, and we have PR90847 for that.  But I think a more
appropriate fix at this stage would be the following: in a template we
want to splice dependent attributes and save them for later, and by
doing so avoid this crash.

	PR c++/93530 - ICE on invalid alignas in a template.
	* decl.c (grokdeclarator): Call cplus_decl_attributes instead of
	decl_attributes.

	* g++.dg/cpp0x/alignas18.C: New test.
2020-02-02 15:30:21 -05:00
Iain Sandoe
26a591f2a4 testsuite,Darwin,PPC: Adjust darwin-abi-12.c for common section use.
This test explicitly tests for code generation that expects a
common section.

gcc/testsuite/ChangeLog:

2020-02-02  Iain Sandoe  <iain@sandoe.co.uk>

* gcc.target/powerpc/darwin-abi-12.c: Add '-fcommon' to the
options.
2020-02-02 19:53:24 +00:00
Vladimir N. Makarov
897a73086b One more fix for PR 91333 - suboptimal register allocation for inline asm
2020-02-02  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/91333
	* ira-color.c (struct allocno_color_data): Add member
	hard_reg_prefs.
	(init_allocno_threads): Set the member up.
	(bucket_allocno_compare_func): Add compare hard reg
	prefs.

2020-02-02  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/91333
	* gcc.target/i386/pr91333.c: Add vmovsd to regexp.  Set up count
	to 3.
2020-02-02 11:27:47 -05:00
GCC Administrator
0303907ea5 Daily bump. 2020-02-02 00:16:33 +00:00
Jakub Jelinek
add31061ec fortran: Fix up TYPE_ARG_TYPES of procs with scalar VALUE optional args [PR92305]
The following patch fixes
-FAIL: libgomp.fortran/use_device_addr-1.f90   -O0  execution test
-FAIL: libgomp.fortran/use_device_addr-2.f90   -O0  execution test
that has been FAILing for several months on powerpc64le-linux.
The problem is in the Fortran FE, which adds the artificial arguments
for scalar VALUE OPTIONAL dummy args only to DECL_ARGUMENTS where the
current function can see them, but not to TYPE_ARG_TYPES; if those functions
aren't varargs, this confuses calls.c to pass the remaining arguments
(which aren't named (== not covered by TYPE_ARG_TYPES) and aren't varargs
either) in a different spot from what the callee (which has proper
DECL_ARGUMENTS for all args) expects.  For the artificial length arguments
for character dummy args we already put them in both DECL_ARGUMENTS and
TYPE_ARG_TYPES.

2020-02-01  Jakub Jelinek  <jakub@redhat.com>

	PR fortran/92305
	* trans-types.c (gfc_get_function_type): Also push boolean_type_node
	types for non-character scalar VALUE optional dummy arguments.
	* trans-decl.c (create_function_arglist): Skip those in
	hidden_typelist.  Formatting fix.
2020-02-01 10:02:20 +01:00
Sandra Loosemore
2d33dcfe9f nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
On nios2-linux-gnu, there has been a long-standing bug in C++ exception
handling that sometimes resulted in link errors like

../nios2-linux-gnu/bin/ld: FDE encoding in /tmp/cccfpQ2l.o(.eh_frame) prevents .eh_frame_hdr table being created

when building some shared libraries or PIE executables.  The root of
the problem is that GCC was incorrectly emitting an absolute encoding
in EH tables for PIC.  This patch changes it to use either
DW_EH_PE_indirect (for global) or DW_EH_PE_datarel (for local), and
fixes libgcc so it can find the address of the GOT as the base address
for DW_EH_PE_datarel.

Complicating matters somewhat, GAS was missing support for
%gotoff(symbol) relocation syntax.  I have just pushed a fix for that,
but I've added a configure check to test for presence of the binutils
support and fall back to the current absolute encoding (which works
most of the time) if it is not available.  Once the fix makes it into
an official binutils release it might be appropriate to make this
error out instead.

Since this is a wrong-code bug and affects only nios2 target, I think
this is appropriate for Stage 4.  I regression-tested on both
nios2-linux-gnu and nios2-elf, with and without the binutils support
present, before committing this.

2020-01-31  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
	* config.in: Regenerated.
	* configure: Regenerated.
	* config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
	for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
	(ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.

	gcc/testsuite/
	* g++.target/nios2/hello-pie.C: New.
	* g++.target/nios2/nios2.exp: New.

	libgcc/
	* config.host [nios2-*-linux*] (tmake_file, tm_file): Adjust.
	* config/nios2-elf-lib.h: New.
	* unwind-dw2-fde-dip.c (_Unwind_IteratePhdrCallback): Use existing
	code for finding GOT base for nios2.
2020-01-31 16:46:50 -08:00
Andrew Burgess
20fa702b32 Fixes after recent configure changes relating to static libraries
This commit:

  commit e7c26e04b2 (tjteru/master)
  Date:   Wed Jan 22 14:54:26 2020 +0000

      gcc: Add new configure options to allow static libraries to be selected

contains a couple of issues.  First I failed to correctly regenerate
all of the configure files it should have done.  Second, there was a
mistake in lib-link.m4, one of the conditions didn't use pure sh
syntax, I wrote this:

  if x$lib_type = xauto || x$lib_type = xshared; then

When I should have written this:

  if test "x$lib_type" = "xauto" || test "x$lib_type" = "xshared"; then

These issues were raised on the mailing list in these messages:

  https://gcc.gnu.org/ml/gcc-patches/2020-01/msg01827.html
  https://gcc.gnu.org/ml/gcc-patches/2020-01/msg01921.html

config/ChangeLog:

	* lib-link.m4 (AC_LIB_LINKFLAGS_BODY): Update shell syntax.

gcc/ChangeLog:

	* configure: Regenerate.

intl/ChangeLog:

	* configure: Regenerate.

libcpp/ChangeLog:

	* configure: Regenerate.

libstdc++-v3/ChangeLog:

	* configure: Regenerate.
2020-02-01 00:34:28 +00:00
GCC Administrator
d1a8030386 Daily bump. 2020-02-01 00:16:32 +00:00
Jason Merrill
00a49cd840 c++: Fix sizeof VLA lambda capture.
sizeof a VLA type is not a constant in C or the GNU C++ extension, so we
need to capture the VLA even in unevaluated context.  For PR60855 we stopped
looking through a previous capture, but we also need to capture the first
time the variable is mentioned.

	PR c++/86216
	* semantics.c (process_outer_var_ref): Capture VLAs even in
	unevaluated context.
2020-01-31 19:06:37 -05:00
Jason Merrill
e98ebda074 c++: Reduce memory consumption for arrays of non-aggregate type.
The remaining low-hanging fruit for improvement on memory consumption in the
14179 testcase was the duplication of the CONSTRUCTOR for the array by
reshape_init.  This patch changes reshape_init to reuse a single constructor
for an array of non-aggregate type such as the one in the testcase.

	PR c++/14179
	* decl.c (reshape_init_array_1): Reuse a single CONSTRUCTOR with
	non-aggregate elements.
	(reshape_init_array): Add first_initializer_p parm.
	(reshape_init_r): Change first_initializer_p from bool to tree.
	(reshape_init): Pass init to it.
2020-01-31 18:19:31 -05:00
Jason Merrill
d2b9548f38 c++: Reduce memory consumption for large static arrays.
PR14179 and the C counterpart PR12245 are about memory consumption of very
large file-scope arrays.  Recently, location wrappers increased memory
consumption significantly: in an array of integer constants, each one will
have a location wrapper, which added up to over 500MB in the 14179
testcase.  For this kind of testcase tracking these locations isn't worth
the cost, so this patch turns the wrappers off after 256 elements; any array
that size or larger isn't likely to be interested in the location of
individual integer constants.

	PR c++/14179
	* parser.c (cp_parser_initializer_list): Suppress location wrappers
	after 256 elements.
2020-01-31 18:19:31 -05:00
David Malcolm
6775172431 analyzer: fix ICE with 'const void *' (PR 93457)
gcc/analyzer/ChangeLog:
	PR analyzer/93457
	* region-model.cc (make_region_for_type): Use VOID_TYPE_P rather
	than checking against void_type_node.

gcc/testsuite/ChangeLog:
	PR analyzer/93457
	* gcc.dg/analyzer/pr93457.c: New test.
2020-01-31 17:26:41 -05:00
David Malcolm
09bea5845a analyzer: fix ICE handling void-type (PR 93373)
gcc/analyzer/ChangeLog:
	PR analyzer/93373
	* region-model.cc (ASSERT_COMPAT_TYPES): Convert to...
	(assert_compat_types): ...this, and bail when either type is NULL,
	or when VOID_TYPE_P (dst_type).
	(region_model::get_lvalue): Update for above conversion.
	(region_model::get_rvalue): Likewise.

gcc/testsuite/ChangeLog:
	PR analyzer/93373
	* gcc.dg/analyzer/torture/pr93373.c: New test.
2020-01-31 17:24:42 -05:00
Vladimir N. Makarov
2a07345c4f Fix for PR 91333 - suboptimal register allocation for inline asm
2020-01-31  Vladimir Makarov  <vmakarov@redhat.com>

            PR rtl-optimization/91333
            * ira-color.c (bucket_allocno_compare_func): Move conflict hard
            reg preferences comparison up.

    2020-01-31  Vladimir Makarov  <vmakarov@redhat.com>

            PR rtl-optimization/91333
            * gcc.target/i386/pr91333.c: New.
2020-01-31 15:00:38 -05:00
David Malcolm
f1c807e887 analyzer: fix ICE getting void return value (PR 93379)
PR analyzer/93379 reports an ICE within
region_model::update_for_return_superedge when writing the
returned svalue_id to the lhs of the call_stmt

The root cause is that this analyzer code assumed that for any call
with a non-NULL gimple_call_lhs, the called fndecl would have non-void
return type, and thus that a non-null svalue_id would be returned from
region_model::pop_frame.  This isn't the case e.g. for a call with
conflicting types where the callee returns void but the caller assumes
int.

This patch fixes the ICE by moving the check for null result so that
it also guards setting the lhs.

gcc/analyzer/ChangeLog:
	PR analyzer/93379
	* region-model.cc (region_model::update_for_return_superedge):
	Move check for null result so that it also guards setting the
	lhs.

gcc/testsuite/ChangeLog:
	PR analyzer/93379
	* gcc.dg/analyzer/torture/pr93379-2.c: New test.
	* gcc.dg/analyzer/torture/pr93379.c: New test.
2020-01-31 14:29:09 -05:00
David Malcolm
455f58ec50 analyzer: fix ICE with pointers between stack frames (PR 93438)
PR analyzer/93438 reports an ICE when merging two region_models
in which an older stack frame has a local pointing to a local in
a more recent stack frame.

  stack
    older frame
      int *: "ow" --+
                    |
    newer frame     |
      int: "pk" <---+

The root cause is that the state-merging code assumes that all frame
regions in the merged model have already been created.
stack_region::can_merge_p iterates through the frames, creating
and populating each merged frame in turn, so when it attempts to
populate the older frame, it attempts to reference the newer frame in
the merged model, which doesn't exist yet.

This patch reworks stack_region::can_merge_p to use a two-pass approach
in which all frames in the merged model are created first, and then
are all populated, fixing the bug.

gcc/analyzer/ChangeLog:
	PR analyzer/93438
	* region-model.cc (stack_region::can_merge_p): Split into a two
	pass approach, creating all stack regions first, then populating
	them.
	(selftest::test_state_merging): Add test coverage for (a) the case
	of self-merging a model in which a local in an older stack frame
	points to a local in a more recent stack frame (which previously
	would ICE), and (b) the case of self-merging a model in which a
	local points to a global (which previously worked OK).

gcc/testsuite/ChangeLog:
	PR analyzer/93438
	* gcc.dg/analyzer/torture/pr93438.c: New test.
	* gcc.dg/analyzer/torture/pr93438-2.c: New test.
2020-01-31 14:26:44 -05:00
Jakub Jelinek
5910b14503 testsuite: Fix up pr91838.C test [PR91838]
The test FAILs on i686-linux with:
FAIL: g++.dg/pr91838.C   (test for excess errors)
Excess errors:
/home/jakub/src/gcc/gcc/testsuite/g++.dg/pr91838.C:7:8: warning: MMX vector return without MMX enabled changes the ABI [-Wpsabi]
/home/jakub/src/gcc/gcc/testsuite/g++.dg/pr91838.C:7:3: warning: MMX vector argument without MMX enabled changes the ABI [-Wpsabi]
and on x86_64-linux with -m32 testing with failure to match the
expected pattern in there (or both with e.g. -m32/-mno-mmx/-mno-sse testing).
The test is also in a wrong directory, has non-standard specification that
it requires c++11 or later.

2020-01-31  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/91838
	* g++.dg/pr91838.C: Moved to ...
	* g++.dg/opt/pr91838.C: ... here.  Require c++11 target instead of
	dg-skip-if for c++98.  Pass -Wno-psabi -w to avoid psabi style
	warnings on vector arg passing or return.  Add -masm=att on i?86/x86_64.
	Only check for pxor %xmm0, %xmm0 on lp64 i?86/x86_64.
2020-01-31 19:35:11 +01:00
Richard Sandiford
896dff99e1 aarch64: Add Armv8.6 SVE bfloat16 support
This patch adds support for the SVE intrinsics that map to Armv8.6
bfloat16 instructions.  This means that svcvtnt is now a base SVE
function for one type suffix combination; the others are still
SVE2-specific.

This relies on a binutils fix:

    https://sourceware.org/ml/binutils/2020-01/msg00450.html

so anyone testing older binutils 2.34 or binutils master sources will
need to upgrade to get clean test results.  (At the time of writing,
no released version of binutils has this bug.)

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
	* config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
	aarch64-sve-builtins-base.h.
	* config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
	aarch64-sve-builtins-base.cc.
	* config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
	(svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
	(svcvtnt): Declare.
	* config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
	(svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
	(svcvtnt): New functions.
	* config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
	(svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
	(svcvtnt): New functions.
	(svcvt): Add a form that converts f32 to bf16.
	* config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
	(ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
	Declare.
	* config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
	Treat B as bfloat16_t.
	(ternary_bfloat_lane_base): New class.
	(ternary_bfloat_def): Likewise.
	(ternary_bfloat): New shape.
	(ternary_bfloat_lane_def): New class.
	(ternary_bfloat_lane): New shape.
	(ternary_bfloat_lanex2_def): New class.
	(ternary_bfloat_lanex2): New shape.
	(ternary_bfloat_opt_n_def): New class.
	(ternary_bfloat_opt_n): New shape.
	* config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
	* config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
	(@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
	(@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
	(@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
	(*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
	(@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
	* config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
	the pattern off the narrow mode instead of the wider one.
	* config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
	(UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
	(sve_fp_op): Handle them.
	(SVE_BFLOAT_TERNARY_LONG): New int itertor.
	(SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_aarch64_asm_bf16_ok):
	New proc.
	* gcc.target/aarch64/sve/acle/asm/bfdot_f32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/bfdot_lane_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/bfmlalb_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/bfmlalb_lane_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/bfmlalt_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/bfmlalt_lane_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/bfmmla_f32.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/cvt_bf16.c: Likweise.
	* gcc.target/aarch64/sve/acle/asm/cvtnt_bf16.c: Likweise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_bfloat16_1.c: Likweise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_bfloat16_lane_1.c:
	Likweise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_bfloat16_lanex2_1.c:
	Likweise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_bfloat16_opt_n_1.c:
	Likweise.
2020-01-31 17:40:40 +00:00
Richard Sandiford
02fcd8ac40 aarch64: Add svbfloat16_t support to arm_sve.h
This patch adds support for the bfloat16-related vectors to
arm_sve.h.  It also adds support for functions that just treat
bfloat16_t as a bag of 16 bits; these functions are available
for bf16 whenever they're available for other 16-bit types.

Previously "all_data" was used for both data movement and for arithmetic
that happened to be defined for all data types.  Adding bf16 means we
need to distinguish between the two cases.

The patch also reorders the mode definitions in aarch64-modes.def,
which means we no longer need separate VECTOR_MODE entries for BF
vectors.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/arm_sve.h: Include arm_bf16.h.
	* config/aarch64/aarch64-modes.def (BF): Move definition before
	VECTOR_MODES.  Remove separate VECTOR_MODES for V4BF and V8BF.
	(SVE_MODES): Handle BF modes.
	* config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
	BF modes.
	(aarch64_full_sve_mode): Likewise.
	* config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
	and VNx32BF.
	(SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
	(Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
	(V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
	(insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
	new SVE BF modes.
	* config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
	type_class_index.
	* config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
	(TYPES_all_data): Add bf16.
	(TYPES_reinterpret1, TYPES_reinterpret): Likewise.
	(register_tuple_type): Increase buffer size.
	* config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
	(bf16): New type suffix.
	* config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
	(svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
	(svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
	Change type from all_data to all_arith.
	* config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
	(svminp): Likewise.

gcc/testsuite/
	* g++.target/aarch64/sve/acle/general-c++/mangle_1.C: Test mangling
	of svbfloat16_t.
	* g++.target/aarch64/sve/acle/general-c++/mangle_2.C: Likewise for
	__SVBfloat16_t.
	* gcc.target/aarch64/sve/acle/asm/clasta_bf16.c: New test.
	* gcc.target/aarch64/sve/acle/asm/clastb_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/cnt_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/create2_1.c (create_bf16): Likewise.
	* gcc.target/aarch64/sve/acle/asm/create3_1.c (create_bf16): Likewise.
	* gcc.target/aarch64/sve/acle/asm/create4_1.c (create_bf16): Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dup_lane_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/dupq_lane_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ext_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/get2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/get3_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/get4_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/insr_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/lasta_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/lastb_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1rq_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld3_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld4_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ldff1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ldnf1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ldnt1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/len_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_f16.c
	(reinterpret_f16_bf16_tied1, reinterpret_f16_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_f32.c
	(reinterpret_f32_bf16_tied1, reinterpret_f32_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_f64.c
	(reinterpret_f64_bf16_tied1, reinterpret_f64_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_s16.c
	(reinterpret_s16_bf16_tied1, reinterpret_s16_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_s32.c
	(reinterpret_s32_bf16_tied1, reinterpret_s32_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_s64.c
	(reinterpret_s64_bf16_tied1, reinterpret_s64_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_s8.c
	(reinterpret_s8_bf16_tied1, reinterpret_s8_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_u16.c
	(reinterpret_u16_bf16_tied1, reinterpret_u16_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_u32.c
	(reinterpret_u32_bf16_tied1, reinterpret_u32_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_u64.c
	(reinterpret_u64_bf16_tied1, reinterpret_u64_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/reinterpret_u8.c
	(reinterpret_u8_bf16_tied1, reinterpret_u8_bf16_untied): Likewise.
	* gcc.target/aarch64/sve/acle/asm/rev_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/sel_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/set2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/set3_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/set4_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/splice_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/st1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/st2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/st3_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/st4_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/stnt1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/tbl_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/undef2_1.c (bfloat16_t): Likewise.
	* gcc.target/aarch64/sve/acle/asm/undef3_1.c (bfloat16_t): Likewise.
	* gcc.target/aarch64/sve/acle/asm/undef4_1.c (bfloat16_t): Likewise.
	* gcc.target/aarch64/sve/acle/asm/undef_1.c (bfloat16_t): Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2_bf16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_1.c (ret_bf16, ret_bf16x2)
	(ret_bf16x3, ret_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_2.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_3.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_4.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_5.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_6.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/annotate_7.c (fn_bf16, fn_bf16x2)
	(fn_bf16x3, fn_bf16x4): Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_le_bf16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_6_be_bf16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_6_le_bf16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/gnu_vectors_1.c (bfloat16x16_t): New
	typedef.
	(bfloat16_callee, bfloat16_caller): New tests.
	* gcc.target/aarch64/sve/pcs/gnu_vectors_2.c (bfloat16x16_t): New
	typedef.
	(bfloat16_callee, bfloat16_caller): New tests.
	* gcc.target/aarch64/sve/pcs/return_4.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_4_128.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_4_256.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_4_512.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_4_1024.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_4_2048.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5_128.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5_256.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5_512.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5_1024.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_5_2048.c (CALLER_BF16): New macro.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6_128.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6_256.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6_512.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6_1024.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_6_2048.c (bfloat16_t): New typedef.
	(callee_bf16, caller_bf16): New tests.
	* gcc.target/aarch64/sve/pcs/return_7.c (callee_bf16): Likewise
	(caller_bf16): Likewise.
	* gcc.target/aarch64/sve/pcs/return_8.c (callee_bf16): Likewise
	(caller_bf16): Likewise.
	* gcc.target/aarch64/sve/pcs/return_9.c (callee_bf16): Likewise
	(caller_bf16): Likewise.
	* gcc.target/aarch64/sve2/acle/asm/tbl2_bf16.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/tbx_bf16.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/whilerw_bf16.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/whilewr_bf16.c: Likewise.
2020-01-31 17:40:39 +00:00
Richard Sandiford
3669677425 aarch64: Add Armv8.6 SVE matrix multiply support
This mostly follows existing practice.  Perhaps the only noteworthy
thing is that svmmla is split across three extensions (i8mm, f32mm
and f64mm), any of which can be enabled independently.  The easiest
way of coping with this seemed to be to add a fourth svmmla entry
for base SVE, but with no type suffixes.  This means that the
overloaded function is always available for C, but never successfully
resolves without the appropriate target feature.

2020-01-31  Dennis Zhang  <dennis.zhang@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>
	    Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
	__ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
	__ARM_FEATURE_SVE_MATMUL_FP64 as appropriate.  Don't define
	__ARM_FEATURE_MATMUL_FP64.
	* config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
	(sve): Add AARCH64_FL_F32MM to the list of extensions that should
	be disabled at the same time.
	(f32mm): New extension.
	* config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
	(AARCH64_FL_F64MM): Bump to the next bit up.
	(AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
	(TARGET_SVE_F64MM): New macros.
	* config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
	(UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
	(UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
	(UNSPEC_ZIP2Q): New unspeccs.
	(DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
	(optab, sur, perm_insn): Handle the new unspecs.
	(sve_fp_op): Handle UNSPEC_FMMLA.  Resort.
	* config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
	TARGET_SVE_F64MM instead of separate tests.
	(@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
	(@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
	(@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
	(@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
	(@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
	* config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
	(TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
	(TYPES_s_signed): New macro.
	(TYPES_s_integer): Use it.
	(TYPES_d_float): New macro.
	(TYPES_d_data): Use it.
	* config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
	(ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
	(ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
	* config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
	(svmmla): New shape.
	(ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
	template parameters.
	(ternary_resize2_lane_base): Likewise.
	(ternary_resize2_base): New class.
	(ternary_qq_lane_base): Likewise.
	(ternary_intq_uintq_lane_def): Likewise.
	(ternary_intq_uintq_lane): New shape.
	(ternary_intq_uintq_opt_n_def): New class
	(ternary_intq_uintq_opt_n): New shape.
	(ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
	(ternary_uintq_intq_def): New class.
	(ternary_uintq_intq): New shape.
	(ternary_uintq_intq_lane_def): New class.
	(ternary_uintq_intq_lane): New shape.
	(ternary_uintq_intq_opt_n_def): New class.
	(ternary_uintq_intq_opt_n): New shape.
	* config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
	(svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
	(svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
	* config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
	Generalize to...
	(svdotprod_lane_impl): ...this new class.
	(svmmla_impl, svusdot_impl): New classes.
	(svdot_lane): Update to use svdotprod_lane_impl.
	(svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
	(svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
	functions.
	* config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
	function, with no types defined.
	(svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
	AARCH64_FL_I8MM functions.
	(svmmla): New AARCH64_FL_F32MM function.
	(svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
	(svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
	AARCH64_FL_F64MM function.
	(REQUIRED_EXTENSIONS):

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_aarch64_asm_i8mm_ok)
	(check_effective_target_aarch64_asm_f32mm_ok): New target selectors.
	* gcc.target/aarch64/pragma_cpp_predefs_2.c: Test handling of
	__ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
	__ARM_FEATURE_SVE_MATMUL_FP64.
	* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_TRIPLE_Z):
	(TEST_TRIPLE_Z_REV2, TEST_TRIPLE_Z_REV, TEST_TRIPLE_LANE_REG)
	(TEST_TRIPLE_ZX): New macros.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: Remove +sve and
	rely on +f64mm to enable it.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/mmla_f32.c: New test.
	* gcc.target/aarch64/sve/acle/asm/mmla_f64.c: Likewise,
	* gcc.target/aarch64/sve/acle/asm/mmla_s32.c: Likewise,
	* gcc.target/aarch64/sve/acle/asm/mmla_u32.c: Likewise,
	* gcc.target/aarch64/sve/acle/asm/sudot_lane_s32.c: Likewise,
	* gcc.target/aarch64/sve/acle/asm/sudot_s32.c: Likewise,
	* gcc.target/aarch64/sve/acle/asm/trn1q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn1q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/trn2q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/usdot_lane_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/usdot_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/usmmla_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip1q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_f16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/zip2q_u8.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_1.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_2.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_3.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_4.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_5.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_6.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/mmla_7.c: Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_intq_uintq_lane_1.c:
	Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_intq_uintq_opt_n_1.c:
	Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_uintq_intq_1.c:
	Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_uintq_intq_lane_1.c:
	Likewise.
	* gcc.target/aarch64/sve/acle/general-c/ternary_uintq_intq_opt_n_1.c:
	Likewise.
2020-01-31 17:40:38 +00:00