This solves an issue where rv32i, etc. are canonicalized to rv32imafd
since the g->i addition of 'm', 'a', 'f', 'd' is not actually gated by
whether the input was rv32g/rv64g.
gcc/ChangeLog:
* config/riscv/arch-canonicalize: Only add mafd extension if
base was rv32/rv64g.
(cherry picked from commit 63f198553d)
rv64gcv should exapnd into:
rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
but we exapnd fd twice for now:
rv64imafdfdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
gcc/ChangeLog:
* config/riscv/arch-canonicalize: Handle g correctly.
(cherry picked from commit 27239e13b1)
Currently on i386, -fzero-call-used-regs uses a pattern of:
XOR regA,regA
MOV regA,regB
MOV regA,regC
...
RET
However, this introduces both a register ordering dependency (e.g. the CPU
cannot clear regB without clearing regA first), and while greatly reduces
available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets
at the end of functions (e.g. "MOV regA,regC; RET").
This patch will switch to always use XOR on i386:
XOR regA,regA
XOR regB,regB
XOR regC,regC
...
RET
gcc/ChangeLog:
PR target/101891
* config/i386/i386.cc (zero_call_used_regno_mode): use V2SImode
as a generic MMX mode instead of V4HImode.
(zero_all_mm_registers): Use SET to zero instead of MOV for
zeroing scratch registers.
(ix86_zero_call_used_regs): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-13.c: Add -msse.
* gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-16.c: Likewise.
* gcc.target/i386/zero-scratch-regs-17.c: Likewise.
* gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector
-fno-PIC, adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-20.c: Add -msse.
* gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector
-fno-PIC, Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-23.c: Likewise.
* gcc.target/i386/zero-scratch-regs-26.c: Likewise.
* gcc.target/i386/zero-scratch-regs-27.c: Likewise.
* gcc.target/i386/zero-scratch-regs-28.c: Likewise.
* gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector.
* gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector.
* gcc.target/i386/zero-scratch-regs-7.c: Likewise.
* gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector.
(cherry picked from commit 0b86943aca)
The patch that was so far added for documenting --with-zstd is pretty
minimal:
- it refers to undocumented options --with-zstd-include and
--with-zstd-lib;
- it suggests that --with-zstd can be used without an argument;
- it does not clarify how this option applies to cross-compilation.
How about adding the same details as for the --with-isl,
--with-isl-include, --with-isl-lib options, mutatis mutandis? This patch
does that.
PR other/105527
gcc/ChangeLog:
* doc/install.texi (Configuration): Add more details about --with-zstd.
Document --with-zstd-include and --with-zstd-lib
Signed-off-by: Bruno Haible <bruno@clisp.org>
(cherry picked from commit 3677eb80b6)
When optimizing the DGEMM kernel in OpenBLAS to use MMA, the MMA code
uses all 8 accumulators, which overlap all vs0-vs31 vector registers.
Current trunk assigns one of the normal vector inputs to one of the MMA
instructions, which forces us to spill one of the accumulators to memory,
leading to poor performance. The solution here is to replace the "wa"
constraints for the vector input operands in the MMA instruction patterns
with "v,?wa" so that we prefer using the altivec registers vs32-vs63
over the vs0-vs31 registers.
2022-05-17 Peter Bergner <bergner@linux.ibm.com>
Segher Boessenkool <segher@kernel.crashing.org>
gcc/
PR target/105556
* config/rs6000/mma.md (mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
mma_<vvi4i4i4>, mma_<avvi4i4i4>): Replace "wa" constraints with "v,?wa".
Update other operands accordingly.
(cherry picked from commit c6e36f05fb)
The testcase shows that we can end up with a contiguous access across
loop iterations but by means of permutations the elements accessed
might only cover parts of a vector. In this case we end up with
GROUP_GAP == 0 but still need to avoid accessing excess elements
in the last loop iterations. Peeling for gaps is designed to cover
this but a single scalar iteration might not cover all of the excess
elements. The following ensures peeling for gaps is done in this
situation and when that isn't sufficient because we need to peel
more than one iteration (gcc.dg/vect/pr103116-2.c), fail the SLP
vectorization.
2022-05-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/103116
* tree-vect-stmts.cc (get_group_load_store_type): Handle the
case we need peeling for gaps even though GROUP_GAP is zero.
* gcc.dg/vect/pr103116-1.c: New testcase.
* gcc.dg/vect/pr103116-2.c: Likewise.
(cherry picked from commit 52b7b86f8c)
The PR97330 fix caused some missed sinking of loads out of loops
the following patch re-instantiates.
2022-05-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/105618
* tree-ssa-sink.cc (statement_sink_location): For virtual
PHI uses ignore those defining the used virtual operand.
* gcc.dg/tree-ssa/ssa-sink-19.c: New testcase.
(cherry picked from commit ebce0e9bd8)
2022-05-16 Richard Biener <rguenther@suse.de>
PR rtl-optimization/105577
* g++.dg/torture/pr105577.C: New testcase.
(cherry picked from commit ef7b8976b9)
When one of the first two stages of DSE removes a throwing stmt
we have to purge dead EH edges before the DF re-analyze fires off
a fast DCE since that cannot cope with the situation.
2022-05-12 Richard Biener <rguenther@suse.de>
PR rtl-optimization/105577
* dse.cc (rest_of_handle_dse): Make sure to purge dead EH
edges before running fast DCE via df_analyze.
(cherry picked from commit dfda40f814)
We can avoid some uninit diagnostics by making FRE disambiguate
against CLOBBERs since any aliasing there would invoke undefined
behavior for a read we are looking up.
2022-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/105562
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Disambiguate
against all CLOBBER defs if there's not an obvious must-alias
and we are not doing redundant store elimination.
(vn_walk_cb_data::redundant_store_removal_p): New field.
(vn_reference_lookup_pieces): Initialize it.
(vn_reference_lookup): Add argument to specify if we are
doing redundant store removal.
(eliminate_dom_walker::eliminate_stmt): Specify we do.
* tree-ssa-sccvn.h (vn_reference_lookup): Adjust.
* g++.dg/warn/uninit-pr105562.C: New testcase.
(cherry picked from commit 94b8a37fa1)
When the insn to delete is a debug insn there's no point in figuring
out whether it might be the last real insn and thus we have to purge
dead edges.
2022-05-11 Richard Biener <rguenther@suse.de>
PR rtl-optimization/105559
* cfgrtl.cc (delete_insn_and_edges): Only perform search to BB_END
for non-debug insns.
(cherry picked from commit 37a8220fa9)
The following makes sure to have a consistent state of
flag_var_tracking_assignments with the distributed handling
in process_options and finish_options by moving everything to
finish_options which also restores diagnostics for
-g0 -fvar-tracking which was lost with previous changes.
2022-05-10 Richard Biener <rguenther@suse.de>
PR middle-end/105537
* toplev.cc (process_options): Move flag_var_tracking
handling ...
* opts.cc (finish_options): ... here.
* gcc.dg/torture/pr105537.c: New testcase.
(cherry picked from commit 76db543db8)
When code was moved from process_options to finish_options it
was not properly adjusted to look at and alter the opts set
passed to the function but continued to modify the global options
set. The following rectifies this and makes sure the same
mistake isn't repeated by poisoning global_options{,_set}.
2022-05-10 Richard Biener <rguenther@suse.de>
* flags.h (dwarf_debuginfo_p): Add opts argument, guard
API with !GENERATOR_FILE.
* opts.cc (global_options): Poison.
(global_options_set): Likewise.
(finish_options): Refer to options via opts.
(cherry picked from commit d469484610)
This avoids undefined signed overflow when calling powi_as_mults_1.
2022-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/105431
* tree-ssa-math-opts.cc (powi_as_mults_1): Make n unsigned.
(powi_as_mults): Use absu_hwi.
(gimple_expand_builtin_powi): Remove now pointless n != -n
check.
(cherry picked from commit 44b09adb9b)
The problem is that subtypes are not part of the limited view of a package
so we need to use types in conjunction with limited_with clauses, which is
not always desirable as this yields less portable Ada bindings. The patch
also contains a small enhancement for complex floating-point types.
gcc/c-family/
* c-ada-spec.cc (dump_ada_node) <COMPLEX_TYPE>: Deal with usual
floating-point complex types.
<POINTER_TYPE>: Do not use limited_with clause if the designated
type is a scalar type.
When registering a relation, we need to merge with any existing relation
before checking if it was an equivalence... otherwise it was not being
handled properly.
gcc/
PR tree-optimization/105458
* value-relation.cc (path_oracle::register_relation): Merge, then check
for equivalence.
gcc/testsuite/
* gcc.dg/pr105458.c: New.
OpenMP 5.2 added
"When called from within a target region the effect is unspecified."
restriction to omp_display_env, so it is ok not to support it in
target regions (worst case we could add an empty implementation
or one with __builtin_trap in there).
2022-05-17 Jakub Jelinek <jakub@redhat.com>
* libgomp.texi (OpenMP 5.1): Remove "Not inside target regions"
comment for omp_display_env feature.
(cherry picked from commit 741478ed3e)
These are the C++23 proposals supported in the gcc-12 branch.
libstdc++-v3/ChangeLog:
* doc/xml/manual/status_cxx2023.xml: Update with gcc-12 support.
* doc/html/*: Regenerate.
(cherry picked from commit 8414dad54a)
These are the C++23 proposals already supported in the gcc-11 branch.
libstdc++-v3/ChangeLog:
* doc/xml/manual/intro.xml: Include new chapter.
* doc/xml/manual/status_cxx2020.xml: Tweak release numbers.
* doc/xml/manual/status_cxx2023.xml: New file.
* doc/html/*: Regenerate.
(cherry picked from commit 4361867344)
libstdc++-v3/ChangeLog:
* doc/html/manual/status.html: Regenerate.
* doc/xml/manual/status_cxx2020.xml: Fix supported version for
C++20 bit operations.
(cherry picked from commit 64648821f1)
DW_OP_not is a bitwise, not a logical NOT, so it computes the wrong result
in a DWARF conditional expression.
gcc/
* dwarf2out.cc (loc_list_from_tree_1) <TRUTH_NOT_EXPR>: Do a logical
instead of a bitwise negation.
<COND_EXPR>: Swap the operands if the condition is TRUTH_NOT_EXPR.
D front-end changes:
- Import dmd v2.100.0.
Phobos changes:
- Import phobos v2.100.0.
gcc/d/ChangeLog:
* dmd/MERGE: Merge upstream dmd a53934d18.
* dmd/VERSION: Update version to v2.100.0.
* d-codegen.cc (d_decl_context): Use resolvedLinkage to get
declaration linkage.
(build_struct_literal): Track offset in bits.
* d-gimplify.cc (d_gimplify_modify_expr): Check both operands for a
bit-field reference.
* d-lang.cc (d_post_options): Set flag_rtti and flag_exceptions if
-fno-druntime was seen on command-line.
(d_type_promotes_to): Use resolvedLinkage to get declaration linkage.
* decl.cc (make_thunk): Likewise.
* types.cc (layout_aggregate_members): Ignore anonymous fields in
total count.
libphobos/ChangeLog:
* src/MERGE: Merge upstream phobos 604534d7c.
My patch for 105191 made us use build_value_init more frequently from
build_vec_init_expr, but build_value_init doesn't like to be called to
initialize a class in a template. That's caused trouble in the past, and
seems like a strange restriction, so let's fix it.
PR c++/105589
PR c++/105191
PR c++/92385
gcc/cp/ChangeLog:
* init.cc (build_value_init): Handle class in template.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-array16.C: New test.
In this testcase, we were trying to substitute into
variant<Foo<T>>::__accepted_type, but failed to look it up because
variant<Foo<T>> doesn't exist. In other cases we already rewrite such
things into a dependent reference; we need to do that for alias templates as
well.
This caused some testsuite regressions on alias uses outside of deduction
guides, so I've made all of this rewriting conditional on a new tf_dguide
tsubst flag.
PR c++/104470
gcc/cp/ChangeLog:
* cp-tree.h (enum tsubst_flags): Add tf_dguide.
* pt.cc (tsubst_aggr_type): Check it.
(tsubst_baselink, tsubst_copy): Check it.
(maybe_dependent_member_ref): Check it.
(instantiate_alias_template): Handle it.
(build_deduction_guide): Set it.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/explicit11.C: Second example also ill-formed.
* g++.dg/cpp2a/class-deduction-alias12.C: New test.
PR49387 was a problem with initially asking for a typeid for a class
template specialization before it was complete, and later actually filling
in the descriptor when the class was complete, and thus disagreeing on the
form of the descriptor. I fixed that by forcing the class to be complete,
but this testcase shows why that approach is problematic. So instead let's
adjust the type of the descriptor later if needed.
PR c++/102651
PR c++/49387
gcc/cp/ChangeLog:
* rtti.cc (get_tinfo_decl_direct): Don't complete_type.
(emit_tinfo_decl): Update tdesc type if needed.
gcc/testsuite/ChangeLog:
* g++.dg/rtti/typeid-complete1.C: New test.
gcov_info::n_functions type is initialized by generated
code in build_info_type:
/* n_functions */
field = build_decl (BUILTINS_LOCATION, FIELD_DECL, NULL_TREE,
get_gcov_unsigned_t ());
It uses gcov_unsigned_t, but the struct definition in libgcov.h uses
unsigned type. That brings troubled on 16-bit targets.
PR gcov-profile/105535
libgcc/ChangeLog:
* libgcov.h (struct gcov_info): Use gcov_unsigned_t for
n_functions.
Co-Authored-By: Hans-Peter Helfert <peter-helfert@t-online.de>
(cherry picked from commit eaf359ed04e7169f740dade548965c757f4c1e0a)
Most cases of VIEW_CONVERT_EXPRs involving reverse scalar storage order are
disqualified for SRA because they are storage_order_barrier_p, but you can
still have a VIEW_CONVERT_EXPR to a regular composite type being applied to
a component of a record type with reverse scalar storage order.
In this case the bypass for !useless_type_conversion_p in sra_modify_assign,
albeit already heavily guarded, triggers and may generate wrong code, so the
patch makes sure that it does only when the SSO is the same on both side.
gcc/
* tree-sra.cc (sra_modify_assign): Check that scalar storage order
is the same on the LHS and RHS before rewriting one with the model
of the other.
gcc/testsuite/
* gnat.dg/sso17.adb: New test.
When turning unconditional edges into conditional, as in
gimple-harden-conditionals.cc:insert_check_and_trap, the newly-created
edge's probability comes out uninitialized, while the previously
unconditional edge's probability is presumably
profile_probability::always.
Mixing initialized and uninitialized probabilities before expand
breaks predict.cc:force_edge_cold: the initialized probability may end
up copied to a REG_BR_PROB note in a conditional branch insn, but if
force_edge_cold is called on that edge, it will find another edge with
uninitialized probability and assume the note is absent. Later on,
rtl_verify_edges complains that the note does not match the
probability modified by force_edge_cold in the edge.
This patch sets probabilities for edges affected by hardening of
conditionals, both the newly-created edges to trap blocks and the
previously-unconditional edges, so that the former are considered
never taken, while the latter are confirmed as always taken.
for gcc/ChangeLog
PR rtl-optimization/105455
* gimple-harden-conditionals.cc (insert_check_and_trap): Set
probabilities for newly-conditional edges.
for gcc/testsuite/ChangeLog
PR rtl-optimization/105455
* gcc.dg/pr105455.c: New.
(cherry picked from commit 90a8eab4a1)
libstdc++'s bits/simd.h section for PowerPC, guarded by __ALTIVEC__,
defines various intrinsic vector types that are only available with
__VSX__: 64-bit long double, double, (un)signed long long, and 64-bit
(un)signed long.
experimental/simd/standard_abi_usable{,_2}.cc tests error out
reporting the unmet requirements when the target cpu doesn't enable
VSX. Make the reported instrinsic types conditional on __VSX__ so
that <experimental/simd> can be used on PowerPC variants that do not
support VSX.
for libstdc++-v3/ChangeLog
* include/experimental/bits/simd.h [__ALTIVEC__]: Require VSX
for double, long long, and 64-bit long intrinsic types.
[__ALTIVEC__] (__intrinsic_type): Mention 128-bit in
preexisting long double diagnostic, adjust no-VSX double
diagnostic to cover 64-bit long double as well.
(cherry picked from commit 469c76f0d9)
GCC Administrator
Simon Cook
Kito Cheng
Qing Zhao
Bruno Haible
Martin Liska
Peter Bergner
Richard Biener
Eric Botcazou
Andrew MacLeod
Jakub Jelinek
Sebastian Pop
Jonathan Wakely
Iain Buclaw
Jason Merrill
Harald Anlauf
Alexandre Oliva