We use a negative ID number to link together the doloop_begin and
doloop_end instructions. This negative ID number is setup within
doloop_begin, at this point the ID is stored into the loop end
instruction (doloop_end_i) and placed into the doloop_begin_i
instruction.
In arc.c (arc_reorg) we extract the ID from the doloop_end_i
instruction in order to find the matching doloop_begin_i instruction,
though the ID is only used in some cases.
Currently in arc_reorg when we extract the ID we negate it. This
negation is invalid. The ID stored in both doloop_end_i and
doloop_begin_i is already negative, the negation in arc_reorg means
that if we need to use the ID to find the doloop_begin_i then we will
never find it (as the IDs will never match).
This commit removes the unneeded negation, moves the extraction of the
ID into a more appropriately scoped block and adds a new test for this
issue.
gcc/ChangeLog:
* config/arc/arc.c (arc_reorg): Move loop_end_id into a more local
block, and do not negate it, the stored id is already negative.
gcc/testsuite/ChangeLog:
* gcc.target/arc/loop-1.c: New file.
Co-Authored-By: Guy Benyei <guybe@mellanox.com>
From-SVN: r246933
The old ARC assembler would accept expressions like 'LABEL-(.&-4)'
which would calculate the offset from the PCL to LABEL. The new ARC
assembler does not accept these expressions, instead there's an @pcl
synax, used like LABEL@pcl which gives the offset from PCL to LABEL.
Most of the use of the old expression syntax have been removed,
however, this one got missed.
gcc/ChangeLog:
* config/arc/arc.md (doloop_begin_i): Use @pcl assembler syntax.
From-SVN: r246932
[gcc]
2017-04-14 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80098
* config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS): Define
masks of options that should be turned off if the VSX vector
options are turned off.
(OTHER_P8_VECTOR_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Call
rs6000_disable_incompatible_switches to validate no type switches
like -mvsx.
(rs6000_incompatible_switch): New function to disallow turning on
other vector options if -mno-vsx, -mno-power8-vector, or
-mno-power9-vector are specified.
[gcc/testsuite]
2017-04-14 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80098
* gcc.target/powerpc/pr80098-1.c: New test.
* gcc.target/powerpc/pr80098-2.c: Likewise.
* gcc.target/powerpc/pr80098-3.c: Likewise.
* gcc.target/powerpc/pr80098-4.c: Likewise.
From-SVN: r246930
Update arc_mode_dependent_address_p to avoid emitting subreg(mem (reg
..)) when expanding by relaxing the conditions.
gcc/
2017-04-14 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_mode_dependent_address_p): Relax
conditions to take advantage of various optimizations.
From-SVN: r246925
* config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear
in operands[1] if it is a MEM and TARGET_MIPS16 is active.
(zero_extendsidi2_dext): Likewise.
From-SVN: r246924
PR sanitizer/80403
* fold-const.c (fold_ternary_loc): Revert
use op0 instead of fold_convert_loc (loc, type, arg0) part of
2017-04-12 change.
* g++.dg/ubsan/pr80403-2.C: New test.
From-SVN: r246917
2017-04-13 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/80343
* lra-remat.c (update_scratch_ops): Assign original hard reg to
new scratch pseudo.
2017-04-13 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/80343
* gcc.target/powerpc/pr80343.c: New.
From-SVN: r246914
PR sanitizer/80414
* ubsan.c (ubsan_expand_bounds_ifn): Pass original index
to ubsan_encode_value.
* c-c++-common/ubsan/bounds-15.c: New test.
From-SVN: r246909
2017-04-13 Martin Liska <mliska@suse.cz>
PR gcov-profile/80413
* gcov-io.c (gcov_write_string): Copy to buffer just when
allocated size is greater than zero.
From-SVN: r246903
PR debug/80321
* dwarf2out.c (decls_for_scope): Ignore declarations of
current_function_decl in BLOCK_NONLOCALIZED_VARS.
* gcc.dg/debug/pr80321.c: New test.
2017-04-13 Eric Botcazou <ebotcazou@adacore.com>
* gnat.dg/debug10.adb: New test.
* gnat.dg/debug10_pkg.ads: New helper.
From-SVN: r246900
PR lto/69953
* ipa-visibility.c (non_local_p): Fix typos.
(localize_node): When localizing symbol in same comdat group,
dissolve the group only when we know external symbols are going
to be privatized.
(function_and_variable_visibility): Do not localize DECL_EXTERNAL.
From-SVN: r246899
PR tree-optimization/79390
* optabs.c (emit_conditional_move): If the preferred op2/op3 operand
order does not result in usable sequence, retry with reversed operand
order.
* gcc.target/i386/pr70465-2.c: Xfail the scan-assembler-not test.
From-SVN: r246882
PR sanitizer/80403
PR sanitizer/80404
PR sanitizer/80405
* fold-const.c (fold_ternary_loc): Use op1 instead of arg1 as argument
to fold_build2_loc. Convert TREE_OPERAND (tem, 0) to type. Use
op0 instead of fold_convert_loc (loc, type, arg0).
* g++.dg/ubsan/pr80403.C: New test.
* g++.dg/ubsan/pr80404.C: New test.
* g++.dg/ubsan/pr80405.C: New test.
From-SVN: r246881
PR c/80163
* expr.c <CASE_CONVERT>: For EXPAND_INITIALIZER determine SIGN_EXTEND
vs. ZERO_EXTEND based on signedness of treeop0's type rather than
signedness of the result type.
* gcc.dg/torture/pr80163.c: New test.
From-SVN: r246876
2017-04-12 Richard Biener <rguenther@suse.de>
Jeff Law <law@redhat.com>
PR tree-optimization/80359
* tree-ssa-dse.c (maybe_trim_partially_dead_store): Do not
trim stores to TARGET_MEM_REFs.
* gcc.dg/torture/pr80359.c: New testcase.
Co-Authored-By: Jeff Law <law@redhat.com>
From-SVN: r246875
2017-04-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/79390
* gimple-ssa-split-paths.c (is_feasible_trace): Restrict
threading case even more.
From-SVN: r246869
Whatever expand expands to should be valid instructions. The defined
instructions here have a quad_memory_operand predicate, which boils
down to quad_address_p on the address, so let's test for that instead
of only disallowing indexed addresses.
* config/rs6000/sync.md (atomic_load<mode>, atomic_store<mode): Test
for quad_address_p for TImode, instead of just not indexed_address.
From-SVN: r246868
Whatever expand expands to should be valid instructions. The defined
instructions here have a quad_memory_operand predicate, which boils
down to quad_address_p on the address, so let's test for that instead
of only disallowing indexed addresses.
* config/rs6000/sync.md (atomic_load<mode>, atomic_store<mode): Test
for quad_address_p for TImode, instead of just not indexed_address.
From-SVN: r246867
PR go/77857
cmd/go: generate vendor paths for -I arg on compile
This change generates the vendor path to be used with -I
on a gccgo compile to find imports from the vendor directories.
Fixesgolang/go#15628
Reviewed-on: https://go-review.googlesource.com/39590
From-SVN: r246864
2017-04-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/80376
PR target/80315
* config/rs6000/rs6000.c (rs6000_expand_unop_builtin): Return
CONST0_RTX (mode) rather than const0_rtx where appropriate.
(rs6000_expand_binop_builtin): Likewise.
(rs6000_expand_ternop_builtin): Likewise; also add missing
vsx_xxpermdi_* variants; also fix typo (arg1 => arg2) for
vshasigma built-ins.
* doc/extend.texi: Document that vec_xxpermdi's third argument
must be a constant.
From-SVN: r246859
* constexpr.c (reduced_constant_expression_p):
A null constructor element is non-constant.
(cxx_eval_indirect_ref): Don't VERIFY_CONSTANT before
returning an empty base.
From-SVN: r246858
PR c++/80370
* decl.c (cp_finish_decomp): If processing_template_decl on
non-dependent decl, only set TREE_TYPE on the v[i] decls, but don't
change their DECL_VALUE_EXPR nor cp_finish_decl them. Instead make
sure DECL_VALUE_EXPR is the canonical NULL type ARRAY_REF for tsubst
processing.
* pt.c (value_dependent_expression_p) <case VAR_DECL>: For variables
with DECL_VALUE_EXPR, return true if DECL_VALUE_EXPR is type
dependent.
* g++.dg/cpp1z/decomp28.C: New test.
From-SVN: r246857
* config/i386/i386.c (dimode_scalar_chain::compute_convert_gain):
Use shift_const cost parameter when calculating gain of STV shifts.
From-SVN: r246856
PR rtl-optimization/80385
* simplify-rtx.c (simplify_unary_operation_1): Don't transform
(not (neg X)) into (plus X -1) for complex or non-integral modes.
* g++.dg/opt/pr80385.C: New test.
From-SVN: r246850
PR libgomp/80394
* omp-low.c (scan_omp_task): Don't optimize away empty tasks
if they have any depend clauses.
* testsuite/libgomp.c/pr80394.c: New test.
From-SVN: r246849
2017-04-11 Martin Liska <mliska@suse.cz>
PR ipa/80212
* cgraph.c (cgraph_node::dump): Dump calls_comdat_local.
* ipa-split.c (split_function): Create a local comdat symbol
if caller is in a comdat group.
2017-04-11 Martin Liska <mliska@suse.cz>
PR ipa/80212
* g++.dg/ipa/pr80212.C: New test.
From-SVN: r246848
gcc/ChangeLog:
PR middle-end/80364
* gimple-ssa-sprintf.c (get_int_range): Remove second argument and
always use the int type. Use INTEGRAL_TYPE_P() rather than testing
for INTEGER_TYPE.
(directive::set_width, directive::set_precision, format_character):
Adjust.
(parse_directive): Use INTEGRAL_TYPE_P() rather than testing for
INTEGER_TYPE.
gcc/testsuite/ChangeLog:
PR middle-end/80364
* gcc.dg/tree-ssa/builtin-sprintf-warn-16.c: New test.
From-SVN: r246846
2017-04-11 Damian Rouson <damian@sourceryinstitute.org>
* download_prerequisites (md5_check): New function emulates Linux
'md5 --check' on macOS. Modified script for macOS compatibility.
From-SVN: r246845
In this PR we incorrectly print the architecture name in a .cpu
directive in the assembly file when the -mcpu and -march options
conflict (don't target the same base architecture). In this case the
.arch overrides the .cpu directive and we should emit a .arch option.
PR target/80389
* config/arm/arm.c (arm_configure_build_target): When -mcpu and -arch conflict,
set target->arch_name instead of target->cpu_name.
From-SVN: r246843
