76f09260b7
175564 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Andre Simoes Dias Vieira
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719c864225 |
gcc, Arm: Revert changes to {get,set}_fpscr
MVE made changes to {get,set}_fpscr to enable the compiler to optimize
unneccesary gets and sets when using these for intrinsics that use and/or write
the carry bit. However, these actually get and set the full FPSCR register and
are used by fp env intrinsics to modify the fp context. So MVE should not be
using these.
gcc/ChangeLog:
2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
(VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
* config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
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Andre Simoes Dias Vieira
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005f6fc59e |
gcc, Arm: Fix testisms for MVE testsuite
This patch fixes some testism where -mfpu=auto was missing or where we could end up with -mfloat-abi=hard and soft on the same command-line. gcc/testsuite/ChangeLog: 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms. * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. |
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Andre Simoes Dias Vieira
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0efe7d8796 |
gcc, Arm: Fix MVE move from GPR -> GPR
This patch fixes the pattern mve_mov for the case where both MVE vectors are in R registers and the move does not get optimized away. I use the same approach as we do for NEON, where we use four register moves. gcc/ChangeLog: 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/mve.md (mve_mov<mode>): Fix R->R case. gcc/testsuite/ChangeLog: 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test. |
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Jakub Jelinek
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4119cd693d |
store-merging: Fix up -fnon-call-exceptions handling [PR94224]
When we are adding a single store into a store group, we are already checking that store->lp_nr matches, but we have also code to add further INTEGER_CST stores into the group right away if the ordering requires that either we put there all or none from a certain set of stores. And in those cases we weren't doing these lp_nr checks, which means we could end up with stores with different lp_nr in the same group, which then ICEs during output_merged_store. 2020-03-20 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/94224 * gimple-ssa-store-merging.c (imm_store_chain_info::coalesce_immediate): Don't consider overlapping or adjacent INTEGER_CST rhs_code stores as mergeable if they have different lp_nr. * g++.dg/tree-ssa/pr94224.C: New test. |
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Andre Simoes Dias Vieira
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05009698ee |
gcc, Arm: Fix no_cond issue introduced by MVE
This was a matter of mistaken logic in (define_attr "conds" ..). This was setting the conds attribute for any neon instruction to no_cond which was messing up code generation. gcc/ChangeLog: 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. |
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Bin Bin Lv
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4a18f168f4 |
[rs6000] Rewrite the declaration of a variable
Rewrite the declaration of toc_section from the source file rs6000.c to its header file for standardizing the code. Bootstrap and regression were done on powerpc64le-linux-gnu (LE) with no regressions. gcc/ChangeLog 2020-03-20 Bin Bin Lv <shlb.linux.ibm.com> * config/rs6000/rs6000-internal.h (toc_section): Remove the declaration. * config/rs6000/rs6000.h (toc_section): Add the declaration. * config/rs6000/rs6000.c (toc_section): Remove the declaration. |
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Jason Merrill
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94e2418780 |
c++: Avoid unnecessary empty class copy [94175].
A simple empty class copy is still simple when wrapped in a TARGET_EXPR, so we need to strip that as well. This change also exposed some unnecessary copies in return statements, which when returning by invisible reference led to <RETURN_EXPR <MEM_REF <RESULT_DECL>>>, which gimplify_return_expr didn't like. So we also need to strip the _REF when we eliminate the INIT_EXPR. gcc/cp/ChangeLog 2020-03-19 Jason Merrill <jason@redhat.com> PR c++/94175 * cp-gimplify.c (simple_empty_class_p): Look through SIMPLE_TARGET_EXPR_P. (cp_gimplify_expr) [MODIFY_EXPR]: Likewise. [RETURN_EXPR]: Avoid producing 'return *retval;'. * call.c (build_call_a): Strip TARGET_EXPR from empty class arg. * cp-tree.h (SIMPLE_TARGET_EXPR_P): Check that TARGET_EXPR_INITIAL is non-null. |
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GCC Administrator
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3373d3e38e | Daily bump. | ||
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Jan Hubicka
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f7dceb4e65 |
Fix cgraph_node::function_symbol availability compuattion [PR94202]
this fixes ICE in inliner cache sanity check which is caused by very old bug in visibility calculation in cgraph_node::function_symbol and cgraph_node::function_or_virtual_thunk_symbol. In the testcase there is indirect call to a thunk. At begining we correctly see that its body as AVAIL_AVAILABLE but later we inline into the thunk and this turns it to AVAIL_INTERPOSABLE. This is because function_symbol incorrectly overwrites availability parameter by availability of the alias used in the call within thunk, which is a local alias. gcc/ChangeLog: 2020-03-19 Jan Hubicka <hubicka@ucw.cz> PR ipa/94202 * cgraph.c (cgraph_node::function_symbol): Fix availability computation. (cgraph_node::function_or_virtual_thunk_symbol): Likewise. gcc/testsuite/ChangeLog: 2020-03-19 Jan Hubicka <hubicka@ucw.cz> PR ipa/94202 * g++.dg/torture/pr94202.C: New test. |
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Jakub Jelinek
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9def91e9f2 |
c: Fix up cfun->function_end_locus from the C FE [PR94029]
On the following testcase we ICE because while
DECL_STRUCT_FUNCTION (current_function_decl)->function_start_locus
= c_parser_peek_token (parser)->location;
and similarly DECL_SOURCE_LOCATION (fndecl) is set from some token's
location, the end is set as:
/* Store the end of the function, so that we get good line number
info for the epilogue. */
cfun->function_end_locus = input_location;
and the thing is that input_location is only very rarely set in the C FE
(the primary spot that changes it is the cb_line_change/fe_file_change).
Which means, e.g. for pretty much all C functions that are on a single line,
function_start_locus column is > than function_end_locus column, and the
testcase even has smaller line in function_end_locus because cb_line_change
isn't performed while parsing multi-line arguments of a function-like macro.
Attached are two possible fixes to achieve what the C++ FE does, in
particular that cfun->function_end_locus is the locus of the closing } of
the function. The first one updates input_location when we see a closing }
of a compound statement (though any, not just the function body) and thus
input_location in the finish_function call is what we need.
The second instead propagates the location_t from the parsing of the
outermost compound statement (the function body) to finish_function.
The second one is this version.
2020-03-19 Jakub Jelinek <jakub@redhat.com>
PR gcov-profile/94029
* c-tree.h (finish_function): Add location_t argument defaulted to
input_location.
* c-parser.c (c_parser_compound_statement): Add endlocp argument and
set it to the locus of closing } if non-NULL.
(c_parser_compound_statement_nostart): Return locus of closing }.
(c_parser_parse_rtl_body): Likewise.
(c_parser_declaration_or_fndef): Propagate locus of closing } to
finish_function.
* c-decl.c (finish_function): Add end_loc argument, use it instead of
input_location to set function_end_locus.
* gcc.misc-tests/gcov-pr94029.c: New test.
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Iain Buclaw
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37482edc3f |
d/dmd: Merge upstream dmd d1a606599
Fixes long standing regression in the D front-end implemention, and adds a new field to allow retrieving a list of all content imports from the code generator. Reviewed-on: https://github.com/dlang/dmd/pull/10913 https://github.com/dlang/dmd/pull/10933 |
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Jan Hubicka
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f22712bd8a |
Fix inliner ICE on alias with flatten attribute [PR92372]
gcc/ChangeLog: 2020-03-19 Jan Hubicka <hubicka@ucw.cz> PR ipa/92372 * cgraphunit.c (process_function_and_variable_attributes): warn for flatten attribute on alias. * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. gcc/testsuite/ChangeLog: 2020-03-19 Jan Hubicka <hubicka@ucw.cz> PR ipa/92372 * gcc.c-torture/pr92372.c: New test. * gcc.dg/attr-flatten-1.c: New test. |
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Martin Liska
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c8429c2aba
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API extension for binutils (type of symbols).
* lto-section-in.c: Add ext_symtab. * lto-streamer-out.c (write_symbol_extension_info): New. (produce_symtab_extension): New. (produce_asm_for_decls): Stream also produce_symtab_extension. * lto-streamer.h (enum lto_section_type): New section. * lto-symtab.h (enum gcc_plugin_symbol_type): New. (enum gcc_plugin_symbol_section_kind): Likewise. * lto-plugin.c (LTO_SECTION_PREFIX): Rename to ... (LTO_SYMTAB_PREFIX): ... this. (LTO_SECTION_PREFIX_LEN): Rename to ... (LTO_SYMTAB_PREFIX_LEN): ... this. (LTO_SYMTAB_EXT_PREFIX): New. (LTO_SYMTAB_EXT_PREFIX_LEN): New. (LTO_LTO_PREFIX): New. (LTO_LTO_PREFIX_LEN): New. (parse_table_entry): Fill up unused to zero. (parse_table_entry_extension): New. (parse_symtab_extension): New. (finish_conflict_resolution): Change type for resolution. (process_symtab): Use new macro name. (process_symtab_extension): New. (claim_file_handler): Parse also process_symtab_extension. (onload): Call new add_symbols_v2. |
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Martin Liska
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f5389e17e4
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Update include/plugin-api.h.
* plugin-api.h (struct ld_plugin_symbol): Split int def into 4 char fields. (enum ld_plugin_symbol_type): New. (enum ld_plugin_symbol_section_kind): New. (enum ld_plugin_tag): Add LDPT_ADD_SYMBOLS_V2. |
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Jakub Jelinek
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02f7334ac9 |
c++: Fix up handling of captured vars in lambdas in OpenMP clauses [PR93931]
Without the parser.c change we were ICEing on the testcase, because while the uses of the captured vars inside of the constructs were replaced with capture proxy decls, we didn't do that for decls in OpenMP clauses. With that fixed, we don't ICE anymore, but the testcase is miscompiled and FAILs at runtime. This is because the capture proxy decls have DECL_VALUE_EXPR and during gimplification we were gimplifying those to their DECL_VALUE_EXPRs. That is fine for shared vars, but for privatized ones we must not do that. So that is what the cp-gimplify.c changes do. Had to add a DECL_CONTEXT check before calling is_capture_proxy because some VAR_DECLs don't have DECL_CONTEXT set (yet) and is_capture_proxy relies on that being non-NULL always. 2020-03-19 Jakub Jelinek <jakub@redhat.com> PR c++/93931 * parser.c (cp_parser_omp_var_list_no_open): Call process_outer_var_ref on outer_automatic_var_p decls. * cp-gimplify.c (cxx_omp_disregard_value_expr): Return true also for capture proxy decls. * testsuite/libgomp.c++/pr93931.C: New test. |
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Tobias Burnus
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bb83e069eb |
libgomp/testsuite: ignore blank-line output for function-not-offloaded.c
* testsuite/libgomp.c-c++-common/function-not-offloaded.c: Add dg-allow-blank-lines-in-output. |
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Jakub Jelinek
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c7e9019681 |
phiopt: Avoid -fcompare-debug bug in phiopt [PR94211]
Two years ago, I've added support for up to 2 simple preparation statements in value_replacement, but the - && estimate_num_insns (assign, &eni_time_weights) + && estimate_num_insns (bb_seq (middle_bb), &eni_time_weights) change, meant that we compute the cost of all those statements rather than just the single assign that has been the single supported non-debug statement in the bb before, doesn't do what I thought would do, gimple_seq is just gimple * and thus it can't be really overloaded depending on whether we pass a single gimple * or a whole sequence. Which means in the last two years it doesn't count all the statements, but only the first one. With -g that happens to be a DEBUG_STMT, or it could be e.g. the first preparation statement which could be much cheaper than the actual assign. 2020-03-19 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/94211 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq instead of estimate_num_insns for bb_seq (middle_bb). Rename emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust all uses. * gcc.dg/pr94211.c: New test. |
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Richard Biener
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f3280e4c0c |
ipa/94217 simplify offsetted address build
This avoids using build_ref_for_offset and build_fold_addr_expr where type mixup easily results in something not IP invariant. 2020-03-19 Richard Biener <rguenther@suse.de> PR ipa/94217 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr and build_ref_for_offset. |
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Richard Biener
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73bc09fa8c |
middle-end/94216 fix another build_fold_addr_expr use
2020-03-19 Richard Biener <rguenther@suse.de> PR middle-end/94216 * fold-const.c (fold_binary_loc): Avoid using build_fold_addr_expr when we really want an ADDR_EXPR. * g++.dg/torture/pr94216.C: New testcase. |
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GCC Administrator
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b5562f1187 | Daily bump. | ||
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Jonathan Wakely
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b334182653 |
libstdc++: Fix is_trivially_constructible (PR 94033)
This attempts to make is_nothrow_constructible more robust (and efficient to compile) by not depending on is_constructible. Instead the __is_constructible intrinsic is used directly. The helper class __is_nt_constructible_impl which checks whether the construction is non-throwing now takes a bool template parameter that is substituted by the result of the instrinsic. This fixes the reported bug by not using the already-instantiated (and incorrect) value of std::is_constructible. I don't think it really fixes the problem in general, because std::is_nothrow_constructible itself could already have been instantiated in a context where it gives the wrong result. A proper fix needs to be done in the compiler. PR libstdc++/94033 * include/std/type_traits (__is_nt_default_constructible_atom): Remove. (__is_nt_default_constructible_impl): Remove. (__is_nothrow_default_constructible_impl): Remove. (__is_nt_constructible_impl): Add bool template parameter. Adjust partial specializations. (__is_nothrow_constructible_impl): Replace class template with alias template. (is_nothrow_default_constructible): Derive from alias template __is_nothrow_constructible_impl instead of __is_nothrow_default_constructible_impl. * testsuite/20_util/is_nothrow_constructible/94003.cc: New test. |
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Segher Boessenkool
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07fe4af4d5 |
rs6000: Add back some w* constraints (PR91886)
In May and June last year I deleted many of our (vector) constraints. We can now just use "wa" for those, together with some other conditions, which can be per alternative using the "enabled" attribute (which in turn primarily uses the "isa" attribute). But, it turns out that Clang implements some of those constraints as well, and at least musl uses some of them. It is easy for us to add those contraints back (as undocumented aliases to "wa", which always did mean the same thing for valid inline assembler code), so do that. gcc/ * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented aliases for "wa". |
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Jeff Law
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529ea7d959 |
Complete change to resolve pr90275.
PR rtl-optimization/90275 * cse.c (cse_insn): Delete no-op register moves too. |
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Martin Sebor
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3512dc0108 |
PR ipa/92799 - ICE on a weakref function definition followed by a declaration
gcc/testsuite/ChangeLog: PR ipa/92799 * gcc.dg/attr-weakref-5.c: New test. gcc/ChangeLog: PR ipa/92799 * cgraphunit.c (process_function_and_variable_attributes): Also complain about weakref function definitions and drop all effects of the attribute. |
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Srinath Parvathaneni
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7a5fffa5ed |
[ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, word and double word to memory.
This patch supports the following MVE ACLE store intrinsics which stores an halfword, word or double word to memory. vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64, vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64, vstrdq_scatter_shifted_offset_u64, vstrhq_scatter_offset_f16, vstrhq_scatter_offset_p_f16, vstrhq_scatter_shifted_offset_f16, vstrhq_scatter_shifted_offset_p_f16, vstrwq_scatter_base_f32, vstrwq_scatter_base_p_f32, vstrwq_scatter_offset_f32, vstrwq_scatter_offset_p_f32, vstrwq_scatter_offset_p_s32, vstrwq_scatter_offset_p_u32, vstrwq_scatter_offset_s32, vstrwq_scatter_offset_u32, vstrwq_scatter_shifted_offset_f32, vstrwq_scatter_shifted_offset_p_f32, vstrwq_scatter_shifted_offset_p_s32, vstrwq_scatter_shifted_offset_p_u32, vstrwq_scatter_shifted_offset_s32, vstrwq_scatter_shifted_offset_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch a new predicate "Ri" is defined to check the immediate is in the range of +/-1016 and multiple of 8. 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. (vstrdq_scatter_base_p_u64): Likewise. (vstrdq_scatter_base_s64): Likewise. (vstrdq_scatter_base_u64): Likewise. (vstrdq_scatter_offset_p_s64): Likewise. (vstrdq_scatter_offset_p_u64): Likewise. (vstrdq_scatter_offset_s64): Likewise. (vstrdq_scatter_offset_u64): Likewise. (vstrdq_scatter_shifted_offset_p_s64): Likewise. (vstrdq_scatter_shifted_offset_p_u64): Likewise. (vstrdq_scatter_shifted_offset_s64): Likewise. (vstrdq_scatter_shifted_offset_u64): Likewise. (vstrhq_scatter_offset_f16): Likewise. (vstrhq_scatter_offset_p_f16): Likewise. (vstrhq_scatter_shifted_offset_f16): Likewise. (vstrhq_scatter_shifted_offset_p_f16): Likewise. (vstrwq_scatter_base_f32): Likewise. (vstrwq_scatter_base_p_f32): Likewise. (vstrwq_scatter_offset_f32): Likewise. (vstrwq_scatter_offset_p_f32): Likewise. (vstrwq_scatter_offset_p_s32): Likewise. (vstrwq_scatter_offset_p_u32): Likewise. (vstrwq_scatter_offset_s32): Likewise. (vstrwq_scatter_offset_u32): Likewise. (vstrwq_scatter_shifted_offset_f32): Likewise. (vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrwq_scatter_shifted_offset_p_s32): Likewise. (vstrwq_scatter_shifted_offset_p_u32): Likewise. (vstrwq_scatter_shifted_offset_s32): Likewise. (vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. (__arm_vstrdq_scatter_base_p_u64): Likewise. (__arm_vstrdq_scatter_base_s64): Likewise. (__arm_vstrdq_scatter_base_u64): Likewise. (__arm_vstrdq_scatter_offset_p_s64): Likewise. (__arm_vstrdq_scatter_offset_p_u64): Likewise. (__arm_vstrdq_scatter_offset_s64): Likewise. (__arm_vstrdq_scatter_offset_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. (__arm_vstrwq_scatter_offset_p_s32): Likewise. (__arm_vstrwq_scatter_offset_p_u32): Likewise. (__arm_vstrwq_scatter_offset_s32): Likewise. (__arm_vstrwq_scatter_offset_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_f16): Likewise. (__arm_vstrhq_scatter_offset_p_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. (__arm_vstrwq_scatter_base_f32): Likewise. (__arm_vstrwq_scatter_base_p_f32): Likewise. (__arm_vstrwq_scatter_offset_f32): Likewise. (__arm_vstrwq_scatter_offset_p_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrhq_scatter_offset): Define polymorphic variant. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrwq_scatter_base): Likewise. (vstrwq_scatter_base_p): Likewise. (vstrwq_scatter_offset): Likewise. (vstrwq_scatter_offset_p): Likewise. (vstrwq_scatter_shifted_offset): Likewise. (vstrwq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_base_p): Likewise. (vstrdq_scatter_base): Likewise. (vstrdq_scatter_offset_p): Likewise. (vstrdq_scatter_offset): Likewise. (vstrdq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_shifted_offset): Likewise. * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. (STRSBS_P): Likewise. (STRSBU): Likewise. (STRSBU_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. * config/arm/constraints.md (Ri): Define. * config/arm/mve.md (VSTRDSBQ): Define iterator. (VSTRDSOQ): Likewise. (VSTRDSSOQ): Likewise. (VSTRWSOQ): Likewise. (VSTRWSSOQ): Likewise. (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern. (mve_vstrdq_scatter_base_<supf>v2di): Likewise. (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise. (mve_vstrdq_scatter_offset_<supf>v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise. (mve_vstrhq_scatter_offset_fv8hf): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. (mve_vstrwq_scatter_base_fv4sf): Likewise. (mve_vstrwq_scatter_base_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise. (mve_vstrwq_scatter_offset_<supf>v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise. * config/arm/predicates.md (Ri): Define predicate to check immediate is the range +/-1016 and multiple of 8. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c: New test. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. |
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Srinath Parvathaneni
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5cad47e0f8 |
[ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to memory.
This patch supports the following MVE ACLE store intrinsics which stores a byte, halfword, or word to memory. vst1q_f32, vst1q_f16, vst1q_s8, vst1q_s32, vst1q_s16, vst1q_u8, vst1q_u32, vst1q_u16, vstrhq_f16, vstrhq_scatter_offset_s32, vstrhq_scatter_offset_s16, vstrhq_scatter_offset_u32, vstrhq_scatter_offset_u16, vstrhq_scatter_offset_p_s32, vstrhq_scatter_offset_p_s16, vstrhq_scatter_offset_p_u32, vstrhq_scatter_offset_p_u16, vstrhq_scatter_shifted_offset_s32, vstrhq_scatter_shifted_offset_s16, vstrhq_scatter_shifted_offset_u32, vstrhq_scatter_shifted_offset_u16, vstrhq_scatter_shifted_offset_p_s32, vstrhq_scatter_shifted_offset_p_s16, vstrhq_scatter_shifted_offset_p_u32, vstrhq_scatter_shifted_offset_p_u16, vstrhq_s32, vstrhq_s16, vstrhq_u32, vstrhq_u16, vstrhq_p_f16, vstrhq_p_s32, vstrhq_p_s16, vstrhq_p_u32, vstrhq_p_u16, vstrwq_f32, vstrwq_s32, vstrwq_u32, vstrwq_p_f32, vstrwq_p_s32, vstrwq_p_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vst1q_f32): Define macro. (vst1q_f16): Likewise. (vst1q_s8): Likewise. (vst1q_s32): Likewise. (vst1q_s16): Likewise. (vst1q_u8): Likewise. (vst1q_u32): Likewise. (vst1q_u16): Likewise. (vstrhq_f16): Likewise. (vstrhq_scatter_offset_s32): Likewise. (vstrhq_scatter_offset_s16): Likewise. (vstrhq_scatter_offset_u32): Likewise. (vstrhq_scatter_offset_u16): Likewise. (vstrhq_scatter_offset_p_s32): Likewise. (vstrhq_scatter_offset_p_s16): Likewise. (vstrhq_scatter_offset_p_u32): Likewise. (vstrhq_scatter_offset_p_u16): Likewise. (vstrhq_scatter_shifted_offset_s32): Likewise. (vstrhq_scatter_shifted_offset_s16): Likewise. (vstrhq_scatter_shifted_offset_u32): Likewise. (vstrhq_scatter_shifted_offset_u16): Likewise. (vstrhq_scatter_shifted_offset_p_s32): Likewise. (vstrhq_scatter_shifted_offset_p_s16): Likewise. (vstrhq_scatter_shifted_offset_p_u32): Likewise. (vstrhq_scatter_shifted_offset_p_u16): Likewise. (vstrhq_s32): Likewise. (vstrhq_s16): Likewise. (vstrhq_u32): Likewise. (vstrhq_u16): Likewise. (vstrhq_p_f16): Likewise. (vstrhq_p_s32): Likewise. (vstrhq_p_s16): Likewise. (vstrhq_p_u32): Likewise. (vstrhq_p_u16): Likewise. (vstrwq_f32): Likewise. (vstrwq_s32): Likewise. (vstrwq_u32): Likewise. (vstrwq_p_f32): Likewise. (vstrwq_p_s32): Likewise. (vstrwq_p_u32): Likewise. (__arm_vst1q_s8): Define intrinsic. (__arm_vst1q_s32): Likewise. (__arm_vst1q_s16): Likewise. (__arm_vst1q_u8): Likewise. (__arm_vst1q_u32): Likewise. (__arm_vst1q_u16): Likewise. (__arm_vstrhq_scatter_offset_s32): Likewise. (__arm_vstrhq_scatter_offset_s16): Likewise. (__arm_vstrhq_scatter_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_u16): Likewise. (__arm_vstrhq_scatter_offset_p_s32): Likewise. (__arm_vstrhq_scatter_offset_p_s16): Likewise. (__arm_vstrhq_scatter_offset_p_u32): Likewise. (__arm_vstrhq_scatter_offset_p_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. (__arm_vstrhq_s32): Likewise. (__arm_vstrhq_s16): Likewise. (__arm_vstrhq_u32): Likewise. (__arm_vstrhq_u16): Likewise. (__arm_vstrhq_p_s32): Likewise. (__arm_vstrhq_p_s16): Likewise. (__arm_vstrhq_p_u32): Likewise. (__arm_vstrhq_p_u16): Likewise. (__arm_vstrwq_s32): Likewise. (__arm_vstrwq_u32): Likewise. (__arm_vstrwq_p_s32): Likewise. (__arm_vstrwq_p_u32): Likewise. (__arm_vstrwq_p_f32): Likewise. (__arm_vstrwq_f32): Likewise. (__arm_vst1q_f32): Likewise. (__arm_vst1q_f16): Likewise. (__arm_vstrhq_f16): Likewise. (__arm_vstrhq_p_f16): Likewise. (vst1q): Define polymorphic variant. (vstrhq): Likewise. (vstrhq_p): Likewise. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrwq_p): Likewise. (vstrwq): Likewise. * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. (STRS_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. (STRU): Likewise. (STRU_P): Likewise. * config/arm/mve.md (VST1Q): Define iterator. (VSTRHSOQ): Likewise. (VSTRHSSOQ): Likewise. (VSTRHQ): Likewise. (VSTRWQ): Likewise. (mve_vstrhq_fv8hf): Define RTL pattern. (mve_vstrhq_p_fv8hf): Likewise. (mve_vstrhq_p_<supf><mode>): Likewise. (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise. (mve_vstrhq_scatter_offset_<supf><mode>): Likewise. (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise. (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise. (mve_vstrhq_<supf><mode>): Likewise. (mve_vstrwq_fv4sf): Likewise. (mve_vstrwq_p_fv4sf): Likewise. (mve_vstrwq_p_<supf>v4si): Likewise. (mve_vstrwq_<supf>v4si): Likewise. (mve_vst1q_f<mode>): Define expand. (mve_vst1q_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. |
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Srinath Parvathaneni
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4cc23303ba |
[ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and word or double word from memory.
This patch supports the following Remaining MVE ACLE load intrinsics which load an halfword, word or double word from memory. vldrdq_gather_base_s64, vldrdq_gather_base_u64, vldrdq_gather_base_z_s64, vldrdq_gather_base_z_u64, vldrdq_gather_offset_s64, vldrdq_gather_offset_u64, vldrdq_gather_offset_z_s64, vldrdq_gather_offset_z_u64, vldrdq_gather_shifted_offset_s64, vldrdq_gather_shifted_offset_u64, vldrdq_gather_shifted_offset_z_s64, vldrdq_gather_shifted_offset_z_u64, vldrhq_gather_offset_f16, vldrhq_gather_offset_z_f16, vldrhq_gather_shifted_offset_f16, vldrhq_gather_shifted_offset_z_f16, vldrwq_gather_base_f32, vldrwq_gather_base_z_f32, vldrwq_gather_offset_f32, vldrwq_gather_offset_s32, vldrwq_gather_offset_u32, vldrwq_gather_offset_z_f32, vldrwq_gather_offset_z_s32, vldrwq_gather_offset_z_u32, vldrwq_gather_shifted_offset_f32, vldrwq_gather_shifted_offset_s32, vldrwq_gather_shifted_offset_u32, vldrwq_gather_shifted_offset_z_f32, vldrwq_gather_shifted_offset_z_s32, vldrwq_gather_shifted_offset_z_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. (mve_vldrhq_<supf><mode>): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_<supf><mode>): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_<supf>v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_<supf>v4si): Likewise. (mve_vld1q_f<mode>): Define RTL expand pattern. (mve_vld1q_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. |
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Srinath Parvathaneni
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bf1e3d5afa |
[ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from memory.
This patch supports the following MVE ACLE load intrinsics which load a byte, halfword, or word from memory. vld1q_s8, vld1q_s32, vld1q_s16, vld1q_u8, vld1q_u32, vld1q_u16, vldrhq_gather_offset_s32, vldrhq_gather_offset_s16, vldrhq_gather_offset_u32, vldrhq_gather_offset_u16, vldrhq_gather_offset_z_s32, vldrhq_gather_offset_z_s16, vldrhq_gather_offset_z_u32, vldrhq_gather_offset_z_u16, vldrhq_gather_shifted_offset_s32,vldrwq_f32, vldrwq_z_f32, vldrhq_gather_shifted_offset_s16, vldrhq_gather_shifted_offset_u32, vldrhq_gather_shifted_offset_u16, vldrhq_gather_shifted_offset_z_s32, vldrhq_gather_shifted_offset_z_s16, vldrhq_gather_shifted_offset_z_u32, vldrhq_gather_shifted_offset_z_u16, vldrhq_s32, vldrhq_s16, vldrhq_u32, vldrhq_u16, vldrhq_z_s32, vldrhq_z_s16, vldrhq_z_u32, vldrhq_z_u16, vldrwq_s32, vldrwq_u32, vldrwq_z_s32, vldrwq_z_u32, vld1q_f32, vld1q_f16, vldrhq_f16, vldrhq_z_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. (mve_vldrhq_<supf><mode>): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_<supf><mode>): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_<supf>v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_<supf>v4si): Likewise. (mve_vld1q_f<mode>): Define RTL expand pattern. (mve_vld1q_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. |
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Srinath Parvathaneni
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429d607bc4 |
[ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix.
This patch supports the following MVE ACLE load intrinsics with zero(_z) suffix. * ``_z`` (zero) which indicates false-predicated lanes are filled with zeroes, these are only used for load instructions. vldrbq_gather_offset_z_s16, vldrbq_gather_offset_z_u8, vldrbq_gather_offset_z_s32, vldrbq_gather_offset_z_u16, vldrbq_gather_offset_z_u32, vldrbq_gather_offset_z_s8, vldrbq_z_s16, vldrbq_z_u8, vldrbq_z_s8, vldrbq_z_s32, vldrbq_z_u16, vldrbq_z_u32, vldrwq_gather_base_z_u32, vldrwq_gather_base_z_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. (vldrbq_gather_offset_z_u8): Likewise. (vldrbq_gather_offset_z_s32): Likewise. (vldrbq_gather_offset_z_u16): Likewise. (vldrbq_gather_offset_z_u32): Likewise. (vldrbq_gather_offset_z_s8): Likewise. (vldrbq_z_s16): Likewise. (vldrbq_z_u8): Likewise. (vldrbq_z_s8): Likewise. (vldrbq_z_s32): Likewise. (vldrbq_z_u16): Likewise. (vldrbq_z_u32): Likewise. (vldrwq_gather_base_z_u32): Likewise. (vldrwq_gather_base_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. (__arm_vldrbq_gather_offset_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s16): Likewise. (__arm_vldrbq_gather_offset_z_u8): Likewise. (__arm_vldrbq_gather_offset_z_u32): Likewise. (__arm_vldrbq_gather_offset_z_u16): Likewise. (__arm_vldrbq_z_s8): Likewise. (__arm_vldrbq_z_s32): Likewise. (__arm_vldrbq_z_s16): Likewise. (__arm_vldrbq_z_u8): Likewise. (__arm_vldrbq_z_u32): Likewise. (__arm_vldrbq_z_u16): Likewise. (__arm_vldrwq_gather_base_z_s32): Likewise. (__arm_vldrwq_gather_base_z_u32): Likewise. (vldrbq_gather_offset_z): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define RTL pattern. (mve_vldrbq_z_<supf><mode>): Likewise. (mve_vldrwq_gather_base_z_<supf>v4si): Likewise. gcc/testsuite/ChangeLog: Likewise. 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c: Likewise. |
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Srinath Parvathaneni
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405e918c31 |
[ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix.
This patch supports the following MVE ACLE store intrinsics with predicated suffix. vstrbq_p_s8, vstrbq_p_s32, vstrbq_p_s16, vstrbq_p_u8, vstrbq_p_u32, vstrbq_p_u16, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u16, vstrwq_scatter_base_p_s32, vstrwq_scatter_base_p_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. (vstrbq_p_s32): Likewise. (vstrbq_p_s16): Likewise. (vstrbq_p_u8): Likewise. (vstrbq_p_u32): Likewise. (vstrbq_p_u16): Likewise. (vstrbq_scatter_offset_p_s8): Likewise. (vstrbq_scatter_offset_p_s32): Likewise. (vstrbq_scatter_offset_p_s16): Likewise. (vstrbq_scatter_offset_p_u8): Likewise. (vstrbq_scatter_offset_p_u32): Likewise. (vstrbq_scatter_offset_p_u16): Likewise. (vstrwq_scatter_base_p_s32): Likewise. (vstrwq_scatter_base_p_u32): Likewise. (__arm_vstrbq_p_s8): Define intrinsic. (__arm_vstrbq_p_s32): Likewise. (__arm_vstrbq_p_s16): Likewise. (__arm_vstrbq_p_u8): Likewise. (__arm_vstrbq_p_u32): Likewise. (__arm_vstrbq_p_u16): Likewise. (__arm_vstrbq_scatter_offset_p_s8): Likewise. (__arm_vstrbq_scatter_offset_p_s32): Likewise. (__arm_vstrbq_scatter_offset_p_s16): Likewise. (__arm_vstrbq_scatter_offset_p_u8): Likewise. (__arm_vstrbq_scatter_offset_p_u32): Likewise. (__arm_vstrbq_scatter_offset_p_u16): Likewise. (__arm_vstrwq_scatter_base_p_s32): Likewise. (__arm_vstrwq_scatter_base_p_u32): Likewise. (vstrbq_p): Define polymorphic variant. (vstrbq_scatter_offset_p): Likewise. (vstrwq_scatter_base_p): Likewise. * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define RTL pattern. (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise. (mve_vstrbq_p_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. |
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Srinath Parvathaneni
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535a8645bb |
[ARM][GCC][2/5x]: MVE load intrinsics.
This patch supports the following MVE ACLE load intrinsics. vldrbq_gather_offset_u8, vldrbq_gather_offset_s8, vldrbq_s8, vldrbq_u8, vldrbq_gather_offset_u16, vldrbq_gather_offset_s16, vldrbq_s16, vldrbq_u16, vldrbq_gather_offset_u32, vldrbq_gather_offset_s32, vldrbq_s32, vldrbq_u32, vldrwq_gather_base_s32, vldrwq_gather_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. (vldrbq_gather_offset_s8): Likewise. (vldrbq_s8): Likewise. (vldrbq_u8): Likewise. (vldrbq_gather_offset_u16): Likewise. (vldrbq_gather_offset_s16): Likewise. (vldrbq_s16): Likewise. (vldrbq_u16): Likewise. (vldrbq_gather_offset_u32): Likewise. (vldrbq_gather_offset_s32): Likewise. (vldrbq_s32): Likewise. (vldrbq_u32): Likewise. (vldrwq_gather_base_s32): Likewise. (vldrwq_gather_base_u32): Likewise. (__arm_vldrbq_gather_offset_u8): Define intrinsic. (__arm_vldrbq_gather_offset_s8): Likewise. (__arm_vldrbq_s8): Likewise. (__arm_vldrbq_u8): Likewise. (__arm_vldrbq_gather_offset_u16): Likewise. (__arm_vldrbq_gather_offset_s16): Likewise. (__arm_vldrbq_s16): Likewise. (__arm_vldrbq_u16): Likewise. (__arm_vldrbq_gather_offset_u32): Likewise. (__arm_vldrbq_gather_offset_s32): Likewise. (__arm_vldrbq_s32): Likewise. (__arm_vldrbq_u32): Likewise. (__arm_vldrwq_gather_base_s32): Likewise. (__arm_vldrwq_gather_base_u32): Likewise. (vldrbq_gather_offset): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/mve.md (VLDRBGOQ): Define iterator. (VLDRBQ): Likewise. (VLDRWGBQ): Likewise. (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern. (mve_vldrbq_<supf><mode>): Likewise. (mve_vldrwq_gather_base_<supf>v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. |
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Srinath Parvathaneni
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4ff6857599 |
[ARM][GCC][1/5x]: MVE store intrinsics.
This patch supports the following MVE ACLE store intrinsics. vstrbq_scatter_offset_s8, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_u8, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u16, vstrbq_s8, vstrbq_s32, vstrbq_s16, vstrbq_u8, vstrbq_u32, vstrbq_u16, vstrwq_scatter_base_s32, vstrwq_scatter_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_s8): Define macro. (vstrbq_u8): Likewise. (vstrbq_u16): Likewise. (vstrbq_scatter_offset_s8): Likewise. (vstrbq_scatter_offset_u8): Likewise. (vstrbq_scatter_offset_u16): Likewise. (vstrbq_s16): Likewise. (vstrbq_u32): Likewise. (vstrbq_scatter_offset_s16): Likewise. (vstrbq_scatter_offset_u32): Likewise. (vstrbq_s32): Likewise. (vstrbq_scatter_offset_s32): Likewise. (vstrwq_scatter_base_s32): Likewise. (vstrwq_scatter_base_u32): Likewise. (__arm_vstrbq_scatter_offset_s8): Define intrinsic. (__arm_vstrbq_scatter_offset_s32): Likewise. (__arm_vstrbq_scatter_offset_s16): Likewise. (__arm_vstrbq_scatter_offset_u8): Likewise. (__arm_vstrbq_scatter_offset_u32): Likewise. (__arm_vstrbq_scatter_offset_u16): Likewise. (__arm_vstrbq_s8): Likewise. (__arm_vstrbq_s32): Likewise. (__arm_vstrbq_s16): Likewise. (__arm_vstrbq_u8): Likewise. (__arm_vstrbq_u32): Likewise. (__arm_vstrbq_u16): Likewise. (__arm_vstrwq_scatter_base_s32): Likewise. (__arm_vstrwq_scatter_base_u32): Likewise. (vstrbq): Define polymorphic variant. (vstrbq_scatter_offset): Likewise. (vstrwq_scatter_base): Likewise. * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. (VSTRWSBQ): Define iterators. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (mve_vstrbq_<supf><mode>): Define RTL pattern. (mve_vstrbq_scatter_offset_<supf><mode>): Likewise. (mve_vstrwq_scatter_base_<supf>v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vstrbq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. |
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Srinath Parvathaneni
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532e9e2402 |
[ARM][GCC][4/4x]: MVE intrinsics with quaternary operands.
This patch supports following MVE ACLE intrinsics with quaternary operands. vabdq_m_f32, vabdq_m_f16, vaddq_m_f32, vaddq_m_f16, vaddq_m_n_f32, vaddq_m_n_f16, vandq_m_f32, vandq_m_f16, vbicq_m_f32, vbicq_m_f16, vbrsrq_m_n_f32, vbrsrq_m_n_f16, vcaddq_rot270_m_f32, vcaddq_rot270_m_f16, vcaddq_rot90_m_f32, vcaddq_rot90_m_f16, vcmlaq_m_f32, vcmlaq_m_f16, vcmlaq_rot180_m_f32, vcmlaq_rot180_m_f16, vcmlaq_rot270_m_f32, vcmlaq_rot270_m_f16, vcmlaq_rot90_m_f32, vcmlaq_rot90_m_f16, vcmulq_m_f32, vcmulq_m_f16, vcmulq_rot180_m_f32, vcmulq_rot180_m_f16, vcmulq_rot270_m_f32, vcmulq_rot270_m_f16, vcmulq_rot90_m_f32, vcmulq_rot90_m_f16, vcvtq_m_n_s32_f32, vcvtq_m_n_s16_f16, vcvtq_m_n_u32_f32, vcvtq_m_n_u16_f16, veorq_m_f32, veorq_m_f16, vfmaq_m_f32, vfmaq_m_f16, vfmaq_m_n_f32, vfmaq_m_n_f16, vfmasq_m_n_f32, vfmasq_m_n_f16, vfmsq_m_f32, vfmsq_m_f16, vmaxnmq_m_f32, vmaxnmq_m_f16, vminnmq_m_f32, vminnmq_m_f16, vmulq_m_f32, vmulq_m_f16, vmulq_m_n_f32, vmulq_m_n_f16, vornq_m_f32, vornq_m_f16, vorrq_m_f32, vorrq_m_f16, vsubq_m_f32, vsubq_m_f16, vsubq_m_n_f32, vsubq_m_n_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vabdq_m_f32): Define macro. (vabdq_m_f16): Likewise. (vaddq_m_f32): Likewise. (vaddq_m_f16): Likewise. (vaddq_m_n_f32): Likewise. (vaddq_m_n_f16): Likewise. (vandq_m_f32): Likewise. (vandq_m_f16): Likewise. (vbicq_m_f32): Likewise. (vbicq_m_f16): Likewise. (vbrsrq_m_n_f32): Likewise. (vbrsrq_m_n_f16): Likewise. (vcaddq_rot270_m_f32): Likewise. (vcaddq_rot270_m_f16): Likewise. (vcaddq_rot90_m_f32): Likewise. (vcaddq_rot90_m_f16): Likewise. (vcmlaq_m_f32): Likewise. (vcmlaq_m_f16): Likewise. (vcmlaq_rot180_m_f32): Likewise. (vcmlaq_rot180_m_f16): Likewise. (vcmlaq_rot270_m_f32): Likewise. (vcmlaq_rot270_m_f16): Likewise. (vcmlaq_rot90_m_f32): Likewise. (vcmlaq_rot90_m_f16): Likewise. (vcmulq_m_f32): Likewise. (vcmulq_m_f16): Likewise. (vcmulq_rot180_m_f32): Likewise. (vcmulq_rot180_m_f16): Likewise. (vcmulq_rot270_m_f32): Likewise. (vcmulq_rot270_m_f16): Likewise. (vcmulq_rot90_m_f32): Likewise. (vcmulq_rot90_m_f16): Likewise. (vcvtq_m_n_s32_f32): Likewise. (vcvtq_m_n_s16_f16): Likewise. (vcvtq_m_n_u32_f32): Likewise. (vcvtq_m_n_u16_f16): Likewise. (veorq_m_f32): Likewise. (veorq_m_f16): Likewise. (vfmaq_m_f32): Likewise. (vfmaq_m_f16): Likewise. (vfmaq_m_n_f32): Likewise. (vfmaq_m_n_f16): Likewise. (vfmasq_m_n_f32): Likewise. (vfmasq_m_n_f16): Likewise. (vfmsq_m_f32): Likewise. (vfmsq_m_f16): Likewise. (vmaxnmq_m_f32): Likewise. (vmaxnmq_m_f16): Likewise. (vminnmq_m_f32): Likewise. (vminnmq_m_f16): Likewise. (vmulq_m_f32): Likewise. (vmulq_m_f16): Likewise. (vmulq_m_n_f32): Likewise. (vmulq_m_n_f16): Likewise. (vornq_m_f32): Likewise. (vornq_m_f16): Likewise. (vorrq_m_f32): Likewise. (vorrq_m_f16): Likewise. (vsubq_m_f32): Likewise. (vsubq_m_f16): Likewise. (vsubq_m_n_f32): Likewise. (vsubq_m_n_f16): Likewise. (__attribute__): Likewise. (__arm_vabdq_m_f32): Likewise. (__arm_vabdq_m_f16): Likewise. (__arm_vaddq_m_f32): Likewise. (__arm_vaddq_m_f16): Likewise. (__arm_vaddq_m_n_f32): Likewise. (__arm_vaddq_m_n_f16): Likewise. (__arm_vandq_m_f32): Likewise. (__arm_vandq_m_f16): Likewise. (__arm_vbicq_m_f32): Likewise. (__arm_vbicq_m_f16): Likewise. (__arm_vbrsrq_m_n_f32): Likewise. (__arm_vbrsrq_m_n_f16): Likewise. (__arm_vcaddq_rot270_m_f32): Likewise. (__arm_vcaddq_rot270_m_f16): Likewise. (__arm_vcaddq_rot90_m_f32): Likewise. (__arm_vcaddq_rot90_m_f16): Likewise. (__arm_vcmlaq_m_f32): Likewise. (__arm_vcmlaq_m_f16): Likewise. (__arm_vcmlaq_rot180_m_f32): Likewise. (__arm_vcmlaq_rot180_m_f16): Likewise. (__arm_vcmlaq_rot270_m_f32): Likewise. (__arm_vcmlaq_rot270_m_f16): Likewise. (__arm_vcmlaq_rot90_m_f32): Likewise. (__arm_vcmlaq_rot90_m_f16): Likewise. (__arm_vcmulq_m_f32): Likewise. (__arm_vcmulq_m_f16): Likewise. (__arm_vcmulq_rot180_m_f32): Define intrinsic. (__arm_vcmulq_rot180_m_f16): Likewise. (__arm_vcmulq_rot270_m_f32): Likewise. (__arm_vcmulq_rot270_m_f16): Likewise. (__arm_vcmulq_rot90_m_f32): Likewise. (__arm_vcmulq_rot90_m_f16): Likewise. (__arm_vcvtq_m_n_s32_f32): Likewise. (__arm_vcvtq_m_n_s16_f16): Likewise. (__arm_vcvtq_m_n_u32_f32): Likewise. (__arm_vcvtq_m_n_u16_f16): Likewise. (__arm_veorq_m_f32): Likewise. (__arm_veorq_m_f16): Likewise. (__arm_vfmaq_m_f32): Likewise. (__arm_vfmaq_m_f16): Likewise. (__arm_vfmaq_m_n_f32): Likewise. (__arm_vfmaq_m_n_f16): Likewise. (__arm_vfmasq_m_n_f32): Likewise. (__arm_vfmasq_m_n_f16): Likewise. (__arm_vfmsq_m_f32): Likewise. (__arm_vfmsq_m_f16): Likewise. (__arm_vmaxnmq_m_f32): Likewise. (__arm_vmaxnmq_m_f16): Likewise. (__arm_vminnmq_m_f32): Likewise. (__arm_vminnmq_m_f16): Likewise. (__arm_vmulq_m_f32): Likewise. (__arm_vmulq_m_f16): Likewise. (__arm_vmulq_m_n_f32): Likewise. (__arm_vmulq_m_n_f16): Likewise. (__arm_vornq_m_f32): Likewise. (__arm_vornq_m_f16): Likewise. (__arm_vorrq_m_f32): Likewise. (__arm_vorrq_m_f16): Likewise. (__arm_vsubq_m_f32): Likewise. (__arm_vsubq_m_f16): Likewise. (__arm_vsubq_m_n_f32): Likewise. (__arm_vsubq_m_n_f16): Likewise. (vabdq_m): Define polymorphic variant. (vaddq_m): Likewise. (vaddq_m_n): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (vcmlaq_m): Likewise. (vcmlaq_rot180_m): Likewise. (vcmlaq_rot270_m): Likewise. (vcmlaq_rot90_m): Likewise. (vcmulq_m): Likewise. (vcmulq_rot180_m): Likewise. (vcmulq_rot270_m): Likewise. (vcmulq_rot90_m): Likewise. (veorq_m): Likewise. (vfmaq_m): Likewise. (vfmaq_m_n): Likewise. (vfmasq_m_n): Likewise. (vfmsq_m): Likewise. (vmaxnmq_m): Likewise. (vminnmq_m): Likewise. (vmulq_m): Likewise. (vmulq_m_n): Likewise. (vornq_m): Likewise. (vsubq_m): Likewise. (vsubq_m_n): Likewise. (vorrq_m): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern. (mve_vaddq_m_f<mode>): Likewise. (mve_vaddq_m_n_f<mode>): Likewise. (mve_vandq_m_f<mode>): Likewise. (mve_vbicq_m_f<mode>): Likewise. (mve_vbrsrq_m_n_f<mode>): Likewise. (mve_vcaddq_rot270_m_f<mode>): Likewise. (mve_vcaddq_rot90_m_f<mode>): Likewise. (mve_vcmlaq_m_f<mode>): Likewise. (mve_vcmlaq_rot180_m_f<mode>): Likewise. (mve_vcmlaq_rot270_m_f<mode>): Likewise. (mve_vcmlaq_rot90_m_f<mode>): Likewise. (mve_vcmulq_m_f<mode>): Likewise. (mve_vcmulq_rot180_m_f<mode>): Likewise. (mve_vcmulq_rot270_m_f<mode>): Likewise. (mve_vcmulq_rot90_m_f<mode>): Likewise. (mve_veorq_m_f<mode>): Likewise. (mve_vfmaq_m_f<mode>): Likewise. (mve_vfmaq_m_n_f<mode>): Likewise. (mve_vfmasq_m_n_f<mode>): Likewise. (mve_vfmsq_m_f<mode>): Likewise. (mve_vmaxnmq_m_f<mode>): Likewise. (mve_vminnmq_m_f<mode>): Likewise. (mve_vmulq_m_f<mode>): Likewise. (mve_vmulq_m_n_f<mode>): Likewise. (mve_vornq_m_f<mode>): Likewise. (mve_vorrq_m_f<mode>): Likewise. (mve_vsubq_m_f<mode>): Likewise. (mve_vsubq_m_n_f<mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. |
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Srinath Parvathaneni
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f2170a379b |
[ARM][GCC][3/4x]: MVE intrinsics with quaternary operands.
This patch supports following MVE ACLE intrinsics with quaternary operands. vmlaldavaq_p_s16, vmlaldavaq_p_s32, vmlaldavaq_p_u16, vmlaldavaq_p_u32, vmlaldavaxq_p_s16, vmlaldavaxq_p_s32, vmlaldavaxq_p_u16, vmlaldavaxq_p_u32, vmlsldavaq_p_s16, vmlsldavaq_p_s32, vmlsldavaxq_p_s16, vmlsldavaxq_p_s32, vmullbq_poly_m_p16, vmullbq_poly_m_p8, vmulltq_poly_m_p16, vmulltq_poly_m_p8, vqdmullbq_m_n_s16, vqdmullbq_m_n_s32, vqdmullbq_m_s16, vqdmullbq_m_s32, vqdmulltq_m_n_s16, vqdmulltq_m_n_s32, vqdmulltq_m_s16, vqdmulltq_m_s32, vqrshrnbq_m_n_s16, vqrshrnbq_m_n_s32, vqrshrnbq_m_n_u16, vqrshrnbq_m_n_u32, vqrshrntq_m_n_s16, vqrshrntq_m_n_s32, vqrshrntq_m_n_u16, vqrshrntq_m_n_u32, vqrshrunbq_m_n_s16, vqrshrunbq_m_n_s32, vqrshruntq_m_n_s16, vqrshruntq_m_n_s32, vqshrnbq_m_n_s16, vqshrnbq_m_n_s32, vqshrnbq_m_n_u16, vqshrnbq_m_n_u32, vqshrntq_m_n_s16, vqshrntq_m_n_s32, vqshrntq_m_n_u16, vqshrntq_m_n_u32, vqshrunbq_m_n_s16, vqshrunbq_m_n_s32, vqshruntq_m_n_s16, vqshruntq_m_n_s32, vrmlaldavhaq_p_s32, vrmlaldavhaq_p_u32, vrmlaldavhaxq_p_s32, vrmlsldavhaq_p_s32, vrmlsldavhaxq_p_s32, vrshrnbq_m_n_s16, vrshrnbq_m_n_s32, vrshrnbq_m_n_u16, vrshrnbq_m_n_u32, vrshrntq_m_n_s16, vrshrntq_m_n_s32, vrshrntq_m_n_u16, vrshrntq_m_n_u32, vshllbq_m_n_s16, vshllbq_m_n_s8, vshllbq_m_n_u16, vshllbq_m_n_u8, vshlltq_m_n_s16, vshlltq_m_n_s8, vshlltq_m_n_u16, vshlltq_m_n_u8, vshrnbq_m_n_s16, vshrnbq_m_n_s32, vshrnbq_m_n_u16, vshrnbq_m_n_u32, vshrntq_m_n_s16, vshrntq_m_n_s32, vshrntq_m_n_u16, vshrntq_m_n_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-protos.h (arm_mve_immediate_check): * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check mode and interger value. * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. (vmlaldavaq_p_s16): Likewise. (vmlaldavaq_p_u32): Likewise. (vmlaldavaq_p_u16): Likewise. (vmlaldavaxq_p_s32): Likewise. (vmlaldavaxq_p_s16): Likewise. (vmlaldavaxq_p_u32): Likewise. (vmlaldavaxq_p_u16): Likewise. (vmlsldavaq_p_s32): Likewise. (vmlsldavaq_p_s16): Likewise. (vmlsldavaxq_p_s32): Likewise. (vmlsldavaxq_p_s16): Likewise. (vmullbq_poly_m_p8): Likewise. (vmullbq_poly_m_p16): Likewise. (vmulltq_poly_m_p8): Likewise. (vmulltq_poly_m_p16): Likewise. (vqdmullbq_m_n_s32): Likewise. (vqdmullbq_m_n_s16): Likewise. (vqdmullbq_m_s32): Likewise. (vqdmullbq_m_s16): Likewise. (vqdmulltq_m_n_s32): Likewise. (vqdmulltq_m_n_s16): Likewise. (vqdmulltq_m_s32): Likewise. (vqdmulltq_m_s16): Likewise. (vqrshrnbq_m_n_s32): Likewise. (vqrshrnbq_m_n_s16): Likewise. (vqrshrnbq_m_n_u32): Likewise. (vqrshrnbq_m_n_u16): Likewise. (vqrshrntq_m_n_s32): Likewise. (vqrshrntq_m_n_s16): Likewise. (vqrshrntq_m_n_u32): Likewise. (vqrshrntq_m_n_u16): Likewise. (vqrshrunbq_m_n_s32): Likewise. (vqrshrunbq_m_n_s16): Likewise. (vqrshruntq_m_n_s32): Likewise. (vqrshruntq_m_n_s16): Likewise. (vqshrnbq_m_n_s32): Likewise. (vqshrnbq_m_n_s16): Likewise. (vqshrnbq_m_n_u32): Likewise. (vqshrnbq_m_n_u16): Likewise. (vqshrntq_m_n_s32): Likewise. (vqshrntq_m_n_s16): Likewise. (vqshrntq_m_n_u32): Likewise. (vqshrntq_m_n_u16): Likewise. (vqshrunbq_m_n_s32): Likewise. (vqshrunbq_m_n_s16): Likewise. (vqshruntq_m_n_s32): Likewise. (vqshruntq_m_n_s16): Likewise. (vrmlaldavhaq_p_s32): Likewise. (vrmlaldavhaq_p_u32): Likewise. (vrmlaldavhaxq_p_s32): Likewise. (vrmlsldavhaq_p_s32): Likewise. (vrmlsldavhaxq_p_s32): Likewise. (vrshrnbq_m_n_s32): Likewise. (vrshrnbq_m_n_s16): Likewise. (vrshrnbq_m_n_u32): Likewise. (vrshrnbq_m_n_u16): Likewise. (vrshrntq_m_n_s32): Likewise. (vrshrntq_m_n_s16): Likewise. (vrshrntq_m_n_u32): Likewise. (vrshrntq_m_n_u16): Likewise. (vshllbq_m_n_s8): Likewise. (vshllbq_m_n_s16): Likewise. (vshllbq_m_n_u8): Likewise. (vshllbq_m_n_u16): Likewise. (vshlltq_m_n_s8): Likewise. (vshlltq_m_n_s16): Likewise. (vshlltq_m_n_u8): Likewise. (vshlltq_m_n_u16): Likewise. (vshrnbq_m_n_s32): Likewise. (vshrnbq_m_n_s16): Likewise. (vshrnbq_m_n_u32): Likewise. (vshrnbq_m_n_u16): Likewise. (vshrntq_m_n_s32): Likewise. (vshrntq_m_n_s16): Likewise. (vshrntq_m_n_u32): Likewise. (vshrntq_m_n_u16): Likewise. (__arm_vmlaldavaq_p_s32): Define intrinsic. (__arm_vmlaldavaq_p_s16): Likewise. (__arm_vmlaldavaq_p_u32): Likewise. (__arm_vmlaldavaq_p_u16): Likewise. (__arm_vmlaldavaxq_p_s32): Likewise. (__arm_vmlaldavaxq_p_s16): Likewise. (__arm_vmlaldavaxq_p_u32): Likewise. (__arm_vmlaldavaxq_p_u16): Likewise. (__arm_vmlsldavaq_p_s32): Likewise. (__arm_vmlsldavaq_p_s16): Likewise. (__arm_vmlsldavaxq_p_s32): Likewise. (__arm_vmlsldavaxq_p_s16): Likewise. (__arm_vmullbq_poly_m_p8): Likewise. (__arm_vmullbq_poly_m_p16): Likewise. (__arm_vmulltq_poly_m_p8): Likewise. (__arm_vmulltq_poly_m_p16): Likewise. (__arm_vqdmullbq_m_n_s32): Likewise. (__arm_vqdmullbq_m_n_s16): Likewise. (__arm_vqdmullbq_m_s32): Likewise. (__arm_vqdmullbq_m_s16): Likewise. (__arm_vqdmulltq_m_n_s32): Likewise. (__arm_vqdmulltq_m_n_s16): Likewise. (__arm_vqdmulltq_m_s32): Likewise. (__arm_vqdmulltq_m_s16): Likewise. (__arm_vqrshrnbq_m_n_s32): Likewise. (__arm_vqrshrnbq_m_n_s16): Likewise. (__arm_vqrshrnbq_m_n_u32): Likewise. (__arm_vqrshrnbq_m_n_u16): Likewise. (__arm_vqrshrntq_m_n_s32): Likewise. (__arm_vqrshrntq_m_n_s16): Likewise. (__arm_vqrshrntq_m_n_u32): Likewise. (__arm_vqrshrntq_m_n_u16): Likewise. (__arm_vqrshrunbq_m_n_s32): Likewise. (__arm_vqrshrunbq_m_n_s16): Likewise. (__arm_vqrshruntq_m_n_s32): Likewise. (__arm_vqrshruntq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_s32): Likewise. (__arm_vqshrnbq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_u32): Likewise. (__arm_vqshrnbq_m_n_u16): Likewise. (__arm_vqshrntq_m_n_s32): Likewise. (__arm_vqshrntq_m_n_s16): Likewise. (__arm_vqshrntq_m_n_u32): Likewise. (__arm_vqshrntq_m_n_u16): Likewise. (__arm_vqshrunbq_m_n_s32): Likewise. (__arm_vqshrunbq_m_n_s16): Likewise. (__arm_vqshruntq_m_n_s32): Likewise. (__arm_vqshruntq_m_n_s16): Likewise. (__arm_vrmlaldavhaq_p_s32): Likewise. (__arm_vrmlaldavhaq_p_u32): Likewise. (__arm_vrmlaldavhaxq_p_s32): Likewise. (__arm_vrmlsldavhaq_p_s32): Likewise. (__arm_vrmlsldavhaxq_p_s32): Likewise. (__arm_vrshrnbq_m_n_s32): Likewise. (__arm_vrshrnbq_m_n_s16): Likewise. (__arm_vrshrnbq_m_n_u32): Likewise. (__arm_vrshrnbq_m_n_u16): Likewise. (__arm_vrshrntq_m_n_s32): Likewise. (__arm_vrshrntq_m_n_s16): Likewise. (__arm_vrshrntq_m_n_u32): Likewise. (__arm_vrshrntq_m_n_u16): Likewise. (__arm_vshllbq_m_n_s8): Likewise. (__arm_vshllbq_m_n_s16): Likewise. (__arm_vshllbq_m_n_u8): Likewise. (__arm_vshllbq_m_n_u16): Likewise. (__arm_vshlltq_m_n_s8): Likewise. (__arm_vshlltq_m_n_s16): Likewise. (__arm_vshlltq_m_n_u8): Likewise. (__arm_vshlltq_m_n_u16): Likewise. (__arm_vshrnbq_m_n_s32): Likewise. (__arm_vshrnbq_m_n_s16): Likewise. (__arm_vshrnbq_m_n_u32): Likewise. (__arm_vshrnbq_m_n_u16): Likewise. (__arm_vshrntq_m_n_s32): Likewise. (__arm_vshrntq_m_n_s16): Likewise. (__arm_vshrntq_m_n_u32): Likewise. (__arm_vshrntq_m_n_u16): Likewise. (vmullbq_poly_m): Define polymorphic variant. (vmulltq_poly_m): Likewise. (vshllbq_m): Likewise. (vshrntq_m_n): Likewise. (vshrnbq_m_n): Likewise. (vshlltq_m_n): Likewise. (vshllbq_m_n): Likewise. (vrshrntq_m_n): Likewise. (vrshrnbq_m_n): Likewise. (vqshruntq_m_n): Likewise. (vqshrunbq_m_n): Likewise. (vqdmullbq_m_n): Likewise. (vqdmullbq_m): Likewise. (vqdmulltq_m_n): Likewise. (vqdmulltq_m): Likewise. (vqrshrnbq_m_n): Likewise. (vqrshrntq_m_n): Likewise. (vqrshrunbq_m_n): Likewise. (vqrshruntq_m_n): Likewise. (vqshrnbq_m_n): Likewise. (vqshrntq_m_n): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifiers. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. (VMLALDAVAXQ_P): Likewise. (VQRSHRNBQ_M_N): Likewise. (VQRSHRNTQ_M_N): Likewise. (VQSHRNBQ_M_N): Likewise. (VQSHRNTQ_M_N): Likewise. (VRSHRNBQ_M_N): Likewise. (VRSHRNTQ_M_N): Likewise. (VSHLLBQ_M_N): Likewise. (VSHLLTQ_M_N): Likewise. (VSHRNBQ_M_N): Likewise. (VSHRNTQ_M_N): Likewise. (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern. (mve_vmlaldavaxq_p_<supf><mode>): Likewise. (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. (mve_vqrshrntq_m_n_<supf><mode>): Likewise. (mve_vqshrnbq_m_n_<supf><mode>): Likewise. (mve_vqshrntq_m_n_<supf><mode>): Likewise. (mve_vrmlaldavhaq_p_sv4si): Likewise. (mve_vrshrnbq_m_n_<supf><mode>): Likewise. (mve_vrshrntq_m_n_<supf><mode>): Likewise. (mve_vshllbq_m_n_<supf><mode>): Likewise. (mve_vshlltq_m_n_<supf><mode>): Likewise. (mve_vshrnbq_m_n_<supf><mode>): Likewise. (mve_vshrntq_m_n_<supf><mode>): Likewise. (mve_vmlsldavaq_p_s<mode>): Likewise. (mve_vmlsldavaxq_p_s<mode>): Likewise. (mve_vmullbq_poly_m_p<mode>): Likewise. (mve_vmulltq_poly_m_p<mode>): Likewise. (mve_vqdmullbq_m_n_s<mode>): Likewise. (mve_vqdmullbq_m_s<mode>): Likewise. (mve_vqdmulltq_m_n_s<mode>): Likewise. (mve_vqdmulltq_m_s<mode>): Likewise. (mve_vqrshrunbq_m_n_s<mode>): Likewise. (mve_vqrshruntq_m_n_s<mode>): Likewise. (mve_vqshrunbq_m_n_s<mode>): Likewise. (mve_vqshruntq_m_n_s<mode>): Likewise. (mve_vrmlaldavhaq_p_uv4si): Likewise. (mve_vrmlaldavhaxq_p_sv4si): Likewise. (mve_vrmlsldavhaq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_p_sv4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise. |
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Srinath Parvathaneni
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8eb3b6b9cf |
[ARM][GCC][2/4x]: MVE intrinsics with quaternary operands.
This patch supports following MVE ACLE intrinsics with quaternary operands. vabdq_m_s8, vabdq_m_s32, vabdq_m_s16, vabdq_m_u8, vabdq_m_u32, vabdq_m_u16, vaddq_m_n_s8, vaddq_m_n_s32, vaddq_m_n_s16, vaddq_m_n_u8, vaddq_m_n_u32, vaddq_m_n_u16, vaddq_m_s8, vaddq_m_s32, vaddq_m_s16, vaddq_m_u8, vaddq_m_u32, vaddq_m_u16, vandq_m_s8, vandq_m_s32, vandq_m_s16, vandq_m_u8, vandq_m_u32, vandq_m_u16, vbicq_m_s8, vbicq_m_s32, vbicq_m_s16, vbicq_m_u8, vbicq_m_u32, vbicq_m_u16, vbrsrq_m_n_s8, vbrsrq_m_n_s32, vbrsrq_m_n_s16, vbrsrq_m_n_u8, vbrsrq_m_n_u32, vbrsrq_m_n_u16, vcaddq_rot270_m_s8, vcaddq_rot270_m_s32, vcaddq_rot270_m_s16, vcaddq_rot270_m_u8, vcaddq_rot270_m_u32, vcaddq_rot270_m_u16, vcaddq_rot90_m_s8, vcaddq_rot90_m_s32, vcaddq_rot90_m_s16, vcaddq_rot90_m_u8, vcaddq_rot90_m_u32, vcaddq_rot90_m_u16, veorq_m_s8, veorq_m_s32, veorq_m_s16, veorq_m_u8, veorq_m_u32, veorq_m_u16, vhaddq_m_n_s8, vhaddq_m_n_s32, vhaddq_m_n_s16, vhaddq_m_n_u8, vhaddq_m_n_u32, vhaddq_m_n_u16, vhaddq_m_s8, vhaddq_m_s32, vhaddq_m_s16, vhaddq_m_u8, vhaddq_m_u32, vhaddq_m_u16, vhcaddq_rot270_m_s8, vhcaddq_rot270_m_s32, vhcaddq_rot270_m_s16, vhcaddq_rot90_m_s8, vhcaddq_rot90_m_s32, vhcaddq_rot90_m_s16, vhsubq_m_n_s8, vhsubq_m_n_s32, vhsubq_m_n_s16, vhsubq_m_n_u8, vhsubq_m_n_u32, vhsubq_m_n_u16, vhsubq_m_s8, vhsubq_m_s32, vhsubq_m_s16, vhsubq_m_u8, vhsubq_m_u32, vhsubq_m_u16, vmaxq_m_s8, vmaxq_m_s32, vmaxq_m_s16, vmaxq_m_u8, vmaxq_m_u32, vmaxq_m_u16, vminq_m_s8, vminq_m_s32, vminq_m_s16, vminq_m_u8, vminq_m_u32, vminq_m_u16, vmladavaq_p_s8, vmladavaq_p_s32, vmladavaq_p_s16, vmladavaq_p_u8, vmladavaq_p_u32, vmladavaq_p_u16, vmladavaxq_p_s8, vmladavaxq_p_s32, vmladavaxq_p_s16, vmlaq_m_n_s8, vmlaq_m_n_s32, vmlaq_m_n_s16, vmlaq_m_n_u8, vmlaq_m_n_u32, vmlaq_m_n_u16, vmlasq_m_n_s8, vmlasq_m_n_s32, vmlasq_m_n_s16, vmlasq_m_n_u8, vmlasq_m_n_u32, vmlasq_m_n_u16, vmlsdavaq_p_s8, vmlsdavaq_p_s32, vmlsdavaq_p_s16, vmlsdavaxq_p_s8, vmlsdavaxq_p_s32, vmlsdavaxq_p_s16, vmulhq_m_s8, vmulhq_m_s32, vmulhq_m_s16, vmulhq_m_u8, vmulhq_m_u32, vmulhq_m_u16, vmullbq_int_m_s8, vmullbq_int_m_s32, vmullbq_int_m_s16, vmullbq_int_m_u8, vmullbq_int_m_u32, vmullbq_int_m_u16, vmulltq_int_m_s8, vmulltq_int_m_s32, vmulltq_int_m_s16, vmulltq_int_m_u8, vmulltq_int_m_u32, vmulltq_int_m_u16, vmulq_m_n_s8, vmulq_m_n_s32, vmulq_m_n_s16, vmulq_m_n_u8, vmulq_m_n_u32, vmulq_m_n_u16, vmulq_m_s8, vmulq_m_s32, vmulq_m_s16, vmulq_m_u8, vmulq_m_u32, vmulq_m_u16, vornq_m_s8, vornq_m_s32, vornq_m_s16, vornq_m_u8, vornq_m_u32, vornq_m_u16, vorrq_m_s8, vorrq_m_s32, vorrq_m_s16, vorrq_m_u8, vorrq_m_u32, vorrq_m_u16, vqaddq_m_n_s8, vqaddq_m_n_s32, vqaddq_m_n_s16, vqaddq_m_n_u8, vqaddq_m_n_u32, vqaddq_m_n_u16, vqaddq_m_s8, vqaddq_m_s32, vqaddq_m_s16, vqaddq_m_u8, vqaddq_m_u32, vqaddq_m_u16, vqdmladhq_m_s8, vqdmladhq_m_s32, vqdmladhq_m_s16, vqdmladhxq_m_s8, vqdmladhxq_m_s32, vqdmladhxq_m_s16, vqdmlahq_m_n_s8, vqdmlahq_m_n_s32, vqdmlahq_m_n_s16, vqdmlahq_m_n_u8, vqdmlahq_m_n_u32, vqdmlahq_m_n_u16, vqdmlsdhq_m_s8, vqdmlsdhq_m_s32, vqdmlsdhq_m_s16, vqdmlsdhxq_m_s8, vqdmlsdhxq_m_s32, vqdmlsdhxq_m_s16, vqdmulhq_m_n_s8, vqdmulhq_m_n_s32, vqdmulhq_m_n_s16, vqdmulhq_m_s8, vqdmulhq_m_s32, vqdmulhq_m_s16, vqrdmladhq_m_s8, vqrdmladhq_m_s32, vqrdmladhq_m_s16, vqrdmladhxq_m_s8, vqrdmladhxq_m_s32, vqrdmladhxq_m_s16, vqrdmlahq_m_n_s8, vqrdmlahq_m_n_s32, vqrdmlahq_m_n_s16, vqrdmlahq_m_n_u8, vqrdmlahq_m_n_u32, vqrdmlahq_m_n_u16, vqrdmlashq_m_n_s8, vqrdmlashq_m_n_s32, vqrdmlashq_m_n_s16, vqrdmlashq_m_n_u8, vqrdmlashq_m_n_u32, vqrdmlashq_m_n_u16, vqrdmlsdhq_m_s8, vqrdmlsdhq_m_s32, vqrdmlsdhq_m_s16, vqrdmlsdhxq_m_s8, vqrdmlsdhxq_m_s32, vqrdmlsdhxq_m_s16, vqrdmulhq_m_n_s8, vqrdmulhq_m_n_s32, vqrdmulhq_m_n_s16, vqrdmulhq_m_s8, vqrdmulhq_m_s32, vqrdmulhq_m_s16, vqrshlq_m_s8, vqrshlq_m_s32, vqrshlq_m_s16, vqrshlq_m_u8, vqrshlq_m_u32, vqrshlq_m_u16, vqshlq_m_n_s8, vqshlq_m_n_s32, vqshlq_m_n_s16, vqshlq_m_n_u8, vqshlq_m_n_u32, vqshlq_m_n_u16, vqshlq_m_s8, vqshlq_m_s32, vqshlq_m_s16, vqshlq_m_u8, vqshlq_m_u32, vqshlq_m_u16, vqsubq_m_n_s8, vqsubq_m_n_s32, vqsubq_m_n_s16, vqsubq_m_n_u8, vqsubq_m_n_u32, vqsubq_m_n_u16, vqsubq_m_s8, vqsubq_m_s32, vqsubq_m_s16, vqsubq_m_u8, vqsubq_m_u32, vqsubq_m_u16, vrhaddq_m_s8, vrhaddq_m_s32, vrhaddq_m_s16, vrhaddq_m_u8, vrhaddq_m_u32, vrhaddq_m_u16, vrmulhq_m_s8, vrmulhq_m_s32, vrmulhq_m_s16, vrmulhq_m_u8, vrmulhq_m_u32, vrmulhq_m_u16, vrshlq_m_s8, vrshlq_m_s32, vrshlq_m_s16, vrshlq_m_u8, vrshlq_m_u32, vrshlq_m_u16, vrshrq_m_n_s8, vrshrq_m_n_s32, vrshrq_m_n_s16, vrshrq_m_n_u8, vrshrq_m_n_u32, vrshrq_m_n_u16, vshlq_m_n_s8, vshlq_m_n_s32, vshlq_m_n_s16, vshlq_m_n_u8, vshlq_m_n_u32, vshlq_m_n_u16, vshrq_m_n_s8, vshrq_m_n_s32, vshrq_m_n_s16, vshrq_m_n_u8, vshrq_m_n_u32, vshrq_m_n_u16, vsliq_m_n_s8, vsliq_m_n_s32, vsliq_m_n_s16, vsliq_m_n_u8, vsliq_m_n_u32, vsliq_m_n_u16, vsubq_m_n_s8, vsubq_m_n_s32, vsubq_m_n_s16, vsubq_m_n_u8, vsubq_m_n_u32, vsubq_m_n_u16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vabdq_m_s8): Define macro. (vabdq_m_s32): Likewise. (vabdq_m_s16): Likewise. (vabdq_m_u8): Likewise. (vabdq_m_u32): Likewise. (vabdq_m_u16): Likewise. (vaddq_m_n_s8): Likewise. (vaddq_m_n_s32): Likewise. (vaddq_m_n_s16): Likewise. (vaddq_m_n_u8): Likewise. (vaddq_m_n_u32): Likewise. (vaddq_m_n_u16): Likewise. (vaddq_m_s8): Likewise. (vaddq_m_s32): Likewise. (vaddq_m_s16): Likewise. (vaddq_m_u8): Likewise. (vaddq_m_u32): Likewise. (vaddq_m_u16): Likewise. (vandq_m_s8): Likewise. (vandq_m_s32): Likewise. (vandq_m_s16): Likewise. (vandq_m_u8): Likewise. (vandq_m_u32): Likewise. (vandq_m_u16): Likewise. (vbicq_m_s8): Likewise. (vbicq_m_s32): Likewise. (vbicq_m_s16): Likewise. (vbicq_m_u8): Likewise. (vbicq_m_u32): Likewise. (vbicq_m_u16): Likewise. (vbrsrq_m_n_s8): Likewise. (vbrsrq_m_n_s32): Likewise. (vbrsrq_m_n_s16): Likewise. (vbrsrq_m_n_u8): Likewise. (vbrsrq_m_n_u32): Likewise. (vbrsrq_m_n_u16): Likewise. (vcaddq_rot270_m_s8): Likewise. (vcaddq_rot270_m_s32): Likewise. (vcaddq_rot270_m_s16): Likewise. (vcaddq_rot270_m_u8): Likewise. (vcaddq_rot270_m_u32): Likewise. (vcaddq_rot270_m_u16): Likewise. (vcaddq_rot90_m_s8): Likewise. (vcaddq_rot90_m_s32): Likewise. (vcaddq_rot90_m_s16): Likewise. (vcaddq_rot90_m_u8): Likewise. (vcaddq_rot90_m_u32): Likewise. (vcaddq_rot90_m_u16): Likewise. (veorq_m_s8): Likewise. (veorq_m_s32): Likewise. (veorq_m_s16): Likewise. (veorq_m_u8): Likewise. (veorq_m_u32): Likewise. (veorq_m_u16): Likewise. (vhaddq_m_n_s8): Likewise. (vhaddq_m_n_s32): Likewise. (vhaddq_m_n_s16): Likewise. (vhaddq_m_n_u8): Likewise. (vhaddq_m_n_u32): Likewise. (vhaddq_m_n_u16): Likewise. (vhaddq_m_s8): Likewise. (vhaddq_m_s32): Likewise. (vhaddq_m_s16): Likewise. (vhaddq_m_u8): Likewise. (vhaddq_m_u32): Likewise. (vhaddq_m_u16): Likewise. (vhcaddq_rot270_m_s8): Likewise. (vhcaddq_rot270_m_s32): Likewise. (vhcaddq_rot270_m_s16): Likewise. (vhcaddq_rot90_m_s8): Likewise. (vhcaddq_rot90_m_s32): Likewise. (vhcaddq_rot90_m_s16): Likewise. (vhsubq_m_n_s8): Likewise. (vhsubq_m_n_s32): Likewise. (vhsubq_m_n_s16): Likewise. (vhsubq_m_n_u8): Likewise. (vhsubq_m_n_u32): Likewise. (vhsubq_m_n_u16): Likewise. (vhsubq_m_s8): Likewise. (vhsubq_m_s32): Likewise. (vhsubq_m_s16): Likewise. (vhsubq_m_u8): Likewise. (vhsubq_m_u32): Likewise. (vhsubq_m_u16): Likewise. (vmaxq_m_s8): Likewise. (vmaxq_m_s32): Likewise. (vmaxq_m_s16): Likewise. (vmaxq_m_u8): Likewise. (vmaxq_m_u32): Likewise. (vmaxq_m_u16): Likewise. (vminq_m_s8): Likewise. (vminq_m_s32): Likewise. (vminq_m_s16): Likewise. (vminq_m_u8): Likewise. (vminq_m_u32): Likewise. (vminq_m_u16): Likewise. (vmladavaq_p_s8): Likewise. (vmladavaq_p_s32): Likewise. (vmladavaq_p_s16): Likewise. (vmladavaq_p_u8): Likewise. (vmladavaq_p_u32): Likewise. (vmladavaq_p_u16): Likewise. (vmladavaxq_p_s8): Likewise. (vmladavaxq_p_s32): Likewise. (vmladavaxq_p_s16): Likewise. (vmlaq_m_n_s8): Likewise. (vmlaq_m_n_s32): Likewise. (vmlaq_m_n_s16): Likewise. (vmlaq_m_n_u8): Likewise. (vmlaq_m_n_u32): Likewise. (vmlaq_m_n_u16): Likewise. (vmlasq_m_n_s8): Likewise. (vmlasq_m_n_s32): Likewise. (vmlasq_m_n_s16): Likewise. (vmlasq_m_n_u8): Likewise. (vmlasq_m_n_u32): Likewise. (vmlasq_m_n_u16): Likewise. (vmlsdavaq_p_s8): Likewise. (vmlsdavaq_p_s32): Likewise. (vmlsdavaq_p_s16): Likewise. (vmlsdavaxq_p_s8): Likewise. (vmlsdavaxq_p_s32): Likewise. (vmlsdavaxq_p_s16): Likewise. (vmulhq_m_s8): Likewise. (vmulhq_m_s32): Likewise. (vmulhq_m_s16): Likewise. (vmulhq_m_u8): Likewise. (vmulhq_m_u32): Likewise. (vmulhq_m_u16): Likewise. (vmullbq_int_m_s8): Likewise. (vmullbq_int_m_s32): Likewise. (vmullbq_int_m_s16): Likewise. (vmullbq_int_m_u8): Likewise. (vmullbq_int_m_u32): Likewise. (vmullbq_int_m_u16): Likewise. (vmulltq_int_m_s8): Likewise. (vmulltq_int_m_s32): Likewise. (vmulltq_int_m_s16): Likewise. (vmulltq_int_m_u8): Likewise. (vmulltq_int_m_u32): Likewise. (vmulltq_int_m_u16): Likewise. (vmulq_m_n_s8): Likewise. (vmulq_m_n_s32): Likewise. (vmulq_m_n_s16): Likewise. (vmulq_m_n_u8): Likewise. (vmulq_m_n_u32): Likewise. (vmulq_m_n_u16): Likewise. (vmulq_m_s8): Likewise. (vmulq_m_s32): Likewise. (vmulq_m_s16): Likewise. (vmulq_m_u8): Likewise. (vmulq_m_u32): Likewise. (vmulq_m_u16): Likewise. (vornq_m_s8): Likewise. (vornq_m_s32): Likewise. (vornq_m_s16): Likewise. (vornq_m_u8): Likewise. (vornq_m_u32): Likewise. (vornq_m_u16): Likewise. (vorrq_m_s8): Likewise. (vorrq_m_s32): Likewise. (vorrq_m_s16): Likewise. (vorrq_m_u8): Likewise. (vorrq_m_u32): Likewise. (vorrq_m_u16): Likewise. (vqaddq_m_n_s8): Likewise. (vqaddq_m_n_s32): Likewise. (vqaddq_m_n_s16): Likewise. (vqaddq_m_n_u8): Likewise. (vqaddq_m_n_u32): Likewise. (vqaddq_m_n_u16): Likewise. (vqaddq_m_s8): Likewise. (vqaddq_m_s32): Likewise. (vqaddq_m_s16): Likewise. (vqaddq_m_u8): Likewise. (vqaddq_m_u32): Likewise. (vqaddq_m_u16): Likewise. (vqdmladhq_m_s8): Likewise. (vqdmladhq_m_s32): Likewise. (vqdmladhq_m_s16): Likewise. (vqdmladhxq_m_s8): Likewise. (vqdmladhxq_m_s32): Likewise. (vqdmladhxq_m_s16): Likewise. (vqdmlahq_m_n_s8): Likewise. (vqdmlahq_m_n_s32): Likewise. (vqdmlahq_m_n_s16): Likewise. (vqdmlahq_m_n_u8): Likewise. (vqdmlahq_m_n_u32): Likewise. (vqdmlahq_m_n_u16): Likewise. (vqdmlsdhq_m_s8): Likewise. (vqdmlsdhq_m_s32): Likewise. (vqdmlsdhq_m_s16): Likewise. (vqdmlsdhxq_m_s8): Likewise. (vqdmlsdhxq_m_s32): Likewise. (vqdmlsdhxq_m_s16): Likewise. (vqdmulhq_m_n_s8): Likewise. (vqdmulhq_m_n_s32): Likewise. (vqdmulhq_m_n_s16): Likewise. (vqdmulhq_m_s8): Likewise. (vqdmulhq_m_s32): Likewise. (vqdmulhq_m_s16): Likewise. (vqrdmladhq_m_s8): Likewise. (vqrdmladhq_m_s32): Likewise. (vqrdmladhq_m_s16): Likewise. (vqrdmladhxq_m_s8): Likewise. (vqrdmladhxq_m_s32): Likewise. (vqrdmladhxq_m_s16): Likewise. (vqrdmlahq_m_n_s8): Likewise. (vqrdmlahq_m_n_s32): Likewise. (vqrdmlahq_m_n_s16): Likewise. (vqrdmlahq_m_n_u8): Likewise. (vqrdmlahq_m_n_u32): Likewise. (vqrdmlahq_m_n_u16): Likewise. (vqrdmlashq_m_n_s8): Likewise. (vqrdmlashq_m_n_s32): Likewise. (vqrdmlashq_m_n_s16): Likewise. (vqrdmlashq_m_n_u8): Likewise. (vqrdmlashq_m_n_u32): Likewise. (vqrdmlashq_m_n_u16): Likewise. (vqrdmlsdhq_m_s8): Likewise. (vqrdmlsdhq_m_s32): Likewise. (vqrdmlsdhq_m_s16): Likewise. (vqrdmlsdhxq_m_s8): Likewise. (vqrdmlsdhxq_m_s32): Likewise. (vqrdmlsdhxq_m_s16): Likewise. (vqrdmulhq_m_n_s8): Likewise. (vqrdmulhq_m_n_s32): Likewise. (vqrdmulhq_m_n_s16): Likewise. (vqrdmulhq_m_s8): Likewise. (vqrdmulhq_m_s32): Likewise. (vqrdmulhq_m_s16): Likewise. (vqrshlq_m_s8): Likewise. (vqrshlq_m_s32): Likewise. (vqrshlq_m_s16): Likewise. (vqrshlq_m_u8): Likewise. (vqrshlq_m_u32): Likewise. (vqrshlq_m_u16): Likewise. (vqshlq_m_n_s8): Likewise. (vqshlq_m_n_s32): Likewise. (vqshlq_m_n_s16): Likewise. (vqshlq_m_n_u8): Likewise. (vqshlq_m_n_u32): Likewise. (vqshlq_m_n_u16): Likewise. (vqshlq_m_s8): Likewise. (vqshlq_m_s32): Likewise. (vqshlq_m_s16): Likewise. (vqshlq_m_u8): Likewise. (vqshlq_m_u32): Likewise. (vqshlq_m_u16): Likewise. (vqsubq_m_n_s8): Likewise. (vqsubq_m_n_s32): Likewise. (vqsubq_m_n_s16): Likewise. (vqsubq_m_n_u8): Likewise. (vqsubq_m_n_u32): Likewise. (vqsubq_m_n_u16): Likewise. (vqsubq_m_s8): Likewise. (vqsubq_m_s32): Likewise. (vqsubq_m_s16): Likewise. (vqsubq_m_u8): Likewise. (vqsubq_m_u32): Likewise. (vqsubq_m_u16): Likewise. (vrhaddq_m_s8): Likewise. (vrhaddq_m_s32): Likewise. (vrhaddq_m_s16): Likewise. (vrhaddq_m_u8): Likewise. (vrhaddq_m_u32): Likewise. (vrhaddq_m_u16): Likewise. (vrmulhq_m_s8): Likewise. (vrmulhq_m_s32): Likewise. (vrmulhq_m_s16): Likewise. (vrmulhq_m_u8): Likewise. (vrmulhq_m_u32): Likewise. (vrmulhq_m_u16): Likewise. (vrshlq_m_s8): Likewise. (vrshlq_m_s32): Likewise. (vrshlq_m_s16): Likewise. (vrshlq_m_u8): Likewise. (vrshlq_m_u32): Likewise. (vrshlq_m_u16): Likewise. (vrshrq_m_n_s8): Likewise. (vrshrq_m_n_s32): Likewise. (vrshrq_m_n_s16): Likewise. (vrshrq_m_n_u8): Likewise. (vrshrq_m_n_u32): Likewise. (vrshrq_m_n_u16): Likewise. (vshlq_m_n_s8): Likewise. (vshlq_m_n_s32): Likewise. (vshlq_m_n_s16): Likewise. (vshlq_m_n_u8): Likewise. (vshlq_m_n_u32): Likewise. (vshlq_m_n_u16): Likewise. (vshrq_m_n_s8): Likewise. (vshrq_m_n_s32): Likewise. (vshrq_m_n_s16): Likewise. (vshrq_m_n_u8): Likewise. (vshrq_m_n_u32): Likewise. (vshrq_m_n_u16): Likewise. (vsliq_m_n_s8): Likewise. (vsliq_m_n_s32): Likewise. (vsliq_m_n_s16): Likewise. (vsliq_m_n_u8): Likewise. (vsliq_m_n_u32): Likewise. (vsliq_m_n_u16): Likewise. (vsubq_m_n_s8): Likewise. (vsubq_m_n_s32): Likewise. (vsubq_m_n_s16): Likewise. (vsubq_m_n_u8): Likewise. (vsubq_m_n_u32): Likewise. (vsubq_m_n_u16): Likewise. (__arm_vabdq_m_s8): Define intrinsic. (__arm_vabdq_m_s32): Likewise. (__arm_vabdq_m_s16): Likewise. (__arm_vabdq_m_u8): Likewise. (__arm_vabdq_m_u32): Likewise. (__arm_vabdq_m_u16): Likewise. (__arm_vaddq_m_n_s8): Likewise. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m_s8): Likewise. (__arm_vaddq_m_s32): Likewise. (__arm_vaddq_m_s16): Likewise. (__arm_vaddq_m_u8): Likewise. (__arm_vaddq_m_u32): Likewise. (__arm_vaddq_m_u16): Likewise. (__arm_vandq_m_s8): Likewise. (__arm_vandq_m_s32): Likewise. (__arm_vandq_m_s16): Likewise. (__arm_vandq_m_u8): Likewise. (__arm_vandq_m_u32): Likewise. (__arm_vandq_m_u16): Likewise. (__arm_vbicq_m_s8): Likewise. (__arm_vbicq_m_s32): Likewise. (__arm_vbicq_m_s16): Likewise. (__arm_vbicq_m_u8): Likewise. (__arm_vbicq_m_u32): Likewise. (__arm_vbicq_m_u16): Likewise. (__arm_vbrsrq_m_n_s8): Likewise. (__arm_vbrsrq_m_n_s32): Likewise. (__arm_vbrsrq_m_n_s16): Likewise. (__arm_vbrsrq_m_n_u8): Likewise. (__arm_vbrsrq_m_n_u32): Likewise. (__arm_vbrsrq_m_n_u16): Likewise. (__arm_vcaddq_rot270_m_s8): Likewise. (__arm_vcaddq_rot270_m_s32): Likewise. (__arm_vcaddq_rot270_m_s16): Likewise. (__arm_vcaddq_rot270_m_u8): Likewise. (__arm_vcaddq_rot270_m_u32): Likewise. (__arm_vcaddq_rot270_m_u16): Likewise. (__arm_vcaddq_rot90_m_s8): Likewise. (__arm_vcaddq_rot90_m_s32): Likewise. (__arm_vcaddq_rot90_m_s16): Likewise. (__arm_vcaddq_rot90_m_u8): Likewise. (__arm_vcaddq_rot90_m_u32): Likewise. (__arm_vcaddq_rot90_m_u16): Likewise. (__arm_veorq_m_s8): Likewise. (__arm_veorq_m_s32): Likewise. (__arm_veorq_m_s16): Likewise. (__arm_veorq_m_u8): Likewise. (__arm_veorq_m_u32): Likewise. (__arm_veorq_m_u16): Likewise. (__arm_vhaddq_m_n_s8): Likewise. (__arm_vhaddq_m_n_s32): Likewise. (__arm_vhaddq_m_n_s16): Likewise. (__arm_vhaddq_m_n_u8): Likewise. (__arm_vhaddq_m_n_u32): Likewise. (__arm_vhaddq_m_n_u16): Likewise. (__arm_vhaddq_m_s8): Likewise. (__arm_vhaddq_m_s32): Likewise. (__arm_vhaddq_m_s16): Likewise. (__arm_vhaddq_m_u8): Likewise. (__arm_vhaddq_m_u32): Likewise. (__arm_vhaddq_m_u16): Likewise. (__arm_vhcaddq_rot270_m_s8): Likewise. (__arm_vhcaddq_rot270_m_s32): Likewise. (__arm_vhcaddq_rot270_m_s16): Likewise. (__arm_vhcaddq_rot90_m_s8): Likewise. (__arm_vhcaddq_rot90_m_s32): Likewise. (__arm_vhcaddq_rot90_m_s16): Likewise. (__arm_vhsubq_m_n_s8): Likewise. (__arm_vhsubq_m_n_s32): Likewise. (__arm_vhsubq_m_n_s16): Likewise. (__arm_vhsubq_m_n_u8): Likewise. (__arm_vhsubq_m_n_u32): Likewise. (__arm_vhsubq_m_n_u16): Likewise. (__arm_vhsubq_m_s8): Likewise. (__arm_vhsubq_m_s32): Likewise. (__arm_vhsubq_m_s16): Likewise. (__arm_vhsubq_m_u8): Likewise. (__arm_vhsubq_m_u32): Likewise. (__arm_vhsubq_m_u16): Likewise. (__arm_vmaxq_m_s8): Likewise. (__arm_vmaxq_m_s32): Likewise. (__arm_vmaxq_m_s16): Likewise. (__arm_vmaxq_m_u8): Likewise. (__arm_vmaxq_m_u32): Likewise. (__arm_vmaxq_m_u16): Likewise. (__arm_vminq_m_s8): Likewise. (__arm_vminq_m_s32): Likewise. (__arm_vminq_m_s16): Likewise. (__arm_vminq_m_u8): Likewise. (__arm_vminq_m_u32): Likewise. (__arm_vminq_m_u16): Likewise. (__arm_vmladavaq_p_s8): Likewise. (__arm_vmladavaq_p_s32): Likewise. (__arm_vmladavaq_p_s16): Likewise. (__arm_vmladavaq_p_u8): Likewise. (__arm_vmladavaq_p_u32): Likewise. (__arm_vmladavaq_p_u16): Likewise. (__arm_vmladavaxq_p_s8): Likewise. (__arm_vmladavaxq_p_s32): Likewise. (__arm_vmladavaxq_p_s16): Likewise. (__arm_vmlaq_m_n_s8): Likewise. (__arm_vmlaq_m_n_s32): Likewise. (__arm_vmlaq_m_n_s16): Likewise. (__arm_vmlaq_m_n_u8): Likewise. (__arm_vmlaq_m_n_u32): Likewise. (__arm_vmlaq_m_n_u16): Likewise. (__arm_vmlasq_m_n_s8): Likewise. (__arm_vmlasq_m_n_s32): Likewise. (__arm_vmlasq_m_n_s16): Likewise. (__arm_vmlasq_m_n_u8): Likewise. (__arm_vmlasq_m_n_u32): Likewise. (__arm_vmlasq_m_n_u16): Likewise. (__arm_vmlsdavaq_p_s8): Likewise. (__arm_vmlsdavaq_p_s32): Likewise. (__arm_vmlsdavaq_p_s16): Likewise. (__arm_vmlsdavaxq_p_s8): Likewise. (__arm_vmlsdavaxq_p_s32): Likewise. (__arm_vmlsdavaxq_p_s16): Likewise. (__arm_vmulhq_m_s8): Likewise. (__arm_vmulhq_m_s32): Likewise. (__arm_vmulhq_m_s16): Likewise. (__arm_vmulhq_m_u8): Likewise. (__arm_vmulhq_m_u32): Likewise. (__arm_vmulhq_m_u16): Likewise. (__arm_vmullbq_int_m_s8): Likewise. (__arm_vmullbq_int_m_s32): Likewise. (__arm_vmullbq_int_m_s16): Likewise. (__arm_vmullbq_int_m_u8): Likewise. (__arm_vmullbq_int_m_u32): Likewise. (__arm_vmullbq_int_m_u16): Likewise. (__arm_vmulltq_int_m_s8): Likewise. (__arm_vmulltq_int_m_s32): Likewise. (__arm_vmulltq_int_m_s16): Likewise. (__arm_vmulltq_int_m_u8): Likewise. (__arm_vmulltq_int_m_u32): Likewise. (__arm_vmulltq_int_m_u16): Likewise. (__arm_vmulq_m_n_s8): Likewise. (__arm_vmulq_m_n_s32): Likewise. (__arm_vmulq_m_n_s16): Likewise. (__arm_vmulq_m_n_u8): Likewise. (__arm_vmulq_m_n_u32): Likewise. (__arm_vmulq_m_n_u16): Likewise. (__arm_vmulq_m_s8): Likewise. (__arm_vmulq_m_s32): Likewise. (__arm_vmulq_m_s16): Likewise. (__arm_vmulq_m_u8): Likewise. (__arm_vmulq_m_u32): Likewise. (__arm_vmulq_m_u16): Likewise. (__arm_vornq_m_s8): Likewise. (__arm_vornq_m_s32): Likewise. (__arm_vornq_m_s16): Likewise. (__arm_vornq_m_u8): Likewise. (__arm_vornq_m_u32): Likewise. (__arm_vornq_m_u16): Likewise. (__arm_vorrq_m_s8): Likewise. (__arm_vorrq_m_s32): Likewise. (__arm_vorrq_m_s16): Likewise. (__arm_vorrq_m_u8): Likewise. (__arm_vorrq_m_u32): Likewise. (__arm_vorrq_m_u16): Likewise. (__arm_vqaddq_m_n_s8): Likewise. (__arm_vqaddq_m_n_s32): Likewise. (__arm_vqaddq_m_n_s16): Likewise. (__arm_vqaddq_m_n_u8): Likewise. (__arm_vqaddq_m_n_u32): Likewise. (__arm_vqaddq_m_n_u16): Likewise. (__arm_vqaddq_m_s8): Likewise. (__arm_vqaddq_m_s32): Likewise. (__arm_vqaddq_m_s16): Likewise. (__arm_vqaddq_m_u8): Likewise. (__arm_vqaddq_m_u32): Likewise. (__arm_vqaddq_m_u16): Likewise. (__arm_vqdmladhq_m_s8): Likewise. (__arm_vqdmladhq_m_s32): Likewise. (__arm_vqdmladhq_m_s16): Likewise. (__arm_vqdmladhxq_m_s8): Likewise. (__arm_vqdmladhxq_m_s32): Likewise. (__arm_vqdmladhxq_m_s16): Likewise. (__arm_vqdmlahq_m_n_s8): Likewise. (__arm_vqdmlahq_m_n_s32): Likewise. (__arm_vqdmlahq_m_n_s16): Likewise. (__arm_vqdmlahq_m_n_u8): Likewise. (__arm_vqdmlahq_m_n_u32): Likewise. (__arm_vqdmlahq_m_n_u16): Likewise. (__arm_vqdmlsdhq_m_s8): Likewise. (__arm_vqdmlsdhq_m_s32): Likewise. (__arm_vqdmlsdhq_m_s16): Likewise. (__arm_vqdmlsdhxq_m_s8): Likewise. (__arm_vqdmlsdhxq_m_s32): Likewise. (__arm_vqdmlsdhxq_m_s16): Likewise. (__arm_vqdmulhq_m_n_s8): Likewise. (__arm_vqdmulhq_m_n_s32): Likewise. (__arm_vqdmulhq_m_n_s16): Likewise. (__arm_vqdmulhq_m_s8): Likewise. (__arm_vqdmulhq_m_s32): Likewise. (__arm_vqdmulhq_m_s16): Likewise. (__arm_vqrdmladhq_m_s8): Likewise. (__arm_vqrdmladhq_m_s32): Likewise. (__arm_vqrdmladhq_m_s16): Likewise. (__arm_vqrdmladhxq_m_s8): Likewise. (__arm_vqrdmladhxq_m_s32): Likewise. (__arm_vqrdmladhxq_m_s16): Likewise. (__arm_vqrdmlahq_m_n_s8): Likewise. (__arm_vqrdmlahq_m_n_s32): Likewise. (__arm_vqrdmlahq_m_n_s16): Likewise. (__arm_vqrdmlahq_m_n_u8): Likewise. (__arm_vqrdmlahq_m_n_u32): Likewise. (__arm_vqrdmlahq_m_n_u16): Likewise. (__arm_vqrdmlashq_m_n_s8): Likewise. (__arm_vqrdmlashq_m_n_s32): Likewise. (__arm_vqrdmlashq_m_n_s16): Likewise. (__arm_vqrdmlashq_m_n_u8): Likewise. (__arm_vqrdmlashq_m_n_u32): Likewise. (__arm_vqrdmlashq_m_n_u16): Likewise. (__arm_vqrdmlsdhq_m_s8): Likewise. (__arm_vqrdmlsdhq_m_s32): Likewise. (__arm_vqrdmlsdhq_m_s16): Likewise. (__arm_vqrdmlsdhxq_m_s8): Likewise. (__arm_vqrdmlsdhxq_m_s32): Likewise. (__arm_vqrdmlsdhxq_m_s16): Likewise. (__arm_vqrdmulhq_m_n_s8): Likewise. (__arm_vqrdmulhq_m_n_s32): Likewise. (__arm_vqrdmulhq_m_n_s16): Likewise. (__arm_vqrdmulhq_m_s8): Likewise. (__arm_vqrdmulhq_m_s32): Likewise. (__arm_vqrdmulhq_m_s16): Likewise. (__arm_vqrshlq_m_s8): Likewise. (__arm_vqrshlq_m_s32): Likewise. (__arm_vqrshlq_m_s16): Likewise. (__arm_vqrshlq_m_u8): Likewise. (__arm_vqrshlq_m_u32): Likewise. (__arm_vqrshlq_m_u16): Likewise. (__arm_vqshlq_m_n_s8): Likewise. (__arm_vqshlq_m_n_s32): Likewise. (__arm_vqshlq_m_n_s16): Likewise. (__arm_vqshlq_m_n_u8): Likewise. (__arm_vqshlq_m_n_u32): Likewise. (__arm_vqshlq_m_n_u16): Likewise. (__arm_vqshlq_m_s8): Likewise. (__arm_vqshlq_m_s32): Likewise. (__arm_vqshlq_m_s16): Likewise. (__arm_vqshlq_m_u8): Likewise. (__arm_vqshlq_m_u32): Likewise. (__arm_vqshlq_m_u16): Likewise. (__arm_vqsubq_m_n_s8): Likewise. (__arm_vqsubq_m_n_s32): Likewise. (__arm_vqsubq_m_n_s16): Likewise. (__arm_vqsubq_m_n_u8): Likewise. (__arm_vqsubq_m_n_u32): Likewise. (__arm_vqsubq_m_n_u16): Likewise. (__arm_vqsubq_m_s8): Likewise. (__arm_vqsubq_m_s32): Likewise. (__arm_vqsubq_m_s16): Likewise. (__arm_vqsubq_m_u8): Likewise. (__arm_vqsubq_m_u32): Likewise. (__arm_vqsubq_m_u16): Likewise. (__arm_vrhaddq_m_s8): Likewise. (__arm_vrhaddq_m_s32): Likewise. (__arm_vrhaddq_m_s16): Likewise. (__arm_vrhaddq_m_u8): Likewise. (__arm_vrhaddq_m_u32): Likewise. (__arm_vrhaddq_m_u16): Likewise. (__arm_vrmulhq_m_s8): Likewise. (__arm_vrmulhq_m_s32): Likewise. (__arm_vrmulhq_m_s16): Likewise. (__arm_vrmulhq_m_u8): Likewise. (__arm_vrmulhq_m_u32): Likewise. (__arm_vrmulhq_m_u16): Likewise. (__arm_vrshlq_m_s8): Likewise. (__arm_vrshlq_m_s32): Likewise. (__arm_vrshlq_m_s16): Likewise. (__arm_vrshlq_m_u8): Likewise. (__arm_vrshlq_m_u32): Likewise. (__arm_vrshlq_m_u16): Likewise. (__arm_vrshrq_m_n_s8): Likewise. (__arm_vrshrq_m_n_s32): Likewise. (__arm_vrshrq_m_n_s16): Likewise. (__arm_vrshrq_m_n_u8): Likewise. (__arm_vrshrq_m_n_u32): Likewise. (__arm_vrshrq_m_n_u16): Likewise. (__arm_vshlq_m_n_s8): Likewise. (__arm_vshlq_m_n_s32): Likewise. (__arm_vshlq_m_n_s16): Likewise. (__arm_vshlq_m_n_u8): Likewise. (__arm_vshlq_m_n_u32): Likewise. (__arm_vshlq_m_n_u16): Likewise. (__arm_vshrq_m_n_s8): Likewise. (__arm_vshrq_m_n_s32): Likewise. (__arm_vshrq_m_n_s16): Likewise. (__arm_vshrq_m_n_u8): Likewise. (__arm_vshrq_m_n_u32): Likewise. (__arm_vshrq_m_n_u16): Likewise. (__arm_vsliq_m_n_s8): Likewise. (__arm_vsliq_m_n_s32): Likewise. (__arm_vsliq_m_n_s16): Likewise. (__arm_vsliq_m_n_u8): Likewise. (__arm_vsliq_m_n_u32): Likewise. (__arm_vsliq_m_n_u16): Likewise. (__arm_vsubq_m_n_s8): Likewise. (__arm_vsubq_m_n_s32): Likewise. (__arm_vsubq_m_n_s16): Likewise. (__arm_vsubq_m_n_u8): Likewise. (__arm_vsubq_m_n_u32): Likewise. (__arm_vsubq_m_n_u16): Likewise. (vqdmladhq_m): Define polymorphic variant. (vqdmladhxq_m): Likewise. (vqdmlsdhq_m): Likewise. (vqdmlsdhxq_m): Likewise. (vabdq_m): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (veorq_m): Likewise. (vmaxq_m): Likewise. (vminq_m): Likewise. (vmladavaq_p): Likewise. (vmlaq_m_n): Likewise. (vmlasq_m_n): Likewise. (vmulhq_m): Likewise. (vmullbq_int_m): Likewise. (vmulltq_int_m): Likewise. (vornq_m): Likewise. (vorrq_m): Likewise. (vqdmlahq_m_n): Likewise. (vqrdmlahq_m_n): Likewise. (vqrdmlashq_m_n): Likewise. (vqrshlq_m): Likewise. (vqshlq_m_n): Likewise. (vqshlq_m): Likewise. (vrhaddq_m): Likewise. (vrmulhq_m): Likewise. (vrshlq_m): Likewise. (vrshrq_m_n): Likewise. (vshlq_m_n): Likewise. (vshrq_m_n): Likewise. (vsliq_m): Likewise. (vaddq_m_n): Likewise. (vaddq_m): Likewise. (vhaddq_m_n): Likewise. (vhaddq_m): Likewise. (vhcaddq_rot270_m): Likewise. (vhcaddq_rot90_m): Likewise. (vhsubq_m): Likewise. (vhsubq_m_n): Likewise. (vmulq_m_n): Likewise. (vmulq_m): Likewise. (vqaddq_m_n): Likewise. (vqaddq_m): Likewise. (vqdmulhq_m_n): Likewise. (vqdmulhq_m): Likewise. (vsubq_m_n): Likewise. (vsliq_m_n): Likewise. (vqsubq_m_n): Likewise. (vqsubq_m): Likewise. (vqrdmulhq_m): Likewise. (vqrdmulhq_m_n): Likewise. (vqrdmlsdhxq_m): Likewise. (vqrdmlsdhq_m): Likewise. (vqrdmladhq_m): Likewise. (vqrdmladhxq_m): Likewise. (vmlsdavaxq_p): Likewise. (vmlsdavaq_p): Likewise. (vmladavaxq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VHSUBQ_M): Define iterators. (VSLIQ_M_N): Likewise. (VQRDMLAHQ_M_N): Likewise. (VRSHLQ_M): Likewise. (VMINQ_M): Likewise. (VMULLBQ_INT_M): Likewise. (VMULHQ_M): Likewise. (VMULQ_M): Likewise. (VHSUBQ_M_N): Likewise. (VHADDQ_M_N): Likewise. (VORRQ_M): Likewise. (VRMULHQ_M): Likewise. (VQADDQ_M): Likewise. (VRSHRQ_M_N): Likewise. (VQSUBQ_M_N): Likewise. (VADDQ_M): Likewise. (VORNQ_M): Likewise. (VQDMLAHQ_M_N): Likewise. (VRHADDQ_M): Likewise. (VQSHLQ_M): Likewise. (VANDQ_M): Likewise. (VBICQ_M): Likewise. (VSHLQ_M_N): Likewise. (VCADDQ_ROT270_M): Likewise. (VQRSHLQ_M): Likewise. (VQADDQ_M_N): Likewise. (VADDQ_M_N): Likewise. (VMAXQ_M): Likewise. (VQSUBQ_M): Likewise. (VMLASQ_M_N): Likewise. (VMLADAVAQ_P): Likewise. (VBRSRQ_M_N): Likewise. (VMULQ_M_N): Likewise. (VCADDQ_ROT90_M): Likewise. (VMULLTQ_INT_M): Likewise. (VEORQ_M): Likewise. (VSHRQ_M_N): Likewise. (VSUBQ_M_N): Likewise. (VHADDQ_M): Likewise. (VABDQ_M): Likewise. (VQRDMLASHQ_M_N): Likewise. (VMLAQ_M_N): Likewise. (VQSHLQ_M_N): Likewise. (mve_vabdq_m_<supf><mode>): Define RTL pattern. (mve_vaddq_m_n_<supf><mode>): Likewise. (mve_vaddq_m_<supf><mode>): Likewise. (mve_vandq_m_<supf><mode>): Likewise. (mve_vbicq_m_<supf><mode>): Likewise. (mve_vbrsrq_m_n_<supf><mode>): Likewise. (mve_vcaddq_rot270_m_<supf><mode>): Likewise. (mve_vcaddq_rot90_m_<supf><mode>): Likewise. (mve_veorq_m_<supf><mode>): Likewise. (mve_vhaddq_m_n_<supf><mode>): Likewise. (mve_vhaddq_m_<supf><mode>): Likewise. (mve_vhsubq_m_n_<supf><mode>): Likewise. (mve_vhsubq_m_<supf><mode>): Likewise. (mve_vmaxq_m_<supf><mode>): Likewise. (mve_vminq_m_<supf><mode>): Likewise. (mve_vmladavaq_p_<supf><mode>): Likewise. (mve_vmlaq_m_n_<supf><mode>): Likewise. (mve_vmlasq_m_n_<supf><mode>): Likewise. (mve_vmulhq_m_<supf><mode>): Likewise. (mve_vmullbq_int_m_<supf><mode>): Likewise. (mve_vmulltq_int_m_<supf><mode>): Likewise. (mve_vmulq_m_n_<supf><mode>): Likewise. (mve_vmulq_m_<supf><mode>): Likewise. (mve_vornq_m_<supf><mode>): Likewise. (mve_vorrq_m_<supf><mode>): Likewise. (mve_vqaddq_m_n_<supf><mode>): Likewise. (mve_vqaddq_m_<supf><mode>): Likewise. (mve_vqdmlahq_m_n_<supf><mode>): Likewise. (mve_vqrdmlahq_m_n_<supf><mode>): Likewise. (mve_vqrdmlashq_m_n_<supf><mode>): Likewise. (mve_vqrshlq_m_<supf><mode>): Likewise. (mve_vqshlq_m_n_<supf><mode>): Likewise. (mve_vqshlq_m_<supf><mode>): Likewise. (mve_vqsubq_m_n_<supf><mode>): Likewise. (mve_vqsubq_m_<supf><mode>): Likewise. (mve_vrhaddq_m_<supf><mode>): Likewise. (mve_vrmulhq_m_<supf><mode>): Likewise. (mve_vrshlq_m_<supf><mode>): Likewise. (mve_vrshrq_m_n_<supf><mode>): Likewise. (mve_vshlq_m_n_<supf><mode>): Likewise. (mve_vshrq_m_n_<supf><mode>): Likewise. (mve_vsliq_m_n_<supf><mode>): Likewise. (mve_vsubq_m_n_<supf><mode>): Likewise. (mve_vhcaddq_rot270_m_s<mode>): Likewise. (mve_vhcaddq_rot90_m_s<mode>): Likewise. (mve_vmladavaxq_p_s<mode>): Likewise. (mve_vmlsdavaq_p_s<mode>): Likewise. (mve_vmlsdavaxq_p_s<mode>): Likewise. (mve_vqdmladhq_m_s<mode>): Likewise. (mve_vqdmladhxq_m_s<mode>): Likewise. (mve_vqdmlsdhq_m_s<mode>): Likewise. (mve_vqdmlsdhxq_m_s<mode>): Likewise. (mve_vqdmulhq_m_n_s<mode>): Likewise. (mve_vqdmulhq_m_s<mode>): Likewise. (mve_vqrdmladhq_m_s<mode>): Likewise. (mve_vqrdmladhxq_m_s<mode>): Likewise. (mve_vqrdmlsdhq_m_s<mode>): Likewise. (mve_vqrdmlsdhxq_m_s<mode>): Likewise. (mve_vqrdmulhq_m_n_s<mode>): Likewise. (mve_vqrdmulhq_m_s<mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vandq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbicq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/veorq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vornq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. |
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Srinath Parvathaneni
|
db5db9d254 |
[ARM][GCC][1/4x]: MVE intrinsics with quaternary operands.
This patch supports following MVE ACLE intrinsics with quaternary operands. vsriq_m_n_s8, vsubq_m_s8, vsubq_x_s8, vcvtq_m_n_f16_u16, vcvtq_x_n_f16_u16, vqshluq_m_n_s8, vabavq_p_s8, vsriq_m_n_u8, vshlq_m_u8, vshlq_x_u8, vsubq_m_u8, vsubq_x_u8, vabavq_p_u8, vshlq_m_s8, vshlq_x_s8, vcvtq_m_n_f16_s16, vcvtq_x_n_f16_s16, vsriq_m_n_s16, vsubq_m_s16, vsubq_x_s16, vcvtq_m_n_f32_u32, vcvtq_x_n_f32_u32, vqshluq_m_n_s16, vabavq_p_s16, vsriq_m_n_u16, vshlq_m_u16, vshlq_x_u16, vsubq_m_u16, vsubq_x_u16, vabavq_p_u16, vshlq_m_s16, vshlq_x_s16, vcvtq_m_n_f32_s32, vcvtq_x_n_f32_s32, vsriq_m_n_s32, vsubq_m_s32, vsubq_x_s32, vqshluq_m_n_s32, vabavq_p_s32, vsriq_m_n_u32, vshlq_m_u32, vshlq_x_u32, vsubq_m_u32, vsubq_x_u32, vabavq_p_u32, vshlq_m_s32, vshlq_x_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Define builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. (vsubq_m_s8): Likewise. (vcvtq_m_n_f16_u16): Likewise. (vqshluq_m_n_s8): Likewise. (vabavq_p_s8): Likewise. (vsriq_m_n_u8): Likewise. (vshlq_m_u8): Likewise. (vsubq_m_u8): Likewise. (vabavq_p_u8): Likewise. (vshlq_m_s8): Likewise. (vcvtq_m_n_f16_s16): Likewise. (vsriq_m_n_s16): Likewise. (vsubq_m_s16): Likewise. (vcvtq_m_n_f32_u32): Likewise. (vqshluq_m_n_s16): Likewise. (vabavq_p_s16): Likewise. (vsriq_m_n_u16): Likewise. (vshlq_m_u16): Likewise. (vsubq_m_u16): Likewise. (vabavq_p_u16): Likewise. (vshlq_m_s16): Likewise. (vcvtq_m_n_f32_s32): Likewise. (vsriq_m_n_s32): Likewise. (vsubq_m_s32): Likewise. (vqshluq_m_n_s32): Likewise. (vabavq_p_s32): Likewise. (vsriq_m_n_u32): Likewise. (vshlq_m_u32): Likewise. (vsubq_m_u32): Likewise. (vabavq_p_u32): Likewise. (vshlq_m_s32): Likewise. (__arm_vsriq_m_n_s8): Define intrinsic. (__arm_vsubq_m_s8): Likewise. (__arm_vqshluq_m_n_s8): Likewise. (__arm_vabavq_p_s8): Likewise. (__arm_vsriq_m_n_u8): Likewise. (__arm_vshlq_m_u8): Likewise. (__arm_vsubq_m_u8): Likewise. (__arm_vabavq_p_u8): Likewise. (__arm_vshlq_m_s8): Likewise. (__arm_vsriq_m_n_s16): Likewise. (__arm_vsubq_m_s16): Likewise. (__arm_vqshluq_m_n_s16): Likewise. (__arm_vabavq_p_s16): Likewise. (__arm_vsriq_m_n_u16): Likewise. (__arm_vshlq_m_u16): Likewise. (__arm_vsubq_m_u16): Likewise. (__arm_vabavq_p_u16): Likewise. (__arm_vshlq_m_s16): Likewise. (__arm_vsriq_m_n_s32): Likewise. (__arm_vsubq_m_s32): Likewise. (__arm_vqshluq_m_n_s32): Likewise. (__arm_vabavq_p_s32): Likewise. (__arm_vsriq_m_n_u32): Likewise. (__arm_vshlq_m_u32): Likewise. (__arm_vsubq_m_u32): Likewise. (__arm_vabavq_p_u32): Likewise. (__arm_vshlq_m_s32): Likewise. (__arm_vcvtq_m_n_f16_u16): Likewise. (__arm_vcvtq_m_n_f16_s16): Likewise. (__arm_vcvtq_m_n_f32_u32): Likewise. (__arm_vcvtq_m_n_f32_s32): Likewise. (vcvtq_m_n): Define polymorphic variant. (vqshluq_m_n): Likewise. (vshlq_m): Likewise. (vsriq_m_n): Likewise. (vsubq_m): Likewise. (vabavq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/mve.md (VABAVQ_P): Define iterator. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (mve_vabavq_p_<supf><mode>): Define RTL pattern. (mve_vqshluq_m_n_s<mode>): Likewise. (mve_vshlq_m_<supf><mode>): Likewise. (mve_vsriq_m_n_<supf><mode>): Likewise. (mve_vsubq_m_<supf><mode>): Likewise. (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. |
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Srinath Parvathaneni
|
e3678b4464 |
[ARM][GCC][3/3x]: MVE intrinsics with ternary operands.
This patch supports following MVE ACLE intrinsics with ternary operands. vrmlaldavhaxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vaddlvaq_p_s32, vcvtbq_m_f16_f32, vcvtbq_m_f32_f16, vcvttq_m_f16_f32, vcvttq_m_f32_f16, vrev16q_m_s8, vrev32q_m_f16, vrmlaldavhq_p_s32, vrmlaldavhxq_p_s32, vrmlsldavhq_p_s32, vrmlsldavhxq_p_s32, vaddlvaq_p_u32, vrev16q_m_u8, vrmlaldavhq_p_u32, vmvnq_m_n_s16, vorrq_m_n_s16, vqrshrntq_n_s16, vqshrnbq_n_s16, vqshrntq_n_s16, vrshrnbq_n_s16, vrshrntq_n_s16, vshrnbq_n_s16, vshrntq_n_s16, vcmlaq_f16, vcmlaq_rot180_f16, vcmlaq_rot270_f16, vcmlaq_rot90_f16, vfmaq_f16, vfmaq_n_f16, vfmasq_n_f16, vfmsq_f16, vmlaldavaq_s16, vmlaldavaxq_s16, vmlsldavaq_s16, vmlsldavaxq_s16, vabsq_m_f16, vcvtmq_m_s16_f16, vcvtnq_m_s16_f16, vcvtpq_m_s16_f16, vcvtq_m_s16_f16, vdupq_m_n_f16, vmaxnmaq_m_f16, vmaxnmavq_p_f16, vmaxnmvq_p_f16, vminnmaq_m_f16, vminnmavq_p_f16, vminnmvq_p_f16, vmlaldavq_p_s16, vmlaldavxq_p_s16, vmlsldavq_p_s16, vmlsldavxq_p_s16, vmovlbq_m_s8, vmovltq_m_s8, vmovnbq_m_s16, vmovntq_m_s16, vnegq_m_f16, vpselq_f16, vqmovnbq_m_s16, vqmovntq_m_s16, vrev32q_m_s8, vrev64q_m_f16, vrndaq_m_f16, vrndmq_m_f16, vrndnq_m_f16, vrndpq_m_f16, vrndq_m_f16, vrndxq_m_f16, vcmpeqq_m_n_f16, vcmpgeq_m_f16, vcmpgeq_m_n_f16, vcmpgtq_m_f16, vcmpgtq_m_n_f16, vcmpleq_m_f16, vcmpleq_m_n_f16, vcmpltq_m_f16, vcmpltq_m_n_f16, vcmpneq_m_f16, vcmpneq_m_n_f16, vmvnq_m_n_u16, vorrq_m_n_u16, vqrshruntq_n_s16, vqshrunbq_n_s16, vqshruntq_n_s16, vcvtmq_m_u16_f16, vcvtnq_m_u16_f16, vcvtpq_m_u16_f16, vcvtq_m_u16_f16, vqmovunbq_m_s16, vqmovuntq_m_s16, vqrshrntq_n_u16, vqshrnbq_n_u16, vqshrntq_n_u16, vrshrnbq_n_u16, vrshrntq_n_u16, vshrnbq_n_u16, vshrntq_n_u16, vmlaldavaq_u16, vmlaldavaxq_u16, vmlaldavq_p_u16, vmlaldavxq_p_u16, vmovlbq_m_u8, vmovltq_m_u8, vmovnbq_m_u16, vmovntq_m_u16, vqmovnbq_m_u16, vqmovntq_m_u16, vrev32q_m_u8, vmvnq_m_n_s32, vorrq_m_n_s32, vqrshrntq_n_s32, vqshrnbq_n_s32, vqshrntq_n_s32, vrshrnbq_n_s32, vrshrntq_n_s32, vshrnbq_n_s32, vshrntq_n_s32, vcmlaq_f32, vcmlaq_rot180_f32, vcmlaq_rot270_f32, vcmlaq_rot90_f32, vfmaq_f32, vfmaq_n_f32, vfmasq_n_f32, vfmsq_f32, vmlaldavaq_s32, vmlaldavaxq_s32, vmlsldavaq_s32, vmlsldavaxq_s32, vabsq_m_f32, vcvtmq_m_s32_f32, vcvtnq_m_s32_f32, vcvtpq_m_s32_f32, vcvtq_m_s32_f32, vdupq_m_n_f32, vmaxnmaq_m_f32, vmaxnmavq_p_f32, vmaxnmvq_p_f32, vminnmaq_m_f32, vminnmavq_p_f32, vminnmvq_p_f32, vmlaldavq_p_s32, vmlaldavxq_p_s32, vmlsldavq_p_s32, vmlsldavxq_p_s32, vmovlbq_m_s16, vmovltq_m_s16, vmovnbq_m_s32, vmovntq_m_s32, vnegq_m_f32, vpselq_f32, vqmovnbq_m_s32, vqmovntq_m_s32, vrev32q_m_s16, vrev64q_m_f32, vrndaq_m_f32, vrndmq_m_f32, vrndnq_m_f32, vrndpq_m_f32, vrndq_m_f32, vrndxq_m_f32, vcmpeqq_m_n_f32, vcmpgeq_m_f32, vcmpgeq_m_n_f32, vcmpgtq_m_f32, vcmpgtq_m_n_f32, vcmpleq_m_f32, vcmpleq_m_n_f32, vcmpltq_m_f32, vcmpltq_m_n_f32, vcmpneq_m_f32, vcmpneq_m_n_f32, vmvnq_m_n_u32, vorrq_m_n_u32, vqrshruntq_n_s32, vqshrunbq_n_s32, vqshruntq_n_s32, vcvtmq_m_u32_f32, vcvtnq_m_u32_f32, vcvtpq_m_u32_f32, vcvtq_m_u32_f32, vqmovunbq_m_s32, vqmovuntq_m_s32, vqrshrntq_n_u32, vqshrnbq_n_u32, vqshrntq_n_u32, vrshrnbq_n_u32, vrshrntq_n_u32, vshrnbq_n_u32, vshrntq_n_u32, vmlaldavaq_u32, vmlaldavaxq_u32, vmlaldavq_p_u32, vmlaldavxq_p_u32, vmovlbq_m_u16, vmovltq_m_u16, vmovnbq_m_u32, vmovntq_m_u32, vqmovnbq_m_u32, vqmovntq_m_u32, vrev32q_m_u16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. (vrmlsldavhaq_s32): Likewise. (vrmlsldavhaxq_s32): Likewise. (vaddlvaq_p_s32): Likewise. (vcvtbq_m_f16_f32): Likewise. (vcvtbq_m_f32_f16): Likewise. (vcvttq_m_f16_f32): Likewise. (vcvttq_m_f32_f16): Likewise. (vrev16q_m_s8): Likewise. (vrev32q_m_f16): Likewise. (vrmlaldavhq_p_s32): Likewise. (vrmlaldavhxq_p_s32): Likewise. (vrmlsldavhq_p_s32): Likewise. (vrmlsldavhxq_p_s32): Likewise. (vaddlvaq_p_u32): Likewise. (vrev16q_m_u8): Likewise. (vrmlaldavhq_p_u32): Likewise. (vmvnq_m_n_s16): Likewise. (vorrq_m_n_s16): Likewise. (vqrshrntq_n_s16): Likewise. (vqshrnbq_n_s16): Likewise. (vqshrntq_n_s16): Likewise. (vrshrnbq_n_s16): Likewise. (vrshrntq_n_s16): Likewise. (vshrnbq_n_s16): Likewise. (vshrntq_n_s16): Likewise. (vcmlaq_f16): Likewise. (vcmlaq_rot180_f16): Likewise. (vcmlaq_rot270_f16): Likewise. (vcmlaq_rot90_f16): Likewise. (vfmaq_f16): Likewise. (vfmaq_n_f16): Likewise. (vfmasq_n_f16): Likewise. (vfmsq_f16): Likewise. (vmlaldavaq_s16): Likewise. (vmlaldavaxq_s16): Likewise. (vmlsldavaq_s16): Likewise. (vmlsldavaxq_s16): Likewise. (vabsq_m_f16): Likewise. (vcvtmq_m_s16_f16): Likewise. (vcvtnq_m_s16_f16): Likewise. (vcvtpq_m_s16_f16): Likewise. (vcvtq_m_s16_f16): Likewise. (vdupq_m_n_f16): Likewise. (vmaxnmaq_m_f16): Likewise. (vmaxnmavq_p_f16): Likewise. (vmaxnmvq_p_f16): Likewise. (vminnmaq_m_f16): Likewise. (vminnmavq_p_f16): Likewise. (vminnmvq_p_f16): Likewise. (vmlaldavq_p_s16): Likewise. (vmlaldavxq_p_s16): Likewise. (vmlsldavq_p_s16): Likewise. (vmlsldavxq_p_s16): Likewise. (vmovlbq_m_s8): Likewise. (vmovltq_m_s8): Likewise. (vmovnbq_m_s16): Likewise. (vmovntq_m_s16): Likewise. (vnegq_m_f16): Likewise. (vpselq_f16): Likewise. (vqmovnbq_m_s16): Likewise. (vqmovntq_m_s16): Likewise. (vrev32q_m_s8): Likewise. (vrev64q_m_f16): Likewise. (vrndaq_m_f16): Likewise. (vrndmq_m_f16): Likewise. (vrndnq_m_f16): Likewise. (vrndpq_m_f16): Likewise. (vrndq_m_f16): Likewise. (vrndxq_m_f16): Likewise. (vcmpeqq_m_n_f16): Likewise. (vcmpgeq_m_f16): Likewise. (vcmpgeq_m_n_f16): Likewise. (vcmpgtq_m_f16): Likewise. (vcmpgtq_m_n_f16): Likewise. (vcmpleq_m_f16): Likewise. (vcmpleq_m_n_f16): Likewise. (vcmpltq_m_f16): Likewise. (vcmpltq_m_n_f16): Likewise. (vcmpneq_m_f16): Likewise. (vcmpneq_m_n_f16): Likewise. (vmvnq_m_n_u16): Likewise. (vorrq_m_n_u16): Likewise. (vqrshruntq_n_s16): Likewise. (vqshrunbq_n_s16): Likewise. (vqshruntq_n_s16): Likewise. (vcvtmq_m_u16_f16): Likewise. (vcvtnq_m_u16_f16): Likewise. (vcvtpq_m_u16_f16): Likewise. (vcvtq_m_u16_f16): Likewise. (vqmovunbq_m_s16): Likewise. (vqmovuntq_m_s16): Likewise. (vqrshrntq_n_u16): Likewise. (vqshrnbq_n_u16): Likewise. (vqshrntq_n_u16): Likewise. (vrshrnbq_n_u16): Likewise. (vrshrntq_n_u16): Likewise. (vshrnbq_n_u16): Likewise. (vshrntq_n_u16): Likewise. (vmlaldavaq_u16): Likewise. (vmlaldavaxq_u16): Likewise. (vmlaldavq_p_u16): Likewise. (vmlaldavxq_p_u16): Likewise. (vmovlbq_m_u8): Likewise. (vmovltq_m_u8): Likewise. (vmovnbq_m_u16): Likewise. (vmovntq_m_u16): Likewise. (vqmovnbq_m_u16): Likewise. (vqmovntq_m_u16): Likewise. (vrev32q_m_u8): Likewise. (vmvnq_m_n_s32): Likewise. (vorrq_m_n_s32): Likewise. (vqrshrntq_n_s32): Likewise. (vqshrnbq_n_s32): Likewise. (vqshrntq_n_s32): Likewise. (vrshrnbq_n_s32): Likewise. (vrshrntq_n_s32): Likewise. (vshrnbq_n_s32): Likewise. (vshrntq_n_s32): Likewise. (vcmlaq_f32): Likewise. (vcmlaq_rot180_f32): Likewise. (vcmlaq_rot270_f32): Likewise. (vcmlaq_rot90_f32): Likewise. (vfmaq_f32): Likewise. (vfmaq_n_f32): Likewise. (vfmasq_n_f32): Likewise. (vfmsq_f32): Likewise. (vmlaldavaq_s32): Likewise. (vmlaldavaxq_s32): Likewise. (vmlsldavaq_s32): Likewise. (vmlsldavaxq_s32): Likewise. (vabsq_m_f32): Likewise. (vcvtmq_m_s32_f32): Likewise. (vcvtnq_m_s32_f32): Likewise. (vcvtpq_m_s32_f32): Likewise. (vcvtq_m_s32_f32): Likewise. (vdupq_m_n_f32): Likewise. (vmaxnmaq_m_f32): Likewise. (vmaxnmavq_p_f32): Likewise. (vmaxnmvq_p_f32): Likewise. (vminnmaq_m_f32): Likewise. (vminnmavq_p_f32): Likewise. (vminnmvq_p_f32): Likewise. (vmlaldavq_p_s32): Likewise. (vmlaldavxq_p_s32): Likewise. (vmlsldavq_p_s32): Likewise. (vmlsldavxq_p_s32): Likewise. (vmovlbq_m_s16): Likewise. (vmovltq_m_s16): Likewise. (vmovnbq_m_s32): Likewise. (vmovntq_m_s32): Likewise. (vnegq_m_f32): Likewise. (vpselq_f32): Likewise. (vqmovnbq_m_s32): Likewise. (vqmovntq_m_s32): Likewise. (vrev32q_m_s16): Likewise. (vrev64q_m_f32): Likewise. (vrndaq_m_f32): Likewise. (vrndmq_m_f32): Likewise. (vrndnq_m_f32): Likewise. (vrndpq_m_f32): Likewise. (vrndq_m_f32): Likewise. (vrndxq_m_f32): Likewise. (vcmpeqq_m_n_f32): Likewise. (vcmpgeq_m_f32): Likewise. (vcmpgeq_m_n_f32): Likewise. (vcmpgtq_m_f32): Likewise. (vcmpgtq_m_n_f32): Likewise. (vcmpleq_m_f32): Likewise. (vcmpleq_m_n_f32): Likewise. (vcmpltq_m_f32): Likewise. (vcmpltq_m_n_f32): Likewise. (vcmpneq_m_f32): Likewise. (vcmpneq_m_n_f32): Likewise. (vmvnq_m_n_u32): Likewise. (vorrq_m_n_u32): Likewise. (vqrshruntq_n_s32): Likewise. (vqshrunbq_n_s32): Likewise. (vqshruntq_n_s32): Likewise. (vcvtmq_m_u32_f32): Likewise. (vcvtnq_m_u32_f32): Likewise. (vcvtpq_m_u32_f32): Likewise. (vcvtq_m_u32_f32): Likewise. (vqmovunbq_m_s32): Likewise. (vqmovuntq_m_s32): Likewise. (vqrshrntq_n_u32): Likewise. (vqshrnbq_n_u32): Likewise. (vqshrntq_n_u32): Likewise. (vrshrnbq_n_u32): Likewise. (vrshrntq_n_u32): Likewise. (vshrnbq_n_u32): Likewise. (vshrntq_n_u32): Likewise. (vmlaldavaq_u32): Likewise. (vmlaldavaxq_u32): Likewise. (vmlaldavq_p_u32): Likewise. (vmlaldavxq_p_u32): Likewise. (vmovlbq_m_u16): Likewise. (vmovltq_m_u16): Likewise. (vmovnbq_m_u32): Likewise. (vmovntq_m_u32): Likewise. (vqmovnbq_m_u32): Likewise. (vqmovntq_m_u32): Likewise. (vrev32q_m_u16): Likewise. (__arm_vrmlaldavhaxq_s32): Define intrinsic. (__arm_vrmlsldavhaq_s32): Likewise. (__arm_vrmlsldavhaxq_s32): Likewise. (__arm_vaddlvaq_p_s32): Likewise. (__arm_vrev16q_m_s8): Likewise. (__arm_vrmlaldavhq_p_s32): Likewise. (__arm_vrmlaldavhxq_p_s32): Likewise. (__arm_vrmlsldavhq_p_s32): Likewise. (__arm_vrmlsldavhxq_p_s32): Likewise. (__arm_vaddlvaq_p_u32): Likewise. (__arm_vrev16q_m_u8): Likewise. (__arm_vrmlaldavhq_p_u32): Likewise. (__arm_vmvnq_m_n_s16): Likewise. (__arm_vorrq_m_n_s16): Likewise. (__arm_vqrshrntq_n_s16): Likewise. (__arm_vqshrnbq_n_s16): Likewise. (__arm_vqshrntq_n_s16): Likewise. (__arm_vrshrnbq_n_s16): Likewise. (__arm_vrshrntq_n_s16): Likewise. (__arm_vshrnbq_n_s16): Likewise. (__arm_vshrntq_n_s16): Likewise. (__arm_vmlaldavaq_s16): Likewise. (__arm_vmlaldavaxq_s16): Likewise. (__arm_vmlsldavaq_s16): Likewise. (__arm_vmlsldavaxq_s16): Likewise. (__arm_vmlaldavq_p_s16): Likewise. (__arm_vmlaldavxq_p_s16): Likewise. (__arm_vmlsldavq_p_s16): Likewise. (__arm_vmlsldavxq_p_s16): Likewise. (__arm_vmovlbq_m_s8): Likewise. (__arm_vmovltq_m_s8): Likewise. (__arm_vmovnbq_m_s16): Likewise. (__arm_vmovntq_m_s16): Likewise. (__arm_vqmovnbq_m_s16): Likewise. (__arm_vqmovntq_m_s16): Likewise. (__arm_vrev32q_m_s8): Likewise. (__arm_vmvnq_m_n_u16): Likewise. (__arm_vorrq_m_n_u16): Likewise. (__arm_vqrshruntq_n_s16): Likewise. (__arm_vqshrunbq_n_s16): Likewise. (__arm_vqshruntq_n_s16): Likewise. (__arm_vqmovunbq_m_s16): Likewise. (__arm_vqmovuntq_m_s16): Likewise. (__arm_vqrshrntq_n_u16): Likewise. (__arm_vqshrnbq_n_u16): Likewise. (__arm_vqshrntq_n_u16): Likewise. (__arm_vrshrnbq_n_u16): Likewise. (__arm_vrshrntq_n_u16): Likewise. (__arm_vshrnbq_n_u16): Likewise. (__arm_vshrntq_n_u16): Likewise. (__arm_vmlaldavaq_u16): Likewise. (__arm_vmlaldavaxq_u16): Likewise. (__arm_vmlaldavq_p_u16): Likewise. (__arm_vmlaldavxq_p_u16): Likewise. (__arm_vmovlbq_m_u8): Likewise. (__arm_vmovltq_m_u8): Likewise. (__arm_vmovnbq_m_u16): Likewise. (__arm_vmovntq_m_u16): Likewise. (__arm_vqmovnbq_m_u16): Likewise. (__arm_vqmovntq_m_u16): Likewise. (__arm_vrev32q_m_u8): Likewise. (__arm_vmvnq_m_n_s32): Likewise. (__arm_vorrq_m_n_s32): Likewise. (__arm_vqrshrntq_n_s32): Likewise. (__arm_vqshrnbq_n_s32): Likewise. (__arm_vqshrntq_n_s32): Likewise. (__arm_vrshrnbq_n_s32): Likewise. (__arm_vrshrntq_n_s32): Likewise. (__arm_vshrnbq_n_s32): Likewise. (__arm_vshrntq_n_s32): Likewise. (__arm_vmlaldavaq_s32): Likewise. (__arm_vmlaldavaxq_s32): Likewise. (__arm_vmlsldavaq_s32): Likewise. (__arm_vmlsldavaxq_s32): Likewise. (__arm_vmlaldavq_p_s32): Likewise. (__arm_vmlaldavxq_p_s32): Likewise. (__arm_vmlsldavq_p_s32): Likewise. (__arm_vmlsldavxq_p_s32): Likewise. (__arm_vmovlbq_m_s16): Likewise. (__arm_vmovltq_m_s16): Likewise. (__arm_vmovnbq_m_s32): Likewise. (__arm_vmovntq_m_s32): Likewise. (__arm_vqmovnbq_m_s32): Likewise. (__arm_vqmovntq_m_s32): Likewise. (__arm_vrev32q_m_s16): Likewise. (__arm_vmvnq_m_n_u32): Likewise. (__arm_vorrq_m_n_u32): Likewise. (__arm_vqrshruntq_n_s32): Likewise. (__arm_vqshrunbq_n_s32): Likewise. (__arm_vqshruntq_n_s32): Likewise. (__arm_vqmovunbq_m_s32): Likewise. (__arm_vqmovuntq_m_s32): Likewise. (__arm_vqrshrntq_n_u32): Likewise. (__arm_vqshrnbq_n_u32): Likewise. (__arm_vqshrntq_n_u32): Likewise. (__arm_vrshrnbq_n_u32): Likewise. (__arm_vrshrntq_n_u32): Likewise. (__arm_vshrnbq_n_u32): Likewise. (__arm_vshrntq_n_u32): Likewise. (__arm_vmlaldavaq_u32): Likewise. (__arm_vmlaldavaxq_u32): Likewise. (__arm_vmlaldavq_p_u32): Likewise. (__arm_vmlaldavxq_p_u32): Likewise. (__arm_vmovlbq_m_u16): Likewise. (__arm_vmovltq_m_u16): Likewise. (__arm_vmovnbq_m_u32): Likewise. (__arm_vmovntq_m_u32): Likewise. (__arm_vqmovnbq_m_u32): Likewise. (__arm_vqmovntq_m_u32): Likewise. (__arm_vrev32q_m_u16): Likewise. (__arm_vcvtbq_m_f16_f32): Likewise. (__arm_vcvtbq_m_f32_f16): Likewise. (__arm_vcvttq_m_f16_f32): Likewise. (__arm_vcvttq_m_f32_f16): Likewise. (__arm_vrev32q_m_f16): Likewise. (__arm_vcmlaq_f16): Likewise. (__arm_vcmlaq_rot180_f16): Likewise. (__arm_vcmlaq_rot270_f16): Likewise. (__arm_vcmlaq_rot90_f16): Likewise. (__arm_vfmaq_f16): Likewise. (__arm_vfmaq_n_f16): Likewise. (__arm_vfmasq_n_f16): Likewise. (__arm_vfmsq_f16): Likewise. (__arm_vabsq_m_f16): Likewise. (__arm_vcvtmq_m_s16_f16): Likewise. (__arm_vcvtnq_m_s16_f16): Likewise. (__arm_vcvtpq_m_s16_f16): Likewise. (__arm_vcvtq_m_s16_f16): Likewise. (__arm_vdupq_m_n_f16): Likewise. (__arm_vmaxnmaq_m_f16): Likewise. (__arm_vmaxnmavq_p_f16): Likewise. (__arm_vmaxnmvq_p_f16): Likewise. (__arm_vminnmaq_m_f16): Likewise. (__arm_vminnmavq_p_f16): Likewise. (__arm_vminnmvq_p_f16): Likewise. (__arm_vnegq_m_f16): Likewise. (__arm_vpselq_f16): Likewise. (__arm_vrev64q_m_f16): Likewise. (__arm_vrndaq_m_f16): Likewise. (__arm_vrndmq_m_f16): Likewise. (__arm_vrndnq_m_f16): Likewise. (__arm_vrndpq_m_f16): Likewise. (__arm_vrndq_m_f16): Likewise. (__arm_vrndxq_m_f16): Likewise. (__arm_vcmpeqq_m_n_f16): Likewise. (__arm_vcmpgeq_m_f16): Likewise. (__arm_vcmpgeq_m_n_f16): Likewise. (__arm_vcmpgtq_m_f16): Likewise. (__arm_vcmpgtq_m_n_f16): Likewise. (__arm_vcmpleq_m_f16): Likewise. (__arm_vcmpleq_m_n_f16): Likewise. (__arm_vcmpltq_m_f16): Likewise. (__arm_vcmpltq_m_n_f16): Likewise. (__arm_vcmpneq_m_f16): Likewise. (__arm_vcmpneq_m_n_f16): Likewise. (__arm_vcvtmq_m_u16_f16): Likewise. (__arm_vcvtnq_m_u16_f16): Likewise. (__arm_vcvtpq_m_u16_f16): Likewise. (__arm_vcvtq_m_u16_f16): Likewise. (__arm_vcmlaq_f32): Likewise. (__arm_vcmlaq_rot180_f32): Likewise. (__arm_vcmlaq_rot270_f32): Likewise. (__arm_vcmlaq_rot90_f32): Likewise. (__arm_vfmaq_f32): Likewise. (__arm_vfmaq_n_f32): Likewise. (__arm_vfmasq_n_f32): Likewise. (__arm_vfmsq_f32): Likewise. (__arm_vabsq_m_f32): Likewise. (__arm_vcvtmq_m_s32_f32): Likewise. (__arm_vcvtnq_m_s32_f32): Likewise. (__arm_vcvtpq_m_s32_f32): Likewise. (__arm_vcvtq_m_s32_f32): Likewise. (__arm_vdupq_m_n_f32): Likewise. (__arm_vmaxnmaq_m_f32): Likewise. (__arm_vmaxnmavq_p_f32): Likewise. (__arm_vmaxnmvq_p_f32): Likewise. (__arm_vminnmaq_m_f32): Likewise. (__arm_vminnmavq_p_f32): Likewise. (__arm_vminnmvq_p_f32): Likewise. (__arm_vnegq_m_f32): Likewise. (__arm_vpselq_f32): Likewise. (__arm_vrev64q_m_f32): Likewise. (__arm_vrndaq_m_f32): Likewise. (__arm_vrndmq_m_f32): Likewise. (__arm_vrndnq_m_f32): Likewise. (__arm_vrndpq_m_f32): Likewise. (__arm_vrndq_m_f32): Likewise. (__arm_vrndxq_m_f32): Likewise. (__arm_vcmpeqq_m_n_f32): Likewise. (__arm_vcmpgeq_m_f32): Likewise. (__arm_vcmpgeq_m_n_f32): Likewise. (__arm_vcmpgtq_m_f32): Likewise. (__arm_vcmpgtq_m_n_f32): Likewise. (__arm_vcmpleq_m_f32): Likewise. (__arm_vcmpleq_m_n_f32): Likewise. (__arm_vcmpltq_m_f32): Likewise. (__arm_vcmpltq_m_n_f32): Likewise. (__arm_vcmpneq_m_f32): Likewise. (__arm_vcmpneq_m_n_f32): Likewise. (__arm_vcvtmq_m_u32_f32): Likewise. (__arm_vcvtnq_m_u32_f32): Likewise. (__arm_vcvtpq_m_u32_f32): Likewise. (__arm_vcvtq_m_u32_f32): Likewise. (vcvtq_m): Define polymorphic variant. (vabsq_m): Likewise. (vcmlaq): Likewise. (vcmlaq_rot180): Likewise. (vcmlaq_rot270): Likewise. (vcmlaq_rot90): Likewise. (vcmpeqq_m_n): Likewise. (vcmpgeq_m_n): Likewise. (vrndxq_m): Likewise. (vrndq_m): Likewise. (vrndpq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpneq_m): Likewise. (vcmpneq_m_n): Likewise. (vcvtbq_m): Likewise. (vcvttq_m): Likewise. (vcvtmq_m): Likewise. (vcvtnq_m): Likewise. (vcvtpq_m): Likewise. (vdupq_m_n): Likewise. (vfmaq_n): Likewise. (vfmaq): Likewise. (vfmasq_n): Likewise. (vfmsq): Likewise. (vmaxnmaq_m): Likewise. (vmaxnmavq_m): Likewise. (vmaxnmvq_m): Likewise. (vmaxnmavq_p): Likewise. (vmaxnmvq_p): Likewise. (vminnmaq_m): Likewise. (vminnmavq_p): Likewise. (vminnmvq_p): Likewise. (vrndnq_m): Likewise. (vrndaq_m): Likewise. (vrndmq_m): Likewise. (vrev64q_m): Likewise. (vrev32q_m): Likewise. (vpselq): Likewise. (vnegq_m): Likewise. (vcmpgeq_m): Likewise. (vshrntq_n): Likewise. (vrshrntq_n): Likewise. (vmovlbq_m): Likewise. (vmovnbq_m): Likewise. (vmovntq_m): Likewise. (vmvnq_m_n): Likewise. (vmvnq_m): Likewise. (vshrnbq_n): Likewise. (vrshrnbq_n): Likewise. (vqshruntq_n): Likewise. (vrev16q_m): Likewise. (vqshrunbq_n): Likewise. (vqshrntq_n): Likewise. (vqrshruntq_n): Likewise. (vqrshrntq_n): Likewise. (vqshrnbq_n): Likewise. (vqmovuntq_m): Likewise. (vqmovntq_m): Likewise. (vqmovnbq_m): Likewise. (vorrq_m_n): Likewise. (vmovltq_m): Likewise. (vqmovunbq_m): Likewise. (vaddlvaq_p): Likewise. (vmlaldavaq): Likewise. (vmlaldavaxq): Likewise. (vmlaldavq_p): Likewise. (vmlaldavxq_p): Likewise. (vmlsldavaq): Likewise. (vmlsldavaxq): Likewise. (vmlsldavq_p): Likewise. (vmlsldavxq_p): Likewise. (vrmlaldavhaxq): Likewise. (vrmlaldavhq_p): Likewise. (vrmlaldavhxq_p): Likewise. (vrmlsldavhaq): Likewise. (vrmlsldavhaxq): Likewise. (vrmlsldavhq_p): Likewise. (vrmlsldavhxq_p): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_IMM): Likewise. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. (MVE_pred3): Likewise. (MVE_constraint1): Likewise. (MVE_pred1): Likewise. (VMLALDAVQ_P): Define iterator. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise. (VORRQ_M_N): Likewise. (VREV32Q_M): Likewise. (VREV16Q_M): Likewise. (VQRSHRNTQ_N): Likewise. (VMOVNTQ_M): Likewise. (VMOVLBQ_M): Likewise. (VMLALDAVAQ): Likewise. (VQSHRNBQ_N): Likewise. (VSHRNBQ_N): Likewise. (VRSHRNBQ_N): Likewise. (VMLALDAVXQ_P): Likewise. (VQMOVNTQ_M): Likewise. (VMVNQ_M_N): Likewise. (VQSHRNTQ_N): Likewise. (VMLALDAVAXQ): Likewise. (VSHRNTQ_N): Likewise. (VCVTMQ_M): Likewise. (VCVTNQ_M): Likewise. (VCVTPQ_M): Likewise. (VCVTQ_M_N_FROM_F): Likewise. (VCVTQ_M_FROM_F): Likewise. (VRMLALDAVHQ_P): Likewise. (VADDLVAQ_P): Likewise. (mve_vrndq_m_f<mode>): Define RTL pattern. (mve_vabsq_m_f<mode>): Likewise. (mve_vaddlvaq_p_<supf>v4si): Likewise. (mve_vcmlaq_f<mode>): Likewise. (mve_vcmlaq_rot180_f<mode>): Likewise. (mve_vcmlaq_rot270_f<mode>): Likewise. (mve_vcmlaq_rot90_f<mode>): Likewise. (mve_vcmpeqq_m_n_f<mode>): Likewise. (mve_vcmpgeq_m_f<mode>): Likewise. (mve_vcmpgeq_m_n_f<mode>): Likewise. (mve_vcmpgtq_m_f<mode>): Likewise. (mve_vcmpgtq_m_n_f<mode>): Likewise. (mve_vcmpleq_m_f<mode>): Likewise. (mve_vcmpleq_m_n_f<mode>): Likewise. (mve_vcmpltq_m_f<mode>): Likewise. (mve_vcmpltq_m_n_f<mode>): Likewise. (mve_vcmpneq_m_f<mode>): Likewise. (mve_vcmpneq_m_n_f<mode>): Likewise. (mve_vcvtbq_m_f16_f32v8hf): Likewise. (mve_vcvtbq_m_f32_f16v4sf): Likewise. (mve_vcvttq_m_f16_f32v8hf): Likewise. (mve_vcvttq_m_f32_f16v4sf): Likewise. (mve_vdupq_m_n_f<mode>): Likewise. (mve_vfmaq_f<mode>): Likewise. (mve_vfmaq_n_f<mode>): Likewise. (mve_vfmasq_n_f<mode>): Likewise. (mve_vfmsq_f<mode>): Likewise. (mve_vmaxnmaq_m_f<mode>): Likewise. (mve_vmaxnmavq_p_f<mode>): Likewise. (mve_vmaxnmvq_p_f<mode>): Likewise. (mve_vminnmaq_m_f<mode>): Likewise. (mve_vminnmavq_p_f<mode>): Likewise. (mve_vminnmvq_p_f<mode>): Likewise. (mve_vmlaldavaq_<supf><mode>): Likewise. (mve_vmlaldavaxq_<supf><mode>): Likewise. (mve_vmlaldavq_p_<supf><mode>): Likewise. (mve_vmlaldavxq_p_<supf><mode>): Likewise. (mve_vmlsldavaq_s<mode>): Likewise. (mve_vmlsldavaxq_s<mode>): Likewise. (mve_vmlsldavq_p_s<mode>): Likewise. (mve_vmlsldavxq_p_s<mode>): Likewise. (mve_vmovlbq_m_<supf><mode>): Likewise. (mve_vmovltq_m_<supf><mode>): Likewise. (mve_vmovnbq_m_<supf><mode>): Likewise. (mve_vmovntq_m_<supf><mode>): Likewise. (mve_vmvnq_m_n_<supf><mode>): Likewise. (mve_vnegq_m_f<mode>): Likewise. (mve_vorrq_m_n_<supf><mode>): Likewise. (mve_vpselq_f<mode>): Likewise. (mve_vqmovnbq_m_<supf><mode>): Likewise. (mve_vqmovntq_m_<supf><mode>): Likewise. (mve_vqmovunbq_m_s<mode>): Likewise. (mve_vqmovuntq_m_s<mode>): Likewise. (mve_vqrshrntq_n_<supf><mode>): Likewise. (mve_vqrshruntq_n_s<mode>): Likewise. (mve_vqshrnbq_n_<supf><mode>): Likewise. (mve_vqshrntq_n_<supf><mode>): Likewise. (mve_vqshrunbq_n_s<mode>): Likewise. (mve_vqshruntq_n_s<mode>): Likewise. (mve_vrev32q_m_fv8hf): Likewise. (mve_vrev32q_m_<supf><mode>): Likewise. (mve_vrev64q_m_f<mode>): Likewise. (mve_vrmlaldavhaxq_sv4si): Likewise. (mve_vrmlaldavhxq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_sv4si): Likewise. (mve_vrmlsldavhq_p_sv4si): Likewise. (mve_vrmlsldavhxq_p_sv4si): Likewise. (mve_vrndaq_m_f<mode>): Likewise. (mve_vrndmq_m_f<mode>): Likewise. (mve_vrndnq_m_f<mode>): Likewise. (mve_vrndpq_m_f<mode>): Likewise. (mve_vrndxq_m_f<mode>): Likewise. (mve_vrshrnbq_n_<supf><mode>): Likewise. (mve_vrshrntq_n_<supf><mode>): Likewise. (mve_vshrnbq_n_<supf><mode>): Likewise. (mve_vshrntq_n_<supf><mode>): Likewise. (mve_vcvtmq_m_<supf><mode>): Likewise. (mve_vcvtpq_m_<supf><mode>): Likewise. (mve_vcvtnq_m_<supf><mode>): Likewise. (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise. (mve_vrev16q_m_<supf>v16qi): Likewise. (mve_vcvtq_m_from_f_<supf><mode>): Likewise. (mve_vrmlaldavhq_p_<supf>v4si): Likewise. (mve_vrmlsldavhaq_sv4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vfmsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaldavxq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c: Likewise. |
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|
Srinath Parvathaneni
|
8165795c15 |
[ARM][GCC][2/3x]: MVE intrinsics with ternary operands.
This patch supports following MVE ACLE intrinsics with ternary operands. vpselq_u8, vpselq_s8, vrev64q_m_u8, vqrdmlashq_n_u8, vqrdmlahq_n_u8, vqdmlahq_n_u8, vmvnq_m_u8, vmlasq_n_u8, vmlaq_n_u8, vmladavq_p_u8, vmladavaq_u8, vminvq_p_u8, vmaxvq_p_u8, vdupq_m_n_u8, vcmpneq_m_u8, vcmpneq_m_n_u8, vcmphiq_m_u8, vcmphiq_m_n_u8, vcmpeqq_m_u8, vcmpeqq_m_n_u8, vcmpcsq_m_u8, vcmpcsq_m_n_u8, vclzq_m_u8, vaddvaq_p_u8, vsriq_n_u8, vsliq_n_u8, vshlq_m_r_u8, vrshlq_m_n_u8, vqshlq_m_r_u8, vqrshlq_m_n_u8, vminavq_p_s8, vminaq_m_s8, vmaxavq_p_s8, vmaxaq_m_s8, vcmpneq_m_s8, vcmpneq_m_n_s8, vcmpltq_m_s8, vcmpltq_m_n_s8, vcmpleq_m_s8, vcmpleq_m_n_s8, vcmpgtq_m_s8, vcmpgtq_m_n_s8, vcmpgeq_m_s8, vcmpgeq_m_n_s8, vcmpeqq_m_s8, vcmpeqq_m_n_s8, vshlq_m_r_s8, vrshlq_m_n_s8, vrev64q_m_s8, vqshlq_m_r_s8, vqrshlq_m_n_s8, vqnegq_m_s8, vqabsq_m_s8, vnegq_m_s8, vmvnq_m_s8, vmlsdavxq_p_s8, vmlsdavq_p_s8, vmladavxq_p_s8, vmladavq_p_s8, vminvq_p_s8, vmaxvq_p_s8, vdupq_m_n_s8, vclzq_m_s8, vclsq_m_s8, vaddvaq_p_s8, vabsq_m_s8, vqrdmlsdhxq_s8, vqrdmlsdhq_s8, vqrdmlashq_n_s8, vqrdmlahq_n_s8, vqrdmladhxq_s8, vqrdmladhq_s8, vqdmlsdhxq_s8, vqdmlsdhq_s8, vqdmlahq_n_s8, vqdmladhxq_s8, vqdmladhq_s8, vmlsdavaxq_s8, vmlsdavaq_s8, vmlasq_n_s8, vmlaq_n_s8, vmladavaxq_s8, vmladavaq_s8, vsriq_n_s8, vsliq_n_s8, vpselq_u16, vpselq_s16, vrev64q_m_u16, vqrdmlashq_n_u16, vqrdmlahq_n_u16, vqdmlahq_n_u16, vmvnq_m_u16, vmlasq_n_u16, vmlaq_n_u16, vmladavq_p_u16, vmladavaq_u16, vminvq_p_u16, vmaxvq_p_u16, vdupq_m_n_u16, vcmpneq_m_u16, vcmpneq_m_n_u16, vcmphiq_m_u16, vcmphiq_m_n_u16, vcmpeqq_m_u16, vcmpeqq_m_n_u16, vcmpcsq_m_u16, vcmpcsq_m_n_u16, vclzq_m_u16, vaddvaq_p_u16, vsriq_n_u16, vsliq_n_u16, vshlq_m_r_u16, vrshlq_m_n_u16, vqshlq_m_r_u16, vqrshlq_m_n_u16, vminavq_p_s16, vminaq_m_s16, vmaxavq_p_s16, vmaxaq_m_s16, vcmpneq_m_s16, vcmpneq_m_n_s16, vcmpltq_m_s16, vcmpltq_m_n_s16, vcmpleq_m_s16, vcmpleq_m_n_s16, vcmpgtq_m_s16, vcmpgtq_m_n_s16, vcmpgeq_m_s16, vcmpgeq_m_n_s16, vcmpeqq_m_s16, vcmpeqq_m_n_s16, vshlq_m_r_s16, vrshlq_m_n_s16, vrev64q_m_s16, vqshlq_m_r_s16, vqrshlq_m_n_s16, vqnegq_m_s16, vqabsq_m_s16, vnegq_m_s16, vmvnq_m_s16, vmlsdavxq_p_s16, vmlsdavq_p_s16, vmladavxq_p_s16, vmladavq_p_s16, vminvq_p_s16, vmaxvq_p_s16, vdupq_m_n_s16, vclzq_m_s16, vclsq_m_s16, vaddvaq_p_s16, vabsq_m_s16, vqrdmlsdhxq_s16, vqrdmlsdhq_s16, vqrdmlashq_n_s16, vqrdmlahq_n_s16, vqrdmladhxq_s16, vqrdmladhq_s16, vqdmlsdhxq_s16, vqdmlsdhq_s16, vqdmlahq_n_s16, vqdmladhxq_s16, vqdmladhq_s16, vmlsdavaxq_s16, vmlsdavaq_s16, vmlasq_n_s16, vmlaq_n_s16, vmladavaxq_s16, vmladavaq_s16, vsriq_n_s16, vsliq_n_s16, vpselq_u32, vpselq_s32, vrev64q_m_u32, vqrdmlashq_n_u32, vqrdmlahq_n_u32, vqdmlahq_n_u32, vmvnq_m_u32, vmlasq_n_u32, vmlaq_n_u32, vmladavq_p_u32, vmladavaq_u32, vminvq_p_u32, vmaxvq_p_u32, vdupq_m_n_u32, vcmpneq_m_u32, vcmpneq_m_n_u32, vcmphiq_m_u32, vcmphiq_m_n_u32, vcmpeqq_m_u32, vcmpeqq_m_n_u32, vcmpcsq_m_u32, vcmpcsq_m_n_u32, vclzq_m_u32, vaddvaq_p_u32, vsriq_n_u32, vsliq_n_u32, vshlq_m_r_u32, vrshlq_m_n_u32, vqshlq_m_r_u32, vqrshlq_m_n_u32, vminavq_p_s32, vminaq_m_s32, vmaxavq_p_s32, vmaxaq_m_s32, vcmpneq_m_s32, vcmpneq_m_n_s32, vcmpltq_m_s32, vcmpltq_m_n_s32, vcmpleq_m_s32, vcmpleq_m_n_s32, vcmpgtq_m_s32, vcmpgtq_m_n_s32, vcmpgeq_m_s32, vcmpgeq_m_n_s32, vcmpeqq_m_s32, vcmpeqq_m_n_s32, vshlq_m_r_s32, vrshlq_m_n_s32, vrev64q_m_s32, vqshlq_m_r_s32, vqrshlq_m_n_s32, vqnegq_m_s32, vqabsq_m_s32, vnegq_m_s32, vmvnq_m_s32, vmlsdavxq_p_s32, vmlsdavq_p_s32, vmladavxq_p_s32, vmladavq_p_s32, vminvq_p_s32, vmaxvq_p_s32, vdupq_m_n_s32, vclzq_m_s32, vclsq_m_s32, vaddvaq_p_s32, vabsq_m_s32, vqrdmlsdhxq_s32, vqrdmlsdhq_s32, vqrdmlashq_n_s32, vqrdmlahq_n_s32, vqrdmladhxq_s32, vqrdmladhq_s32, vqdmlsdhxq_s32, vqdmlsdhq_s32, vqdmlahq_n_s32, vqdmladhxq_s32, vqdmladhq_s32, vmlsdavaxq_s32, vmlsdavaq_s32, vmlasq_n_s32, vmlaq_n_s32, vmladavaxq_s32, vmladavaq_s32, vsriq_n_s32, vsliq_n_s32, vpselq_u64, vpselq_s64. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics In this patch new constraints "Rc" and "Re" are added, which checks the constant is with in the range of 0 to 15 and 0 to 31 respectively. Also a new predicates "mve_imm_15" and "mve_imm_31" are added, to check the the matching constraint Rc and Re respectively. 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm_mve.h (vpselq_u8): Define macro. (vpselq_s8): Likewise. (vrev64q_m_u8): Likewise. (vqrdmlashq_n_u8): Likewise. (vqrdmlahq_n_u8): Likewise. (vqdmlahq_n_u8): Likewise. (vmvnq_m_u8): Likewise. (vmlasq_n_u8): Likewise. (vmlaq_n_u8): Likewise. (vmladavq_p_u8): Likewise. (vmladavaq_u8): Likewise. (vminvq_p_u8): Likewise. (vmaxvq_p_u8): Likewise. (vdupq_m_n_u8): Likewise. (vcmpneq_m_u8): Likewise. (vcmpneq_m_n_u8): Likewise. (vcmphiq_m_u8): Likewise. (vcmphiq_m_n_u8): Likewise. (vcmpeqq_m_u8): Likewise. (vcmpeqq_m_n_u8): Likewise. (vcmpcsq_m_u8): Likewise. (vcmpcsq_m_n_u8): Likewise. (vclzq_m_u8): Likewise. (vaddvaq_p_u8): Likewise. (vsriq_n_u8): Likewise. (vsliq_n_u8): Likewise. (vshlq_m_r_u8): Likewise. (vrshlq_m_n_u8): Likewise. (vqshlq_m_r_u8): Likewise. (vqrshlq_m_n_u8): Likewise. (vminavq_p_s8): Likewise. (vminaq_m_s8): Likewise. (vmaxavq_p_s8): Likewise. (vmaxaq_m_s8): Likewise. (vcmpneq_m_s8): Likewise. (vcmpneq_m_n_s8): Likewise. (vcmpltq_m_s8): Likewise. (vcmpltq_m_n_s8): Likewise. (vcmpleq_m_s8): Likewise. (vcmpleq_m_n_s8): Likewise. (vcmpgtq_m_s8): Likewise. (vcmpgtq_m_n_s8): Likewise. (vcmpgeq_m_s8): Likewise. (vcmpgeq_m_n_s8): Likewise. (vcmpeqq_m_s8): Likewise. (vcmpeqq_m_n_s8): Likewise. (vshlq_m_r_s8): Likewise. (vrshlq_m_n_s8): Likewise. (vrev64q_m_s8): Likewise. (vqshlq_m_r_s8): Likewise. (vqrshlq_m_n_s8): Likewise. (vqnegq_m_s8): Likewise. (vqabsq_m_s8): Likewise. (vnegq_m_s8): Likewise. (vmvnq_m_s8): Likewise. (vmlsdavxq_p_s8): Likewise. (vmlsdavq_p_s8): Likewise. (vmladavxq_p_s8): Likewise. (vmladavq_p_s8): Likewise. (vminvq_p_s8): Likewise. (vmaxvq_p_s8): Likewise. (vdupq_m_n_s8): Likewise. (vclzq_m_s8): Likewise. (vclsq_m_s8): Likewise. (vaddvaq_p_s8): Likewise. (vabsq_m_s8): Likewise. (vqrdmlsdhxq_s8): Likewise. (vqrdmlsdhq_s8): Likewise. (vqrdmlashq_n_s8): Likewise. (vqrdmlahq_n_s8): Likewise. (vqrdmladhxq_s8): Likewise. (vqrdmladhq_s8): Likewise. (vqdmlsdhxq_s8): Likewise. (vqdmlsdhq_s8): Likewise. (vqdmlahq_n_s8): Likewise. (vqdmladhxq_s8): Likewise. (vqdmladhq_s8): Likewise. (vmlsdavaxq_s8): Likewise. (vmlsdavaq_s8): Likewise. (vmlasq_n_s8): Likewise. (vmlaq_n_s8): Likewise. (vmladavaxq_s8): Likewise. (vmladavaq_s8): Likewise. (vsriq_n_s8): Likewise. (vsliq_n_s8): Likewise. (vpselq_u16): Likewise. (vpselq_s16): Likewise. (vrev64q_m_u16): Likewise. (vqrdmlashq_n_u16): Likewise. (vqrdmlahq_n_u16): Likewise. (vqdmlahq_n_u16): Likewise. (vmvnq_m_u16): Likewise. (vmlasq_n_u16): Likewise. (vmlaq_n_u16): Likewise. (vmladavq_p_u16): Likewise. (vmladavaq_u16): Likewise. (vminvq_p_u16): Likewise. (vmaxvq_p_u16): Likewise. (vdupq_m_n_u16): Likewise. (vcmpneq_m_u16): Likewise. (vcmpneq_m_n_u16): Likewise. (vcmphiq_m_u16): Likewise. (vcmphiq_m_n_u16): Likewise. (vcmpeqq_m_u16): Likewise. (vcmpeqq_m_n_u16): Likewise. (vcmpcsq_m_u16): Likewise. (vcmpcsq_m_n_u16): Likewise. (vclzq_m_u16): Likewise. (vaddvaq_p_u16): Likewise. (vsriq_n_u16): Likewise. (vsliq_n_u16): Likewise. (vshlq_m_r_u16): Likewise. (vrshlq_m_n_u16): Likewise. (vqshlq_m_r_u16): Likewise. (vqrshlq_m_n_u16): Likewise. (vminavq_p_s16): Likewise. (vminaq_m_s16): Likewise. (vmaxavq_p_s16): Likewise. (vmaxaq_m_s16): Likewise. (vcmpneq_m_s16): Likewise. (vcmpneq_m_n_s16): Likewise. (vcmpltq_m_s16): Likewise. (vcmpltq_m_n_s16): Likewise. (vcmpleq_m_s16): Likewise. (vcmpleq_m_n_s16): Likewise. (vcmpgtq_m_s16): Likewise. (vcmpgtq_m_n_s16): Likewise. (vcmpgeq_m_s16): Likewise. (vcmpgeq_m_n_s16): Likewise. (vcmpeqq_m_s16): Likewise. (vcmpeqq_m_n_s16): Likewise. (vshlq_m_r_s16): Likewise. (vrshlq_m_n_s16): Likewise. (vrev64q_m_s16): Likewise. (vqshlq_m_r_s16): Likewise. (vqrshlq_m_n_s16): Likewise. (vqnegq_m_s16): Likewise. (vqabsq_m_s16): Likewise. (vnegq_m_s16): Likewise. (vmvnq_m_s16): Likewise. (vmlsdavxq_p_s16): Likewise. (vmlsdavq_p_s16): Likewise. (vmladavxq_p_s16): Likewise. (vmladavq_p_s16): Likewise. (vminvq_p_s16): Likewise. (vmaxvq_p_s16): Likewise. (vdupq_m_n_s16): Likewise. (vclzq_m_s16): Likewise. (vclsq_m_s16): Likewise. (vaddvaq_p_s16): Likewise. (vabsq_m_s16): Likewise. (vqrdmlsdhxq_s16): Likewise. (vqrdmlsdhq_s16): Likewise. (vqrdmlashq_n_s16): Likewise. (vqrdmlahq_n_s16): Likewise. (vqrdmladhxq_s16): Likewise. (vqrdmladhq_s16): Likewise. (vqdmlsdhxq_s16): Likewise. (vqdmlsdhq_s16): Likewise. (vqdmlahq_n_s16): Likewise. (vqdmladhxq_s16): Likewise. (vqdmladhq_s16): Likewise. (vmlsdavaxq_s16): Likewise. (vmlsdavaq_s16): Likewise. (vmlasq_n_s16): Likewise. (vmlaq_n_s16): Likewise. (vmladavaxq_s16): Likewise. (vmladavaq_s16): Likewise. (vsriq_n_s16): Likewise. (vsliq_n_s16): Likewise. (vpselq_u32): Likewise. (vpselq_s32): Likewise. (vrev64q_m_u32): Likewise. (vqrdmlashq_n_u32): Likewise. (vqrdmlahq_n_u32): Likewise. (vqdmlahq_n_u32): Likewise. (vmvnq_m_u32): Likewise. (vmlasq_n_u32): Likewise. (vmlaq_n_u32): Likewise. (vmladavq_p_u32): Likewise. (vmladavaq_u32): Likewise. (vminvq_p_u32): Likewise. (vmaxvq_p_u32): Likewise. (vdupq_m_n_u32): Likewise. (vcmpneq_m_u32): Likewise. (vcmpneq_m_n_u32): Likewise. (vcmphiq_m_u32): Likewise. (vcmphiq_m_n_u32): Likewise. (vcmpeqq_m_u32): Likewise. (vcmpeqq_m_n_u32): Likewise. (vcmpcsq_m_u32): Likewise. (vcmpcsq_m_n_u32): Likewise. (vclzq_m_u32): Likewise. (vaddvaq_p_u32): Likewise. (vsriq_n_u32): Likewise. (vsliq_n_u32): Likewise. (vshlq_m_r_u32): Likewise. (vrshlq_m_n_u32): Likewise. (vqshlq_m_r_u32): Likewise. (vqrshlq_m_n_u32): Likewise. (vminavq_p_s32): Likewise. (vminaq_m_s32): Likewise. (vmaxavq_p_s32): Likewise. (vmaxaq_m_s32): Likewise. (vcmpneq_m_s32): Likewise. (vcmpneq_m_n_s32): Likewise. (vcmpltq_m_s32): Likewise. (vcmpltq_m_n_s32): Likewise. (vcmpleq_m_s32): Likewise. (vcmpleq_m_n_s32): Likewise. (vcmpgtq_m_s32): Likewise. (vcmpgtq_m_n_s32): Likewise. (vcmpgeq_m_s32): Likewise. (vcmpgeq_m_n_s32): Likewise. (vcmpeqq_m_s32): Likewise. (vcmpeqq_m_n_s32): Likewise. (vshlq_m_r_s32): Likewise. (vrshlq_m_n_s32): Likewise. (vrev64q_m_s32): Likewise. (vqshlq_m_r_s32): Likewise. (vqrshlq_m_n_s32): Likewise. (vqnegq_m_s32): Likewise. (vqabsq_m_s32): Likewise. (vnegq_m_s32): Likewise. (vmvnq_m_s32): Likewise. (vmlsdavxq_p_s32): Likewise. (vmlsdavq_p_s32): Likewise. (vmladavxq_p_s32): Likewise. (vmladavq_p_s32): Likewise. (vminvq_p_s32): Likewise. (vmaxvq_p_s32): Likewise. (vdupq_m_n_s32): Likewise. (vclzq_m_s32): Likewise. (vclsq_m_s32): Likewise. (vaddvaq_p_s32): Likewise. (vabsq_m_s32): Likewise. (vqrdmlsdhxq_s32): Likewise. (vqrdmlsdhq_s32): Likewise. (vqrdmlashq_n_s32): Likewise. (vqrdmlahq_n_s32): Likewise. (vqrdmladhxq_s32): Likewise. (vqrdmladhq_s32): Likewise. (vqdmlsdhxq_s32): Likewise. (vqdmlsdhq_s32): Likewise. (vqdmlahq_n_s32): Likewise. (vqdmladhxq_s32): Likewise. (vqdmladhq_s32): Likewise. (vmlsdavaxq_s32): Likewise. (vmlsdavaq_s32): Likewise. (vmlasq_n_s32): Likewise. (vmlaq_n_s32): Likewise. (vmladavaxq_s32): Likewise. (vmladavaq_s32): Likewise. (vsriq_n_s32): Likewise. (vsliq_n_s32): Likewise. (vpselq_u64): Likewise. (vpselq_s64): Likewise. (__arm_vpselq_u8): Define intrinsic. (__arm_vpselq_s8): Likewise. (__arm_vrev64q_m_u8): Likewise. (__arm_vqrdmlashq_n_u8): Likewise. (__arm_vqrdmlahq_n_u8): Likewise. (__arm_vqdmlahq_n_u8): Likewise. (__arm_vmvnq_m_u8): Likewise. (__arm_vmlasq_n_u8): Likewise. (__arm_vmlaq_n_u8): Likewise. (__arm_vmladavq_p_u8): Likewise. (__arm_vmladavaq_u8): Likewise. (__arm_vminvq_p_u8): Likewise. (__arm_vmaxvq_p_u8): Likewise. (__arm_vdupq_m_n_u8): Likewise. (__arm_vcmpneq_m_u8): Likewise. (__arm_vcmpneq_m_n_u8): Likewise. (__arm_vcmphiq_m_u8): Likewise. (__arm_vcmphiq_m_n_u8): Likewise. (__arm_vcmpeqq_m_u8): Likewise. (__arm_vcmpeqq_m_n_u8): Likewise. (__arm_vcmpcsq_m_u8): Likewise. (__arm_vcmpcsq_m_n_u8): Likewise. (__arm_vclzq_m_u8): Likewise. (__arm_vaddvaq_p_u8): Likewise. (__arm_vsriq_n_u8): Likewise. (__arm_vsliq_n_u8): Likewise. (__arm_vshlq_m_r_u8): Likewise. (__arm_vrshlq_m_n_u8): Likewise. (__arm_vqshlq_m_r_u8): Likewise. (__arm_vqrshlq_m_n_u8): Likewise. (__arm_vminavq_p_s8): Likewise. (__arm_vminaq_m_s8): Likewise. (__arm_vmaxavq_p_s8): Likewise. (__arm_vmaxaq_m_s8): Likewise. (__arm_vcmpneq_m_s8): Likewise. (__arm_vcmpneq_m_n_s8): Likewise. (__arm_vcmpltq_m_s8): Likewise. (__arm_vcmpltq_m_n_s8): Likewise. (__arm_vcmpleq_m_s8): Likewise. (__arm_vcmpleq_m_n_s8): Likewise. (__arm_vcmpgtq_m_s8): Likewise. (__arm_vcmpgtq_m_n_s8): Likewise. (__arm_vcmpgeq_m_s8): Likewise. (__arm_vcmpgeq_m_n_s8): Likewise. (__arm_vcmpeqq_m_s8): Likewise. (__arm_vcmpeqq_m_n_s8): Likewise. (__arm_vshlq_m_r_s8): Likewise. (__arm_vrshlq_m_n_s8): Likewise. (__arm_vrev64q_m_s8): Likewise. (__arm_vqshlq_m_r_s8): Likewise. (__arm_vqrshlq_m_n_s8): Likewise. (__arm_vqnegq_m_s8): Likewise. (__arm_vqabsq_m_s8): Likewise. (__arm_vnegq_m_s8): Likewise. (__arm_vmvnq_m_s8): Likewise. (__arm_vmlsdavxq_p_s8): Likewise. (__arm_vmlsdavq_p_s8): Likewise. (__arm_vmladavxq_p_s8): Likewise. (__arm_vmladavq_p_s8): Likewise. (__arm_vminvq_p_s8): Likewise. (__arm_vmaxvq_p_s8): Likewise. (__arm_vdupq_m_n_s8): Likewise. (__arm_vclzq_m_s8): Likewise. (__arm_vclsq_m_s8): Likewise. (__arm_vaddvaq_p_s8): Likewise. (__arm_vabsq_m_s8): Likewise. (__arm_vqrdmlsdhxq_s8): Likewise. (__arm_vqrdmlsdhq_s8): Likewise. (__arm_vqrdmlashq_n_s8): Likewise. (__arm_vqrdmlahq_n_s8): Likewise. (__arm_vqrdmladhxq_s8): Likewise. (__arm_vqrdmladhq_s8): Likewise. (__arm_vqdmlsdhxq_s8): Likewise. (__arm_vqdmlsdhq_s8): Likewise. (__arm_vqdmlahq_n_s8): Likewise. (__arm_vqdmladhxq_s8): Likewise. (__arm_vqdmladhq_s8): Likewise. (__arm_vmlsdavaxq_s8): Likewise. (__arm_vmlsdavaq_s8): Likewise. (__arm_vmlasq_n_s8): Likewise. (__arm_vmlaq_n_s8): Likewise. (__arm_vmladavaxq_s8): Likewise. (__arm_vmladavaq_s8): Likewise. (__arm_vsriq_n_s8): Likewise. (__arm_vsliq_n_s8): Likewise. (__arm_vpselq_u16): Likewise. (__arm_vpselq_s16): Likewise. (__arm_vrev64q_m_u16): Likewise. (__arm_vqrdmlashq_n_u16): Likewise. (__arm_vqrdmlahq_n_u16): Likewise. (__arm_vqdmlahq_n_u16): Likewise. (__arm_vmvnq_m_u16): Likewise. (__arm_vmlasq_n_u16): Likewise. (__arm_vmlaq_n_u16): Likewise. (__arm_vmladavq_p_u16): Likewise. (__arm_vmladavaq_u16): Likewise. (__arm_vminvq_p_u16): Likewise. (__arm_vmaxvq_p_u16): Likewise. (__arm_vdupq_m_n_u16): Likewise. (__arm_vcmpneq_m_u16): Likewise. (__arm_vcmpneq_m_n_u16): Likewise. (__arm_vcmphiq_m_u16): Likewise. (__arm_vcmphiq_m_n_u16): Likewise. (__arm_vcmpeqq_m_u16): Likewise. (__arm_vcmpeqq_m_n_u16): Likewise. (__arm_vcmpcsq_m_u16): Likewise. (__arm_vcmpcsq_m_n_u16): Likewise. (__arm_vclzq_m_u16): Likewise. (__arm_vaddvaq_p_u16): Likewise. (__arm_vsriq_n_u16): Likewise. (__arm_vsliq_n_u16): Likewise. (__arm_vshlq_m_r_u16): Likewise. (__arm_vrshlq_m_n_u16): Likewise. (__arm_vqshlq_m_r_u16): Likewise. (__arm_vqrshlq_m_n_u16): Likewise. (__arm_vminavq_p_s16): Likewise. (__arm_vminaq_m_s16): Likewise. (__arm_vmaxavq_p_s16): Likewise. (__arm_vmaxaq_m_s16): Likewise. (__arm_vcmpneq_m_s16): Likewise. (__arm_vcmpneq_m_n_s16): Likewise. (__arm_vcmpltq_m_s16): Likewise. (__arm_vcmpltq_m_n_s16): Likewise. (__arm_vcmpleq_m_s16): Likewise. (__arm_vcmpleq_m_n_s16): Likewise. (__arm_vcmpgtq_m_s16): Likewise. (__arm_vcmpgtq_m_n_s16): Likewise. (__arm_vcmpgeq_m_s16): Likewise. (__arm_vcmpgeq_m_n_s16): Likewise. (__arm_vcmpeqq_m_s16): Likewise. (__arm_vcmpeqq_m_n_s16): Likewise. (__arm_vshlq_m_r_s16): Likewise. (__arm_vrshlq_m_n_s16): Likewise. (__arm_vrev64q_m_s16): Likewise. (__arm_vqshlq_m_r_s16): Likewise. (__arm_vqrshlq_m_n_s16): Likewise. (__arm_vqnegq_m_s16): Likewise. (__arm_vqabsq_m_s16): Likewise. (__arm_vnegq_m_s16): Likewise. (__arm_vmvnq_m_s16): Likewise. (__arm_vmlsdavxq_p_s16): Likewise. (__arm_vmlsdavq_p_s16): Likewise. (__arm_vmladavxq_p_s16): Likewise. (__arm_vmladavq_p_s16): Likewise. (__arm_vminvq_p_s16): Likewise. (__arm_vmaxvq_p_s16): Likewise. (__arm_vdupq_m_n_s16): Likewise. (__arm_vclzq_m_s16): Likewise. (__arm_vclsq_m_s16): Likewise. (__arm_vaddvaq_p_s16): Likewise. (__arm_vabsq_m_s16): Likewise. (__arm_vqrdmlsdhxq_s16): Likewise. (__arm_vqrdmlsdhq_s16): Likewise. (__arm_vqrdmlashq_n_s16): Likewise. (__arm_vqrdmlahq_n_s16): Likewise. (__arm_vqrdmladhxq_s16): Likewise. (__arm_vqrdmladhq_s16): Likewise. (__arm_vqdmlsdhxq_s16): Likewise. (__arm_vqdmlsdhq_s16): Likewise. (__arm_vqdmlahq_n_s16): Likewise. (__arm_vqdmladhxq_s16): Likewise. (__arm_vqdmladhq_s16): Likewise. (__arm_vmlsdavaxq_s16): Likewise. (__arm_vmlsdavaq_s16): Likewise. (__arm_vmlasq_n_s16): Likewise. (__arm_vmlaq_n_s16): Likewise. (__arm_vmladavaxq_s16): Likewise. (__arm_vmladavaq_s16): Likewise. (__arm_vsriq_n_s16): Likewise. (__arm_vsliq_n_s16): Likewise. (__arm_vpselq_u32): Likewise. (__arm_vpselq_s32): Likewise. (__arm_vrev64q_m_u32): Likewise. (__arm_vqrdmlashq_n_u32): Likewise. (__arm_vqrdmlahq_n_u32): Likewise. (__arm_vqdmlahq_n_u32): Likewise. (__arm_vmvnq_m_u32): Likewise. (__arm_vmlasq_n_u32): Likewise. (__arm_vmlaq_n_u32): Likewise. (__arm_vmladavq_p_u32): Likewise. (__arm_vmladavaq_u32): Likewise. (__arm_vminvq_p_u32): Likewise. (__arm_vmaxvq_p_u32): Likewise. (__arm_vdupq_m_n_u32): Likewise. (__arm_vcmpneq_m_u32): Likewise. (__arm_vcmpneq_m_n_u32): Likewise. (__arm_vcmphiq_m_u32): Likewise. (__arm_vcmphiq_m_n_u32): Likewise. (__arm_vcmpeqq_m_u32): Likewise. (__arm_vcmpeqq_m_n_u32): Likewise. (__arm_vcmpcsq_m_u32): Likewise. (__arm_vcmpcsq_m_n_u32): Likewise. (__arm_vclzq_m_u32): Likewise. (__arm_vaddvaq_p_u32): Likewise. (__arm_vsriq_n_u32): Likewise. (__arm_vsliq_n_u32): Likewise. (__arm_vshlq_m_r_u32): Likewise. (__arm_vrshlq_m_n_u32): Likewise. (__arm_vqshlq_m_r_u32): Likewise. (__arm_vqrshlq_m_n_u32): Likewise. (__arm_vminavq_p_s32): Likewise. (__arm_vminaq_m_s32): Likewise. (__arm_vmaxavq_p_s32): Likewise. (__arm_vmaxaq_m_s32): Likewise. (__arm_vcmpneq_m_s32): Likewise. (__arm_vcmpneq_m_n_s32): Likewise. (__arm_vcmpltq_m_s32): Likewise. (__arm_vcmpltq_m_n_s32): Likewise. (__arm_vcmpleq_m_s32): Likewise. (__arm_vcmpleq_m_n_s32): Likewise. (__arm_vcmpgtq_m_s32): Likewise. (__arm_vcmpgtq_m_n_s32): Likewise. (__arm_vcmpgeq_m_s32): Likewise. (__arm_vcmpgeq_m_n_s32): Likewise. (__arm_vcmpeqq_m_s32): Likewise. (__arm_vcmpeqq_m_n_s32): Likewise. (__arm_vshlq_m_r_s32): Likewise. (__arm_vrshlq_m_n_s32): Likewise. (__arm_vrev64q_m_s32): Likewise. (__arm_vqshlq_m_r_s32): Likewise. (__arm_vqrshlq_m_n_s32): Likewise. (__arm_vqnegq_m_s32): Likewise. (__arm_vqabsq_m_s32): Likewise. (__arm_vnegq_m_s32): Likewise. (__arm_vmvnq_m_s32): Likewise. (__arm_vmlsdavxq_p_s32): Likewise. (__arm_vmlsdavq_p_s32): Likewise. (__arm_vmladavxq_p_s32): Likewise. (__arm_vmladavq_p_s32): Likewise. (__arm_vminvq_p_s32): Likewise. (__arm_vmaxvq_p_s32): Likewise. (__arm_vdupq_m_n_s32): Likewise. (__arm_vclzq_m_s32): Likewise. (__arm_vclsq_m_s32): Likewise. (__arm_vaddvaq_p_s32): Likewise. (__arm_vabsq_m_s32): Likewise. (__arm_vqrdmlsdhxq_s32): Likewise. (__arm_vqrdmlsdhq_s32): Likewise. (__arm_vqrdmlashq_n_s32): Likewise. (__arm_vqrdmlahq_n_s32): Likewise. (__arm_vqrdmladhxq_s32): Likewise. (__arm_vqrdmladhq_s32): Likewise. (__arm_vqdmlsdhxq_s32): Likewise. (__arm_vqdmlsdhq_s32): Likewise. (__arm_vqdmlahq_n_s32): Likewise. (__arm_vqdmladhxq_s32): Likewise. (__arm_vqdmladhq_s32): Likewise. (__arm_vmlsdavaxq_s32): Likewise. (__arm_vmlsdavaq_s32): Likewise. (__arm_vmlasq_n_s32): Likewise. (__arm_vmlaq_n_s32): Likewise. (__arm_vmladavaxq_s32): Likewise. (__arm_vmladavaq_s32): Likewise. (__arm_vsriq_n_s32): Likewise. (__arm_vsliq_n_s32): Likewise. (__arm_vpselq_u64): Likewise. (__arm_vpselq_s64): Likewise. (vcmpneq_m_n): Define polymorphic variant. (vcmpneq_m): Likewise. (vqrdmlsdhq): Likewise. (vqrdmlsdhxq): Likewise. (vqrshlq_m_n): Likewise. (vqshlq_m_r): Likewise. (vrev64q_m): Likewise. (vrshlq_m_n): Likewise. (vshlq_m_r): Likewise. (vsliq_n): Likewise. (vsriq_n): Likewise. (vqrdmlashq_n): Likewise. (vqrdmlahq): Likewise. (vqrdmladhxq): Likewise. (vqrdmladhq): Likewise. (vqnegq_m): Likewise. (vqdmlsdhxq): Likewise. (vabsq_m): Likewise. (vclsq_m): Likewise. (vclzq_m): Likewise. (vcmpgeq_m): Likewise. (vcmpgeq_m_n): Likewise. (vdupq_m_n): Likewise. (vmaxaq_m): Likewise. (vmlaq_n): Likewise. (vmlasq_n): Likewise. (vmvnq_m): Likewise. (vnegq_m): Likewise. (vpselq): Likewise. (vqdmlahq_n): Likewise. (vqrdmlahq_n): Likewise. (vqdmlsdhq): Likewise. (vqdmladhq): Likewise. (vqabsq_m): Likewise. (vminaq_m): Likewise. (vrmlaldavhaq): Likewise. (vmlsdavxq_p): Likewise. (vmlsdavq_p): Likewise. (vmlsdavaxq): Likewise. (vmlsdavaq): Likewise. (vaddvaq_p): Likewise. (vcmpcsq_m_n): Likewise. (vcmpcsq_m): Likewise. (vcmpeqq_m_n): Likewise. (vcmpeqq_m): Likewise. (vmladavxq_p): Likewise. (vmladavq_p): Likewise. (vmladavaxq): Likewise. (vmladavaq): Likewise. (vminvq_p): Likewise. (vminavq_p): Likewise. (vmaxvq_p): Likewise. (vmaxavq_p): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmphiq_m_n): Likewise. (vcmphiq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/constraints.md (Rc): Define constraint to check constant is in the range of 0 to 15. (Re): Define constraint to check constant is in the range of 0 to 31. * config/arm/mve.md (VADDVAQ_P): Define iterator. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (mve_vabsq_m_s<mode>): Define RTL pattern. (mve_vaddvaq_p_<supf><mode>): Likewise. (mve_vclsq_m_s<mode>): Likewise. (mve_vclzq_m_<supf><mode>): Likewise. (mve_vcmpcsq_m_n_u<mode>): Likewise. (mve_vcmpcsq_m_u<mode>): Likewise. (mve_vcmpeqq_m_n_<supf><mode>): Likewise. (mve_vcmpeqq_m_<supf><mode>): Likewise. (mve_vcmpgeq_m_n_s<mode>): Likewise. (mve_vcmpgeq_m_s<mode>): Likewise. (mve_vcmpgtq_m_n_s<mode>): Likewise. (mve_vcmpgtq_m_s<mode>): Likewise. (mve_vcmphiq_m_n_u<mode>): Likewise. (mve_vcmphiq_m_u<mode>): Likewise. (mve_vcmpleq_m_n_s<mode>): Likewise. (mve_vcmpleq_m_s<mode>): Likewise. (mve_vcmpltq_m_n_s<mode>): Likewise. (mve_vcmpltq_m_s<mode>): Likewise. (mve_vcmpneq_m_n_<supf><mode>): Likewise. (mve_vcmpneq_m_<supf><mode>): Likewise. (mve_vdupq_m_n_<supf><mode>): Likewise. (mve_vmaxaq_m_s<mode>): Likewise. (mve_vmaxavq_p_s<mode>): Likewise. (mve_vmaxvq_p_<supf><mode>): Likewise. (mve_vminaq_m_s<mode>): Likewise. (mve_vminavq_p_s<mode>): Likewise. (mve_vminvq_p_<supf><mode>): Likewise. (mve_vmladavaq_<supf><mode>): Likewise. (mve_vmladavq_p_<supf><mode>): Likewise. (mve_vmladavxq_p_s<mode>): Likewise. (mve_vmlaq_n_<supf><mode>): Likewise. (mve_vmlasq_n_<supf><mode>): Likewise. (mve_vmlsdavq_p_s<mode>): Likewise. (mve_vmlsdavxq_p_s<mode>): Likewise. (mve_vmvnq_m_<supf><mode>): Likewise. (mve_vnegq_m_s<mode>): Likewise. (mve_vpselq_<supf><mode>): Likewise. (mve_vqabsq_m_s<mode>): Likewise. (mve_vqdmlahq_n_<supf><mode>): Likewise. (mve_vqnegq_m_s<mode>): Likewise. (mve_vqrdmladhq_s<mode>): Likewise. (mve_vqrdmladhxq_s<mode>): Likewise. (mve_vqrdmlahq_n_<supf><mode>): Likewise. (mve_vqrdmlashq_n_<supf><mode>): Likewise. (mve_vqrdmlsdhq_s<mode>): Likewise. (mve_vqrdmlsdhxq_s<mode>): Likewise. (mve_vqrshlq_m_n_<supf><mode>): Likewise. (mve_vqshlq_m_r_<supf><mode>): Likewise. (mve_vrev64q_m_<supf><mode>): Likewise. (mve_vrshlq_m_n_<supf><mode>): Likewise. (mve_vshlq_m_r_<supf><mode>): Likewise. (mve_vsliq_n_<supf><mode>): Likewise. (mve_vsriq_n_<supf><mode>): Likewise. (mve_vqdmlsdhxq_s<mode>): Likewise. (mve_vqdmlsdhq_s<mode>): Likewise. (mve_vqdmladhxq_s<mode>): Likewise. (mve_vqdmladhq_s<mode>): Likewise. (mve_vmlsdavaxq_s<mode>): Likewise. (mve_vmlsdavaq_s<mode>): Likewise. (mve_vmladavaxq_s<mode>): Likewise. * config/arm/predicates.md (mve_imm_15):Define predicate to check the matching constraint Rc. (mve_imm_31): Define predicate to check the matching constraint Re. gcc/testsuite/ChangeLog: 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vpselq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsliq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_n_u8.c: Likewise. |
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Tobias Burnus
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26cbcfe5fc |
Fix libgomp.oacc-fortran/atomic_capture-1.f90
2020-03-18 Julian Brown <julian@codesourcery.com>
Tobias Burnus <tobias@codesourcery.com>
* testsuite/libgomp.oacc-fortran/atomic_capture-1.f90: Really make
it work concurrently.
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David Malcolm
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884d914111 |
analyzer: make summarized dumps more comprehensive
The previous implementation of summarized dumps within region_model::dump_to_pp showed only the "top-level" keys within the current frame and for globals, and thus didn't e.g. show the values of fields of structs, or elements of arrays. This patch rewrites it to gather a vec of representative path_vars for all regions, using this to generate the dump, so that all expressible lvalues ought to make it to the summarized dump. gcc/analyzer/ChangeLog: * region-model.cc: Include "stor-layout.h". (region_model::dump_to_pp): Rather than calling dump_summary_of_map on each of the current frame and the globals, instead get a vec of representative path_vars for all regions, and then dump a summary of all of them. (region_model::dump_summary_of_map): Delete, rewriting into... (region_model::dump_summary_of_rep_path_vars): ...this new function, working on a vec of path_vars. (region_model::set_value): New overload. (region_model::get_representative_path_var): Rename "parent_region" local to "parent_reg" and consolidate with other local. Guard test for grandparent being stack on parent_reg being non-NULL. Move handling for parent being an array_region to within guard for parent_reg being non-NULL. (selftest::make_test_compound_type): New function. (selftest::test_dump_2): New selftest. (selftest::test_dump_3): New selftest. (selftest::test_stack_frames): Update expected output from simplified dump to show "a" and "b" from parent frame and "y" in child frame. (selftest::analyzer_region_model_cc_tests): Call test_dump_2 and test_dump_3. * region-model.h (region_model::set_value): New overload decl. (region_model::dump_summary_of_map): Delete. (region_model::dump_summary_of_rep_path_vars): New. |
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David Malcolm
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f665beeba6 |
analyzer: add test coverage for fixed ICE [PR94047]
PR analyzer/94047 reports an ICE, which turned out to be caused by the erroneous use of TREE_TYPE on the view region's type in region_model::get_representative_path_var that I introduced in r10-7024-ge516294a1acb28aaaad44cfd583cc6a80354044e and fixed in g:787477a226033e36be3f6d16b71be13dd917e982. This patch adds a regression test for the ICE. gcc/testsuite/ChangeLog: PR analyzer/94047 * gcc.dg/analyzer/pr94047.c: New test. |
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David Malcolm
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7d9c107ab1 |
analyzer: introduce noop_region_model_context
tentative_region_model_context and test_region_model_context are both forced to implement numerous pure virtual vfuncs of the abstract region_model_context. This patch adds a noop_region_model_context which provides empty implementations of all of region_model_context's pure virtual functions, and subclasses the above classes from that, rather than from region_model_context directly. gcc/analyzer/ChangeLog: * region-model.h (class noop_region_model_context): New subclass of region_model_context. (class tentative_region_model_context): Inherit from noop_region_model_context rather than from region_model_context; drop redundant vfunc implementations. (class test_region_model_context): Likewise. |
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David Malcolm
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0db2cd1770 |
analyzer: tweaks to exploded_node ctor
I have followup work that touches this, so it's easiest to get this cleanup in first. gcc/analyzer/ChangeLog: * engine.cc (exploded_node::exploded_node): Move implementation here from header; accept point_and_state by const reference rather than by value. * exploded-graph.h (exploded_node::exploded_node): Pass point_and_state by const reference rather than by value. Move body to engine.cc. |
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Jonathan Wakely
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e5de406f99 |
libstdc++ Fix compilation of <stop_token> with Clang
Clang 9 supports C++20 via -std=c++2a but doesn't support three-way comparisons, so <stop_token> fails to compile. When the compiler doesn't support default comparisons, this patch defines operator== and operator!= for the _Stop_state_ref class. That is enough for the header to be compiled with Clang. It allows operator== for stop_token and stop_source to work, but not operator!= because that isn't explicitly defined. * include/std/stop_token (stop_token::_Stop_state_ref): Define comparison operators explicitly if the compiler won't synthesize them. |
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Jonathan Wakely
|
07522ae90b |
libstdc++: Fix compilation with released versions of Clang
Clang 9 supports C++20 via -std=c++2a but doesn't support Concepts, so several of the new additions related to the Ranges library fail to compile with -std=c++2a. The new definition of iterator_traits and the definition of default_sentinel_t are guarded by __cpp_lib_concepts, so check that in addition to __cplusplus > 201703L. * include/bits/stl_algobase.h (__lexicographical_compare_aux): Check __cpp_lib_concepts before using iter_reference_t. * include/bits/stream_iterator.h (istream_iterator): Check __cpp_lib_concepts before using default_sentinel_t. * include/bits/streambuf_iterator.h (istreambuf_iterator): Likewise. |
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Andrew Stubbs
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dbde9e2d59 |
amdgcn: Fix vector compare modes
The GCN VCC register has 64 CC values in one registers, one bit for each vector lane. Previously we avoided problems with invalid optimizations by not declaring a mode for the comparison operators, but it turns out that causes other problems (and build warnings). Instead, the optimization issues can be avoided by setting STORE_REGISTER_VALUE to -1, meaning that all the bits are significant. (It would be better if we could set STORE_REGISTER_VALUE according to the known mask or vector size, but we can't.) 2020-03-18 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode. (vec_cmp<mode>di_dup): Likewise. * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. |
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Andrew Stubbs
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5a80a6c3e5 |
amdgcn: Add cond_add/sub/and/ior/xor for all vector modes
2020-03-18 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". (cond_<expander><mode>): Use VEC_ALLREG_MODE. (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE. |
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Nathan Sidwell
|
11cf25c40e |
PR c++/94147 - mangling of lambdas assigned to globals
This patch implements Jason's suggestion of pushing a lambda scope when parsing a global variable initializer. That bit worked fine, but happened to cause g++.dg/opt/dump1.C to not give any used-but-not-defined warnings. The reason was no_linkage_check, which considers any lambda that has an extra-scope to have linkage. Which is technically correct. Except that we think that all types that have linkage have external linkage. Our representation of linkage and visibility is somewhat inaccurate, particularly when it comes to types. We have TREE_PUBLIC, DECL_EXTERNAL, DECL_VISIBILITY, DECL_COMDAT, DECL_NOT_REALLY_EXTERN. It could really do with a through cleanup, but that won't be a simple task. The best I could come up with was seeing if the extra scope was a VAR_DECL, and if that was TREE_PUBLIC and the var was inline (its COMDATness is sadly not set at that point) or a template instantiation, then the lambda had linkage. Otherwise it's as-if it has no-linkage from the POV of compiler internals. This is an ABI change (so we should document it), but it's changing mangling from an unpredictable (in practice) counter, to something the ABI defines. So I'm not concerned about mangling-changed warnings, or preserving the broken mangling under some ABI selection flag. Code that did this worked by accident within a single TU. It'll continue to work by design there, and across TUs. * parser.c (cp_parser_init_declarator): Namespace-scope variables provide a lambda scope. * tree.c (no_linkage_check): Lambdas with a variable for extra scope have a linkage from the variable. |
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Richard Biener
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1ba9acb11e |
middle-end/94206 fix memset folding to avoid types with padding
This makes sure that the store a memset is folded to uses a type covering all bits. 2020-03-18 Richard Biener <rguenther@suse.de> PR middle-end/94206 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using partial int modes or not mode-precision integer types for the store. * gcc.dg/torture/pr94206.c: New testcase. |
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Jakub Jelinek
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d5029d4594 |
Fix up duplicated duplicated words in comments
Another set of duplicated word fixes for things I've missed last time. These include e.g. *.cc files I forgot about, or duplicated words at the start or end of line. 2020-03-18 Jakub Jelinek <jakub@redhat.com> * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue in a comment. * config/arc/arc.c (frame_stack_add): Likewise. * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): Likewise. * ipa-predicate.c (predicate::remap_after_inlining): Likewise. * tree-ssa-strlen.h (handle_printf_call): Likewise. * tree-ssa-strlen.c (is_strlen_related_p): Likewise. * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. analyzer/ * sm-malloc.cc (malloc_state_machine::on_stmt): Fix up duplicated word issue in a comment. * region-model.cc (region_model::make_region_for_unexpected_tree_code, region_model::delete_region_and_descendents): Likewise. * engine.cc (class exploded_cluster): Likewise. * diagnostic-manager.cc (class path_builder): Likewise. cp/ * constraint.cc (resolve_function_concept_check, subsumes_constraints, strictly_subsumes): Fix up duplicated word issue in a comment. * coroutines.cc (build_init_or_final_await, captures_temporary): Likewise. * logic.cc (dnf_size_r, cnf_size_r): Likewise. * pt.c (append_type_to_template_for_access_check): Likewise. d/ * expr.cc (ExprVisitor::visit (CatAssignExp *)): Fix up duplicated word issue in a comment. * d-target.cc (Target::FPTypeProperties<T>::max): Likewise. fortran/ * class.c (generate_finalization_wrapper): Fix up duplicated word issue in a comment. * trans-types.c (gfc_get_nodesc_array_type): Likewise. |