OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
168,486 Commits 63 Branches 184 Tags 3.1 GiB
92b8603c7c
Commit Graph

168486 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
GCC Administrator
92b8603c7c Daily bump. 
From-SVN: r271275
 2019-05-16 00:16:25 +00:00
Jakub Jelinek
80c1c40acb re PR middle-end/90478 (ICE in emit_case_dispatch_table at gcc/stmt.c:796) 
PR middle-end/90478
	* gcc.dg/tree-ssa/pr90478.c: Add empty dg-options.  Use long long type
	instead of long.

From-SVN: r271271
 2019-05-16 00:43:47 +02:00
Jakub Jelinek
fed2a43c01 omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set max_vf to 1. 
* omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set
	max_vf to 1.
	* omp-expand.c (expand_omp_simd): For if (0) or simdlen (1) clear
	safelen_int and set loop->dont_vectorize.

	* c-c++-common/gomp/simd8.c: New test.

From-SVN: r271270
 2019-05-15 23:42:46 +02:00
Jakub Jelinek
c42b72a7dd re PR debug/90197 (Cannot step through simple loop at -O -g) 
PR debug/90197
	* cp-gimplify.c (genericize_cp_loop): Emit a DEBUG_BEGIN_STMT
	before the condition (or if missing or constant non-zero at the end
	of the loop.  Emit a DEBUG_BEGIN_STMT before the increment expression
	if any.  Don't call protected_set_expr_location on incr if it already
	has a location.

From-SVN: r271269
 2019-05-15 23:41:35 +02:00
Jonathan Wakely
e5d7010bb3 Qualify calls in std::visit and std::visit<R> 
* include/std/variant (visit, visit<R>): Qualify calls to __do_visit.

From-SVN: r271268
 2019-05-15 22:19:39 +01:00
Marek Polacek
47805f5712 CWG 2096 - constraints on literal unions. 
* class.c (check_field_decls): Initialize booleans directly.  A union
	is literal if at least one of its non-static data members is of
	non-volatile literal type.

	* g++.dg/cpp0x/literal-type1.C: New test.

From-SVN: r271267
 2019-05-15 20:42:52 +00:00
Janne Blomqvist
193f241906 Remove translation string markers 
C preprocessor definitions should not be translated.

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

        * parse.c (gfc_parse_file): Remove translation string markers.

From-SVN: r271261
 2019-05-15 22:33:32 +03:00
Janne Blomqvist
0c15ebf1bd Allow opening file on multiple units 
As of Fortran 2018 it's allowed to open the same file on multiple
units.

libgfortran/ChangeLog:

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

	PR fortran/90461
        * io/open.c (new_unit): Don't check if the file is already open
	for F2018.

testsuite/ChangeLog:

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

	PR fortran/90461
        * gfortran.dg/open_errors_2.f90: Add -std=f2008, adjust line number.
	* gfortran.dg/open_errors_3.f90: New test.

From-SVN: r271260
 2019-05-15 21:02:36 +03:00
Uros Bizjak
40c81f845c i386-expand.c (ix86_split_idivmod): Rename signed_p argument to unsigned_p. 
* config/i386/i386-expand.c (ix86_split_idivmod): Rename
	signed_p argument to unsigned_p.  Update all uses for changed polarity.
	* config/i386/i386.md (u_bool): Handle DIV and UDIV RTXes.
	(divmod splitters): Use u_bool macro in the call to ix86_split_idivmod.

From-SVN: r271259
 2019-05-15 19:59:19 +02:00
Paolo Carlini
53f45e3cb9 cp-tree.h (REFERENCE_VLA_OK): Remove. 
2019-05-15  Paolo Carlini  <paolo.carlini@oracle.com>

	* cp-tree.h (REFERENCE_VLA_OK): Remove.
	* lambda.c (build_capture_proxy): Remove use of the above.

From-SVN: r271258
 2019-05-15 17:47:55 +00:00
H.J. Lu
dc90cc8c23 i386: Add tests for MMX intrinsic emulations with SSE 
Test MMX intrinsics with -msse2 in 32-bit mode and -msse2 -mno-mmx in
64-bit mode.

	PR target/89021
	* gcc.target/i386/mmx-vals.h: New file.
	* gcc.target/i386/sse2-mmx-2.c: Likewise.
	* gcc.target/i386/sse2-mmx-3.c: Likewise.
	* gcc.target/i386/sse2-mmx-4.c: Likewise.
	* gcc.target/i386/sse2-mmx-5.c: Likewise.
	* gcc.target/i386/sse2-mmx-6.c: Likewise.
	* gcc.target/i386/sse2-mmx-7.c: Likewise.
	* gcc.target/i386/sse2-mmx-8.c: Likewise.
	* gcc.target/i386/sse2-mmx-9.c: Likewise.
	* gcc.target/i386/sse2-mmx-10.c: Likewise.
	* gcc.target/i386/sse2-mmx-11.c: Likewise.
	* gcc.target/i386/sse2-mmx-12.c: Likewise.
	* gcc.target/i386/sse2-mmx-13.c: Likewise.
	* gcc.target/i386/sse2-mmx-14.c: Likewise.
	* gcc.target/i386/sse2-mmx-15.c: Likewise.
	* gcc.target/i386/sse2-mmx-16.c: Likewise.
	* gcc.target/i386/sse2-mmx-17.c: Likewise.
	* gcc.target/i386/sse2-mmx-18a.c: Likewise.
	* gcc.target/i386/sse2-mmx-18b.c: Likewise.
	* gcc.target/i386/sse2-mmx-18c.c: Likewise.
	* gcc.target/i386/sse2-mmx-19a.c: Likewise.
	* gcc.target/i386/sse2-mmx-18b.c: Likewise.
	* gcc.target/i386/sse2-mmx-19c.c: Likewise.
	* gcc.target/i386/sse2-mmx-19d.c: Likewise.
	* gcc.target/i386/sse2-mmx-19e.c: Likewise.
	* gcc.target/i386/sse2-mmx-20.c: Likewise.
	* gcc.target/i386/sse2-mmx-21.c: Likewise.
	* gcc.target/i386/sse2-mmx-22.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvtpi2ps.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvtps2pi.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvttps2pi.c: Likewise.
	* gcc.target/i386/sse2-mmx-maskmovq.c: Likewise.
	* gcc.target/i386/sse2-mmx-packssdw.c: Likewise.
	* gcc.target/i386/sse2-mmx-packsswb.c: Likewise.
	* gcc.target/i386/sse2-mmx-packuswb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddd.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddq.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddsb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddusb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddusw.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pand.c: Likewise.
	* gcc.target/i386/sse2-mmx-pandn.c: Likewise.
	* gcc.target/i386/sse2-mmx-pavgb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pavgw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pextrw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pinsrw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaddwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaxsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaxub.c: Likewise.
	* gcc.target/i386/sse2-mmx-pminsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pminub.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmovmskb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmulhuw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmulhw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmullw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmuludq.c: Likewise.
	* gcc.target/i386/sse2-mmx-por.c: Likewise.
	* gcc.target/i386/sse2-mmx-psadbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pshufw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pslld.c: Likewise.
	* gcc.target/i386/sse2-mmx-pslldi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllqi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllwi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrad.c: Likewise.
	* gcc.target/i386/sse2-mmx-psradi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psraw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrawi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrld.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrldi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlqi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlwi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubb.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubd.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubusb.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubusw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhdq.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpcklbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckldq.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpcklwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pxor.c: Likewise.

From-SVN: r271254
 2019-05-15 08:39:38 -07:00
H.J. Lu
0cfa5d9c59 i386: Enable TM MMX intrinsics with SSE2 
This patch enables TM MMX intrinsics with SSE2 when MMX is disabled.

	PR target/89021
	* config/i386/i386-builtins.c (bdesc_tm): Enable MMX intrinsics
	with SSE2.

From-SVN: r271253
 2019-05-15 08:33:43 -07:00
H.J. Lu
ecfdb16c54 i386: Allow MMX intrinsic emulation with SSE 
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.

For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.

gcc/

	PR target/89021
	* config/i386/i386-builtin.def: Enable MMX intrinsics with
	SSE/SSE2/SSSE3.
	* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
	Likewise.
	* config/i386/i386-expand.c (ix86_expand_builtin): Allow
	SSE/SSE2/SSSE3 to emulate MMX intrinsics with TARGET_MMX_WITH_SSE.
	* config/i386/mmintrin.h: Only require SSE2 if __MMX_WITH_SSE__
	is defined.

gcc/testsuite/

	PR target/89021
	* gcc.target/i386/pr82483-1.c: Error only on ia32.
	* gcc.target/i386/pr82483-2.c: Likewise.

From-SVN: r271252
 2019-05-15 08:32:33 -07:00
H.J. Lu
d4410ec0ab i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE 
PR target/89021
	* config/i386/mmx.md (*vec_dupv2sf): Changed to
	define_insn_and_split to support SSE emulation.
	(*vec_extractv2sf_0): Likewise.
	(*vec_extractv2sf_1): Likewise.
	(*vec_extractv2si_0): Likewise.
	(*vec_extractv2si_1): Likewise.
	(*vec_extractv2si_zext_mem): Likewise.
	(vec_setv2sf): Also allow TARGET_MMX_WITH_SSE.
	(vec_extractv2sf_1 splitter): Likewise.
	(vec_extractv2sfsf): Likewise.
	(vec_setv2si): Likewise.
	(vec_extractv2si_1 splitter): Likewise.
	(vec_extractv2sisi): Likewise.
	(vec_setv4hi): Likewise.
	(vec_extractv4hihi): Likewise.
	(vec_setv8qi): Likewise.
	(vec_extractv8qiqi): Likewise.
	(vec_extractv2sfsf): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE ix86_expand_vector_extract.
	(vec_extractv2sisi): Likewise.
	(vec_extractv4hihi): Likewise.
	(vec_extractv8qiqi): Likewise.
	(vec_initv2sfsf): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE to ix86_expand_vector_init.
	(vec_initv2sisi): Likewise.
	(vec_initv4hihi): Likewise.
	(vec_initv8qiqi): Likewise.
	(vec_setv2si): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE to ix86_expand_vector_set.
	(vec_setv4hi): Likewise.
	(vec_setv8qi): Likewise.

From-SVN: r271251
 2019-05-15 08:31:18 -07:00
H.J. Lu
e093d046bf i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE 
PR target/89021
	* config/i386/mmx.md (MMXMODE:mov<mode>): Also allow
	TARGET_MMX_WITH_SSE.
	(MMXMODE:*mov<mode>_internal): Likewise.
	(MMXMODE:movmisalign<mode>): Likewise.

From-SVN: r271250
 2019-05-15 08:30:32 -07:00
Uros Bizjak
ebd3c067f0 Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE 
2019-05-15  Uroš Bizjak  <ubizjak@gmail.com>

	PR target/89021
	* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
	* config/i386/sse.md (sse2_cvtpi2pd): Ditto.
	(sse2_cvtpd2pi): Ditto.
	(sse2_cvttpd2pi): Ditto.
	(*vec_concatv2sf_sse4_1): Ditto.
	(*vec_concatv2sf_sse): Ditto.
	(*vec_concatv2si_sse4_1): Ditto.
	(*vec_concatv2si): Ditto.
	(*vec_concatv4si_0): Ditto.
	(*vec_concatv2di_0): Ditto.

From-SVN: r271249
 2019-05-15 08:29:28 -07:00
H.J. Lu
9c1d1db27d i386: Emulate MMX abs<mode>2 with SSE 
Emulate MMX abs<mode>2 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/sse.md (abs<mode>2): Add SSE emulation.

From-SVN: r271248
 2019-05-15 08:28:04 -07:00
H.J. Lu
d3838596c4 i386: Emulate MMX ssse3_palignrdi with SSE 
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_palignrdi): Changed to
	define_insn_and_split to support SSE emulation.

From-SVN: r271247
 2019-05-15 08:27:33 -07:00
H.J. Lu
e8b0e9104f i386: Emulate MMX ssse3_psign<mode>3 with SSE 
Emulate MMX ssse3_psign<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.

From-SVN: r271246
 2019-05-15 08:26:59 -07:00
H.J. Lu
16ed2601ad i386: Emulate MMX pshufb with SSE version 
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
	define_insn_and_split.  Also allow TARGET_MMX_WITH_SSE.  Add
	SSE emulation.

From-SVN: r271245
 2019-05-15 08:26:19 -07:00
H.J. Lu
9c5a353334 i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE 
Emulate MMX ssse3_pmulhrswv4hi3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
	or TARGET_MMX_WITH_SSE.
	(*ssse3_pmulhrswv4hi3): Add SSE emulation.

From-SVN: r271244
 2019-05-15 08:24:44 -07:00
H.J. Lu
6cbd0ef53a i386: Emulate MMX ssse3_pmaddubsw with SSE 
Emulate MMX ssse3_pmaddubsw with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.

From-SVN: r271243
 2019-05-15 08:23:49 -07:00
H.J. Lu
ea25b84870 i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE 
Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):
	Changed to define_insn_and_split to support SSE emulation.

From-SVN: r271242
 2019-05-15 08:23:11 -07:00
H.J. Lu
2da47f31e3 i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE 
Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
	Changed to define_insn_and_split to support SSE emulation.

From-SVN: r271241
 2019-05-15 08:22:39 -07:00
H.J. Lu
84791fca67 i386: Make _mm_empty () as NOP without MMX 
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.

	PR target/89021
	* config/i386/mmx.md (mmx_<emms>): Renamed to ...
	(*mmx_<emms>): This.
	(mmx_<emms>): New expander.

From-SVN: r271240
 2019-05-15 08:22:08 -07:00
H.J. Lu
6624862302 i386: Emulate MMX umulv1siv1di3 with SSE2 
Emulate MMX umulv1siv1di3 with SSE2.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
	support.
	(*sse2_umulv1siv1di3): Add SSE2 emulation.

From-SVN: r271239
 2019-05-15 08:21:39 -07:00
H.J. Lu
2ed7ae1641 i386: Emulate MMX movntq with SSE2 movntidi 
Emulate MMX movntq with SSE2 movntidi.  Only register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.

From-SVN: r271238
 2019-05-15 08:21:04 -07:00
H.J. Lu
018a45bdf3 i386: Emulate MMX mmx_psadbw with SSE 
Emulate MMX mmx_psadbw with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.

From-SVN: r271237
 2019-05-15 08:20:28 -07:00
H.J. Lu
d9d6e621ff i386: Emulate MMX mmx_uavgv4hi3 with SSE 
Emulate MMX mmx_uavgv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
	TARGET_MMX_WITH_SSE.
	(*mmx_uavgv4hi3): Add SSE emulation.

From-SVN: r271236
 2019-05-15 08:19:55 -07:00
H.J. Lu
a899fa3501 i386: Emulate MMX mmx_uavgv8qi3 with SSE 
Emulate MMX mmx_uavgv8qi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
	and TARGET_MMX_WITH_SSE.
	(*mmx_uavgv8qi3): Add SSE emulation.

From-SVN: r271235
 2019-05-15 08:19:19 -07:00
H.J. Lu
55cd237908 i386: Emulate MMX maskmovq with SSE2 maskmovdqu 
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits.  Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.

	PR target/89021
	* config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2
	maskmovdqu for __MMX_WITH_SSE__.

From-SVN: r271234
 2019-05-15 08:18:41 -07:00
H.J. Lu
9377b54a62 i386: Emulate MMX mmx_umulv4hi3_highpart with SSE 
Emulate MMX mmx_umulv4hi3_highpart with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
	TARGET_MMX and TARGET_MMX_WITH_SSE.
	(*mmx_umulv4hi3_highpart): Add SSE emulation.

From-SVN: r271233
 2019-05-15 08:17:25 -07:00
H.J. Lu
73371f6a70 i386: Emulate MMX mmx_pmovmskb with SSE 
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pmovmskb): Changed to
	define_insn_and_split to support SSE emulation.

From-SVN: r271232
 2019-05-15 08:16:27 -07:00
H.J. Lu
18184fdd76 i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE 
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX
	and TARGET_MMX_WITH_SSE.
	(mmx_<code>v8qi3): Likewise.
	(smaxmin:<code>v4hi3): New.
	(umaxmin:<code>v8qi3): Likewise.
	(smaxmin:*mmx_<code>v4hi3): Add SSE emulation.
	(umaxmin:*mmx_<code>v8qi3): Likewise.

From-SVN: r271231
 2019-05-15 08:15:44 -07:00
H.J. Lu
42500d8355 i386: Emulate MMX mmx_pinsrw with SSE 
Emulate MMX mmx_pinsrw with SSE.  Only SSE register destination operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
	TARGET_MMX_WITH_SSE.
	(*mmx_pinsrw): Add SSE emulation.

From-SVN: r271230
 2019-05-15 08:14:03 -07:00
H.J. Lu
f2c2a6fb1e i386: Emulate MMX mmx_pextrw with SSE 
Emulate MMX mmx_pextrw with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.

From-SVN: r271229
 2019-05-15 08:13:31 -07:00
H.J. Lu
b7e97d9a81 i386: Emulate MMX sse_cvtpi2ps with SSE 
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (sse_cvtpi2ps): Changed to
	define_insn_and_split.  Also allow TARGET_MMX_WITH_SSE.  Add
	SSE emulation.

From-SVN: r271228
 2019-05-15 08:12:47 -07:00
H.J. Lu
f3d6634ba3 i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE 
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.

	PR target/89021
	* config/i386/sse.md (sse_cvtps2pi): Add SSE emulation.
	(sse_cvttps2pi): Likewise.

From-SVN: r271227
 2019-05-15 08:12:14 -07:00
H.J. Lu
3d34e8b0ea i386: Emulate MMX pshufw with SSE 
Emulate MMX pshufw with SSE.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
	TARGET_MMX_WITH_SSE.
	(mmx_pshufw_1): Add SSE emulation.
	(*vec_dupv4hi): Changed to define_insn_and_split and also allow
	TARGET_MMX_WITH_SSE to support SSE emulation.

From-SVN: r271226
 2019-05-15 08:11:41 -07:00
H.J. Lu
74e299b929 i386: Emulate MMX vec_dupv2si with SSE 
Emulate MMX vec_dupv2si with SSE.  Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/constraints.md (Yw): New constraint.
	* config/i386/mmx.md (*vec_dupv2si): Changed to
	define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
	support SSE emulation.

From-SVN: r271225
 2019-05-15 08:11:07 -07:00
H.J. Lu
2629da8350 i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE 
Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_eq<mode>3): Also allow
	TARGET_MMX_WITH_SSE.
	(*mmx_eq<mode>3): Also allow TARGET_MMX_WITH_SSE.  Add SSE
	support.
	(mmx_gt<mode>3): Likewise.

From-SVN: r271224
 2019-05-15 08:10:32 -07:00
H.J. Lu
df0e1979a8 i386: Emulate MMX mmx_andnot<mode>3 with SSE 
Emulate MMX mmx_andnot<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_andnot<mode>3): Also allow
	TARGET_MMX_WITH_SSE.  Add SSE support.

From-SVN: r271223
 2019-05-15 08:09:50 -07:00
H.J. Lu
fff6304f52 i386: Emulate MMX <any_logic><mode>3 with SSE 
Emulate MMX <any_logic><mode>3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (any_logic:mmx_<code><mode>3): Also allow
	TARGET_MMX_WITH_SSE.
	(any_logic:<code><mode>3): New.
	(any_logic:*mmx_<code><mode>3): Also allow TARGET_MMX_WITH_SSE.
	Add SSE support.

From-SVN: r271222
 2019-05-15 08:09:19 -07:00
H.J. Lu
5d48867be5 i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE 
Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register
source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_ashr<mode>3): Also allow
	TARGET_MMX_WITH_SSE.  Add SSE emulation.
	(mmx_<shift_insn><mode>3): Likewise.
	(ashr<mode>3): New.
	(<shift_insn><mode>3): Likewise.

From-SVN: r271221
 2019-05-15 08:08:38 -07:00
H.J. Lu
d0e9bf2a6d i386: Emulate MMX mmx_pmaddwd with SSE 
Emulate MMX pmaddwd with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
	(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.  Add SSE support.

From-SVN: r271220
 2019-05-15 08:08:04 -07:00
H.J. Lu
3fdce4b1ef i386: Emulate MMX smulv4hi3_highpart with SSE 
Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
	TARGET_MMX_WITH_SSE.
	(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
	SSE support.

From-SVN: r271219
 2019-05-15 08:07:04 -07:00
H.J. Lu
08266db93f i386: Emulate MMX mulv4hi3 with SSE 
Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_mulv4hi3): Also allow
	TARGET_MMX_WITH_SSE.
	(mulv4hi3): New.
	(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE.  Add SSE
	support.

From-SVN: r271218
 2019-05-15 08:06:28 -07:00
H.J. Lu
1f0dc22ab5 i386: Emulate MMX plusminus/sat_plusminus with SSE 
Emulate MMX plusminus/sat_plusminus with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
	(plusminus:mmx_<plusminus_insn><mode>3): Check
	TARGET_MMX_WITH_SSE.
	(sat_plusminus:mmx_<plusminus_insn><mode>3): Likewise.
	(<plusminus_insn><mode>3): New.
	(*mmx_<plusminus_insn><mode>3): Add SSE emulation.
	(*mmx_<plusminus_insn><mode>3): Likewise.

From-SVN: r271217
 2019-05-15 08:05:48 -07:00
H.J. Lu
6e9fffcf83 i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX 
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX.  For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/i386-expand.c (ix86_split_mmx_punpck): New function.
	* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
	prototype.
	* config/i386/mmx.m (mmx_punpckhbw): Changed to
	define_insn_and_split to support SSE emulation.
	(mmx_punpcklbw): Likewise.
	(mmx_punpckhwd): Likewise.
	(mmx_punpcklwd): Likewise.
	(mmx_punpckhdq): Likewise.
	(mmx_punpckldq): Likewise.

From-SVN: r271216
 2019-05-15 08:05:07 -07:00
H.J. Lu
b74ebb2a36 i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register.  Only SSE register
source operand is allowed.

	PR target/89021
	* config/i386/i386-expand.c (ix86_move_vector_high_sse_to_mmx):
	New function.
	(ix86_split_mmx_pack): Likewise.
	* config/i386/i386-protos.h (ix86_move_vector_high_sse_to_mmx):
	New prototype.
	(ix86_split_mmx_pack): Likewise.
	* config/i386/i386.md (mmx_isa): New.
	(enabled): Also check mmx_isa.
	* config/i386/mmx.md (any_s_truncate): New code iterator.
	(s_trunsuffix): New code attr.
	(mmx_packsswb): Removed.
	(mmx_packssdw): Likewise.
	(mmx_packuswb): Likewise.
	(mmx_pack<s_trunsuffix>swb): New define_insn_and_split to emulate
	MMX packsswb/packuswb with SSE2.
	(mmx_packssdw): Likewise.
	* config/i386/predicates.md (register_mmxmem_operand): New.

Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>

From-SVN: r271215
 2019-05-15 08:04:08 -07:00