Commit Graph

139918 Commits

Author SHA1 Message Date
Maxim Blumenthal 27c4ac7db7 re PR libgomp/66950 (FAIL: libgomp.fortran/examples-4/simd-7.f90 -O0 execution test)
2015-07-22  Maxim Blumenthal  <maxim.blumenthal@intel.com>

	PR libgomp/66950
	* testsuite/libgomp.c/examples-4/simd-7.c (N): Change to 30 from 45.
	(fib_ref): New function.
	(fib): Correct corner cases in the recursion.
	(main): Replace the non-simd loop with fib_ref call.
	* testsuite/libgomp.fortran/examples-4/simd-7.f90: (fib_ref): New
	subroutine.
	(fibonacci): Lower the parameter N to 30.  Correct accordingly check
	for the last array element value.  Replace the non-simd loop with
	fib_ref call.  Remove redundant b_ref array.  Remove the comparison
	of the last array element with according Fibonacci sequence element.
	(fib): Correct corner cases in the recursion.

From-SVN: r226080
2015-07-22 17:19:31 +00:00
Marek Polacek 19e1890350 unpack.c: Use dg-additional-options rather than dg-options.
* gcc.dg/vmx/unpack.c: Use dg-additional-options rather than
	dg-options.

From-SVN: r226078
2015-07-22 16:44:45 +00:00
Ilya Enkovich 65defbee13 re PR driver/66737 (ld: warning: -z bndplt ignored)
PR driver/66737
	* config/i386/linux-common.h (MPX_SPEC): Use linker option
	for 64bit target only.

From-SVN: r226076
2015-07-22 16:24:28 +00:00
Bernd Schmidt ecf6e535fc * config/nvptx/nvptx.c: Expand some comments.
From-SVN: r226075
2015-07-22 15:30:14 +00:00
Mikael Morin 252207bd03 Fix r225926's iso_varying_string ICE regression
PR fortran/61831
	PR fortran/66929
gcc/fortran/
	* trans-array.c (gfc_get_proc_ifc_for_expr): Use esym as procedure
	symbol if available.
gcc/testsuite/
	* gfortran.dg/generic_30.f90: New.

From-SVN: r226074
2015-07-22 15:26:52 +00:00
James Greenhalgh bf976c5824 [Patch ARM/AArch64 obvious] Fix typo: Rename insn_reservation cortex_53_advsimd to cortex_a53_advsimd
gcc/

	* config/arm/cortex-a53 (cortex_53_advsimd): Rename to...
	(cortex_a53_advsimd): ...This.

From-SVN: r226069
2015-07-22 14:15:26 +00:00
Richard Biener 38b52b2fdd genmatch.c (expr::gen_transform): Clarify error message and display location.
2015-07-22  Richard Biener  <rguenther@suse.de>

	* genmatch.c (expr::gen_transform): Clarify error message
	and display location.

From-SVN: r226068
2015-07-22 13:18:47 +00:00
Richard Biener 0889c52f15 genmatch.c (struct operand): Add location member.
2015-07-22  Richard Biener  <rguenther@suse.de>

	* genmatch.c (struct operand): Add location member.
	(predicate, expr, c_expr, capture, if_expr, with_expr): Adjust
	constructors.
	(struct simplify): Remove match_location and result_location
	members.
	(elsehwere): Adjust.

From-SVN: r226067
2015-07-22 13:16:50 +00:00
Prachi Godbole 6dd74463ea Add scheduling for M51xx core family.
gcc/
	* config/mips/m5100.md: New file.
	* config/mips/mips-cpus.def (m5100, m5101): Define.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100.
	* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=m5100 and
	-march=m5101 to -mips32r5.
	(MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float.
	(MIPS_ISA_NAN2008_SPEC): Map -march=m51* to -mnan=2008 if
	!-msoft-float.
	* config/mips/mips.md: Include m5100.md.
	(processor): Add m5100.
	* doc/invoke.texi (-march=@var{arch}): Add m5100, m5101.

From-SVN: r226066
2015-07-22 12:46:09 +00:00
Robert Suchanek 8ced5d2def Add -march=interaptiv.
gcc/
	* config/mips/mips-cpus.def (interaptiv): Define.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=interaptiv to
	-mips32r2.
	(BASE_DRIVER_SELF_SPECS): Likewise but map to -mdsp.
	* doc/invoke.texi (-march=@var{arch}): Add interaptiv.

From-SVN: r226065
2015-07-22 12:45:51 +00:00
Jiong Wang 38996bc957 [AArch64] PR target/63521 Define REG_ALLOC_ORDER
2015-07-22  Jiong Wang  <jiong.wang@arm.com>
 
gcc/
  PR target/63521
  * config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define.
  (HONOR_REG_ALLOC_ORDER): Define.

From-SVN: r226064
2015-07-22 11:41:10 +00:00
Chung-Lin Tang 20ca17e480 linux-atomic.c (<asm/unistd.h>): Remove #include.
2015-07-22  Chung-Lin Tang  <cltang@codesourcery.com>

	libgcc/
	* config/nios2/linux-atomic.c (<asm/unistd.h>): Remove #include.
	(EFAULT,EBUSY,ENOSYS): Delete unused #defines.

From-SVN: r226063
2015-07-22 11:39:30 +00:00
Richard Biener 8bb8e83841 re PR tree-optimization/66952 (wrong code at -O2 and -O3 on x86_64-linux-gnu)
2015-07-22  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/66952
	* tree-ssa-ifcombine.c (pass_tree_ifcombine::execute): For
	blocks we end up executing unconditionally reset all SSA
	info such as range and alignment.
	* tree-ssanames.h (reset_flow_sensitive_info): Declare.
	* tree-ssanames.c (reset_flow_sensitive_info): New function.

	* gcc.dg/torture/pr66952.c: New testcase.

From-SVN: r226062
2015-07-22 11:31:50 +00:00
Charles Baylis b1db706aba aarch64-simd.md (vec_store_lanesoi_lane<mode>): Fix typo in attribute.
2015-07-22  Charles Baylis  <charles.baylis@linaro.org>

	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): Fix
	typo in attribute.

From-SVN: r226061
2015-07-22 10:56:40 +00:00
Richard Biener d3b0b6921f genmatch.c (parser::parse_result): Properly handle match with result operands and conditions.
2015-07-22  Richard Biener  <rguenther@suse.de>

	* genmatch.c (parser::parse_result): Properly handle
	match with result operands and conditions.

From-SVN: r226060
2015-07-22 10:48:11 +00:00
Charles Baylis 4d0a023751 re PR target/63870 ([Aarch64] [ARM] Errors in use of NEON intrinsics are reported incorrectly)
gcc/ChangeLog:

2015-07-22  Charles Baylis  <charles.baylis@linaro.org>

	PR target/63870
	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
	Add qualifier_struct_load_store_lane_index.
	(aarch64_types_loadstruct_lane_qualifiers): Use
	qualifier_struct_load_store_lane_index for lane index argument for
	last argument.
	(aarch64_types_storestruct_lane_qualifiers): Ditto.
	(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_args): Add new argument describing mode of
	builtin. Check lane bounds for arguments with
	SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
	if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Handle arguments with
	qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
	aarch64_simd_expand_args.
	* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
	vst[234]_lane with BUILTIN_VALLDIF.
	* config/aarch64/aarch64-simd.md:
	(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
	endianness reversal on lane index.
	(aarch64_vec_load_lanesci_lane<mode>): Ditto.
	(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
	(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator.
	(vec_store_lanesci_lane<mode>): Ditto.
	(vec_store_lanesxi_lane<mode>): Ditto.
	(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
	reversal of lane index.
	(aarch64_ld3_lane<mode>): Ditto.
	(aarch64_ld4_lane<mode>): Ditto.
	(aarch64_st2_lane<mode>): Ditto.
	(aarch64_st3_lane<mode>): Ditto.
	(aarch64_st4_lane<mode>): Ditto.
	* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
	to qmode. Add new mode parameter. Update uses.
       	(__LD3_LANE_FUNC): Ditto.
	(__LD4_LANE_FUNC): Ditto.
	(__ST2_LANE_FUNC): Ditto.
	(__ST3_LANE_FUNC): Ditto.
	(__ST4_LANE_FUNC): Ditto.

gcc/testsuite/ChangeLog:

2015-07-22  Charles Baylis  <charles.baylis@linaro.org>

        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c: New
	test.
        * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c: New
	test.

From-SVN: r226059
2015-07-22 10:44:16 +00:00
Jonathan Wakely ebaec5f079 invoke.texi (Language Independent Options): Rename node to Diagnostic Message Formatting Options.
* doc/invoke.texi (Language Independent Options): Rename node to
	Diagnostic Message Formatting Options.

From-SVN: r226058
2015-07-22 10:00:16 +01:00
GCC Administrator 21b13185d7 Daily bump.
From-SVN: r226057
2015-07-22 00:16:13 +00:00
Paolo Carlini faa16e4405 decl.c (grokdeclarator): For an erroneous template parameter propagate error_mark_node as type.
/cp
2015-07-21  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl.c (grokdeclarator): For an erroneous template parameter
	propagate error_mark_node as type.

/testsuite
2015-07-21  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/template/crash81.C: Update.

From-SVN: r226054
2015-07-21 20:51:28 +00:00
Vladimir Makarov 6998b929fa re PR ipa/66424 (wrong code at -O2 and -O3 on x86_64-linux-gnu in 32-bit mode)
2015-07-21  Vladimir Makarov  <vmakarov@redhat.com>

	PR ipa/66424.
	* lra-remat.c (operand_to_remat): Prevent using insns with input
	subregs processed separately by IRA.

2015-07-21  Vladimir Makarov  <vmakarov@redhat.com>

	PR ipa/66424.
	* gcc.target/i386/pr66424.c: New.

From-SVN: r226053
2015-07-21 19:54:23 +00:00
Andrew MacLeod f9ffade09c ssa-iterators.h (has_zero_uses, [...]): Implement as straight loops.
2015-07-21  Andrew MacLeod  <amacleod@redhat.com>

	* ssa-iterators.h (has_zero_uses, has_single_use): Implement as
	straight loops.
	(single_imm_use): Check for iterator node.
	(num_imm_uses): Likewise.
	* tree-ssa-operands.c (has_zero_uses_1): Delete.
	(single_imm_use_1): Check for iterator node.

From-SVN: r226051
2015-07-21 19:15:13 +00:00
Mike Frysinger 324000329b configure.ac: Add check for new options in isl-0.15.
* configure.ac: Add check for new options in isl-0.15.
	* config.in, configure: Rebuilt.
	* graphite-blocking.c: Include <isl/constraint.h>
	* graphite-interchange.c,  graphite-poly.c: Likewise.
	* graphhite-scop-detection.c, graphite-sese-to-poly.c: Likewise.
	* graphite.c: Likewise.
	* graphite-isl-ast-to-gimple.c: Include <isl/constraint.h> and
	<isl/union_set.h>.
	* graphite-dependences.c: Include <isl/constraint.h>.
	(max_number_of_out_dimensions): Returns isl_stat.
	(extend_schedule_1): Likewise
	(extend_schedule): Corresponding changes.
	* graphite-optimize-isl.c: Include <isl/constraint.h> and
	<isl/union_set.h>.
	(getSingleMap): Change return type of isl_stat.
	(optimize_isl): Conditionally use
	isl_options_set_schedule_serialize_sccs.
	* graphite-poly.h (isl_stat, isl_stat_ok): Define fallbacks
	if not HAVE_ISL_OPTIONS_SET_SCHEDULE_SERIALIZE_SCCS.

Co-Authored-By: Bernhard Reutner-Fischer <aldot@gcc.gnu.org>

From-SVN: r226050
2015-07-21 12:33:35 -06:00
Georg-Johann Lay 1f82f1245d re PR target/66956 ([avr] Using 32*32=64 multiplicatiion (umulsidi3) for 32=32*32 without MUL.)
PR target/66956
	* config/avr/avr-dimode.md (<extend_u>mulsidi3_insn)
	(<extend_u>mulsidi3): Don't use if !AVR_HAVE_MUL.

From-SVN: r226046
2015-07-21 17:25:48 +00:00
Alex Velenko 82f04ea072 thumb-bitfld1.c (foo): Add explicit return type.
2015-07-21  Alex Velenko  <Alex.Velenko@arm.com>

	* gcc.target/arm/thumb-bitfld1.c (foo): Add explicit return type.

From-SVN: r226043
2015-07-21 14:29:08 +00:00
Richard Biener 2d79964613 re PR tree-optimization/66948 (Performance regression in bit manipulation code)
2015-07-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/66948
	* genmatch.c (capture_info::walk_match): Also recurse to
	captures.  Properly compute expr state from captures of
	captures.
	* match.pd: Add single-use guards to
	(X & C2) >> C1 into (X >> C1) & (C2 >> C1) transform.

From-SVN: r226041
2015-07-21 14:03:57 +00:00
Nathan Sidwell 22be23495a target.c (gomp_offload_image_to_device): Rename to ...
libgomp/
	* target.c (gomp_offload_image_to_device): Rename to ...
	(gomp_load_image_to_device): ... here.
	(GOMP_offload_register): Adjust call.
	(gomp_init_device): Likewise.
	(gomp_unload_image_from_device): New.  Broken out of ...
	(GOMP_offload_unregister): ... here.  Call it.
	(gomp_unload_device): New.
	* libgomp.h (gomp_unload_device): Declare.
	* oacc-init.c (acc_shutdown_1): Unload from device before deleting
	mem maps.

	gcc/
	* config/nvptx/mkoffload.c (process): Add static destructor call.

From-SVN: r226039
2015-07-21 13:30:06 +00:00
Mikael Morin c5189d8e67 Fix r225926's broken testcase
gcc/testsuite/
	PR fortran/61831
	* gfortran.dg/derived_constructor_comps_6.f90: Fix dg directive.
	Drop address sanitization.

From-SVN: r226038
2015-07-21 11:33:15 +00:00
Alex Velenko ceb2acf21a split-live-ranges-for-shrink-wrap.c (dg-skip-if): Skip -march=armv4t.
2015-07-21  Alex Velenko  <Alex.Velenko@arm.com>
gcc/testsuite/
        * gcc.target/arm/split-live-ranges-for-shrink-wrap.c (dg-skip-if):
	Skip -march=armv4t.
        (dg-additional-options): Set armv5t flag.

From-SVN: r226036
2015-07-21 10:33:42 +00:00
Mikael Morin 04ef2474a1 Fix ChangeLog of r225926 (PR fortran/61831)
From-SVN: r226033
2015-07-21 10:03:00 +00:00
Marek Polacek f68dd0a957 unpack-be-order.c: Use -Wno-shift-overflow.
* gcc.dg/vmx/unpack-be-order.c: Use -Wno-shift-overflow.
	* gcc.dg/vmx/unpack.c: Likewise.
	* gcc.target/powerpc/quad-atomic.c: Likewise.

From-SVN: r226032
2015-07-21 10:01:53 +00:00
Kyrylo Tkachov e4e96a4f37 [match.pd] PR middle-end/66915 Restrict A - B -> A + (-B) to non-fixed-point types
PR middle-end/66915
	* match.pd (A - B -> A + (-B)): Don't allow folding
	when type if a fixed-point type.

From-SVN: r226028
2015-07-21 08:26:32 +00:00
GCC Administrator 2ac74346d8 Daily bump.
From-SVN: r226026
2015-07-21 00:16:11 +00:00
DJ Delorie 840cdb80d6 rl78-real.md (andqi3_real): Expand operands for clr1.
* config/rl78/rl78-real.md (andqi3_real): Expand operands for clr1.
(iorqi3_real): Likewise for set1.

From-SVN: r226023
2015-07-20 19:21:43 -04:00
Jason Merrill 3a353ff584 * include/bits/c++config: Fix abi_tag in special modes.
From-SVN: r226022
2015-07-20 18:39:54 -04:00
Uros Bizjak 73c581fbd1 i386.c (ix86_md_asm_adjust): Handle DImode dest_mode for !TARGET_64BIT.
* config/i386/i386.c (ix86_md_asm_adjust): Handle DImode dest_mode
	for !TARGET_64BIT.

testsuite/ChangeLog:

	* gcc.target/i386/asm-flag-5.c (f_ll): New.

From-SVN: r226017
2015-07-20 20:52:12 +02:00
Aditya Kumar 236d2dc4b8 add missing changelog
From-SVN: r226015
2015-07-20 18:05:16 +00:00
Aditya Kumar 050e1371a1 Refactor graphite-isl-ast-to-gimple.c
Refactor graphite-isl-ast-to-gimple.c:
Refactor so that each function can access 'region'. This will help
maintain a parameter rename_map within a region. No functional change intended.
This patch will be followed by another set of patches
where translate_isl_ast_to_gimple::region is used to keep parameters which need
renaming. Since we are planning to remove limit_scops, we now have to maintain a
set of parameters which needs renaming. This refactoring helps avoid passing
`region' to all the functions in this file.

It passes bootstrap and regtest.

gcc/ChangeLog:

2015-07-19  Aditya Kumar  <hiraditya@msn.com>

        * graphite-isl-ast-to-gimple.c:
	Refactor so that each function can access 'region'. This will help
	maintain a parameter rename_map within a region.

From-SVN: r226014
2015-07-20 18:02:49 +00:00
Nathan Sidwell a051317b73 Missed a difference between gomp4 and trunk
From-SVN: r226012
2015-07-20 17:38:49 +00:00
Nathan Sidwell a091118d2c oacc-parallel.c (GOACC_parallel): Move variadic handling into wait=-specific if.
* oacc-parallel.c (GOACC_parallel): Move variadic handling into
	wait=-specific if.
	(GOACC_enter_exit_data, GOACC_update): Use consistent num_waits
	!=0 condition.
	(goacc_waits): Move !num_waits handling to ...
	(GOACC_wait): ... here, the only caller that might have zero waits.

From-SVN: r226011
2015-07-20 17:31:46 +00:00
Ian Lance Taylor 53c1201606 compiler: Create dummy labels for blank labels.
Fixes golang/go#11591.
    
    Reviewed-on: https://go-review.googlesource.com/12043

From-SVN: r226009
2015-07-20 17:25:24 +00:00
Ian Lance Taylor 57c7a33b97 compiler: Remove unnecessary check for GCC-specific issue.
Reviewed-on: https://go-review.googlesource.com/11800

    compiler: remove name of unused parameter to avoid warning
    
    Reviewed-on: https://go-review.googlesource.com/12367

From-SVN: r226007
2015-07-20 16:47:24 +00:00
Segher Boessenkool 824478c04c * config/rs6000/rs6000.md (*lt0_disi): New.
From-SVN: r226006
2015-07-20 18:32:55 +02:00
Segher Boessenkool 7fc5cca388 re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)
PR target/66217
	* config/rs6000/constraints.md ("S", "T", "t"): Delete.  Update
	"available letters" comment.
	* config/rs6000/predicates.md (mask_operand, mask_operand_wrap,
	mask64_operand, mask64_2_operand, any_mask_operand, and64_2_operand,
	and_2rld_operand):  Delete.
	(and_operand): Adjust.
	(rotate_mask_operator): New.
	* config/rs6000/rs6000-protos.h (build_mask64_2_operands,
	includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p,
	includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB,
	extract_ME): Delete.
	(rs6000_is_valid_mask, rs6000_is_valid_and_mask,
	rs6000_is_valid_shift_mask, rs6000_is_valid_insert_mask,
	rs6000_insn_for_and_mask, rs6000_insn_for_shift_mask,
	rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and,
	rs6000_emit_2insn_and): New.
	* config/rs6000/rs6000.c (num_insns_constant): Adjust.
	(build_mask64_2_operands, includes_lshift_p, includes_rshift_p,
	includes_rldic_lshift_p, includes_rldicr_lshift_p,
	insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete.
	(rs6000_is_valid_mask, rs6000_is_valid_and_mask,
	rs6000_insn_for_and_mask, rs6000_is_valid_shift_mask,
	s6000_insn_for_shift_mask, rs6000_is_valid_insert_mask,
	rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and,
	rs6000_emit_2insn_and): New.
	(print_operand) <'b', 'B', 'm', 'M', 's', 'S', 'W'>: Delete.
	(rs6000_rtx_costs) <CONST_INT>: Delete mask_operand and mask64_operand
	handling.
	<NOT>: Don't fall through to next case.
	<AND>: Handle the various rotate-and-mask cases directly.
	<IOR>: Always cost as one insn.
	* config/rs6000/rs6000.md (splitter for bswap:SI): Adjust.
	(and<mode>3): Adjust expander for the new patterns.
	(and<mode>3_imm, and<mode>3_imm_dot, and<mode>3_imm_dot2,
	and<mode>3_imm_mask_dot, and<mode>3_imm_mask_dot2): Adjust condition.
	(*and<mode>3_imm_dot_shifted): New.
	(*and<mode>3_mask): Delete, rewrite as ...
	(and<mode>3_mask): ... New.
	(*and<mode>3_mask_dot, *and<mode>3_mask_dot): Rewrite.
	(andsi3_internal0_nomc): Delete.
	(*andsi3_internal6): Delete.
	(*and<mode>3_2insn): New.
	(insv, insvsi_internal, *insvsi_internal1, *insvsi_internal2,
	*insvsi_internal3, *insvsi_internal4, *insvsi_internal5,
	*insvsi_internal6, insvdi_internal, *insvdi_internal2,
	*insvdi_internal3): Delete.
	(*rotl<mode>3_mask, *rotl<mode>3_mask_dot, *rotl<mode>3_mask_dot2,
	*rotl<mode>3_insert, *rotl<mode>3_insert_2, *rotl<mode>3_insert_3,
	*rotl<mode>3_insert_4, two splitters for multi-precision shifts,
	*ior<mode>_mask): New.
	(extzv, extzvdi_internal, *extzvdi_internal1, *extzvdi_internal2,
	*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2,
	*ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2,
	*lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2):
	Delete.
	(ashr<mode>3): Delete expander.
	(*ashr<mode>3): Rename to ...
	(ashr<mode>3): ... This.
	(ashrdi3_no_power, *ashrdisi3_noppc64be): Delete.
	(*rotldi3_internal4, *rotldi3_internal5 and split,
	*rotldi3_internal6 and split, *ashldi3_internal4, ashldi3_internal5
	and split, *ashldi3_internal6 and split, *ashldi3_internal7,
	ashldi3_internal8 and split, *ashldi3_internal9 and split): Delete.
	(*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): Delete.
	(splitter for loading a mask): Adjust.
	* doc/md.texi (Machine Constraints): Remove q, S, T, t constraints.

From-SVN: r226005
2015-07-20 18:30:56 +02:00
Nathan Sidwell f3e9a059a7 plugin-nvptx.c (struct targ_fn_descriptor): Move later.
* plugin/plugin-nvptx.c (struct targ_fn_descriptor): Move later.
	(struct ptx_image_data): Move earlier, add fns field.
	(struct ptx_device): Add images and image_lock fields.
	(ptx_images, ptx_image_lock): Delete.
	(nvptx_open_device): Initialize images and image_lock fields.
	(nvptx_close_device): Destroy image_lock.
	(GOMP_OFFLOAD_load_image): Register image to device-specific fields.
	(GOMP_OFFLOAD_unload_image): Unregister image from device-specific
	fields.

From-SVN: r226004
2015-07-20 16:17:57 +00:00
Marek Polacek dd5bc4becd genemit.c (print_code, [...]): Remove declarations.
* genemit.c (print_code, gen_exp, gen_insn, gen_expand, gen_split,
	output_add_clobbers, output_added_clobbers_hard_reg_p,
	gen_rtx_scratch): Remove declarations.

From-SVN: r226003
2015-07-20 15:57:19 +00:00
Jiong Wang 4d05408430 [AArch64][testcase] Restrict got_mem_hoist_1.c with small memory model
From-SVN: r225999
2015-07-20 14:33:49 +00:00
Marek Polacek 451b5e4830 re PR c++/55095 (Wshift-overflow)
PR c++/55095
	* c-common.c (c_fully_fold_internal): Warn about left shift overflows.
	Use EXPR_LOC_OR_LOC.
	(maybe_warn_shift_overflow): New function.
	* c-common.h (maybe_warn_shift_overflow): Declare.
	* c-opts.c (c_common_post_options): Set warn_shift_overflow.
	* c.opt (Wshift-overflow): New option.

	* c-typeck.c (digest_init): Pass OPT_Wpedantic to pedwarn_init.
	(build_binary_op): Warn about left shift overflows.

	* typeck.c (cp_build_binary_op): Warn about left shift overflows.

	* doc/invoke.texi: Document -Wshift-overflow and -Wshift-overflow=.

	* c-c++-common/Wshift-overflow-1.c: New test.
	* c-c++-common/Wshift-overflow-2.c: New test.
	* c-c++-common/Wshift-overflow-3.c: New test.
	* c-c++-common/Wshift-overflow-4.c: New test.
	* c-c++-common/Wshift-overflow-5.c: New test.
	* g++.dg/cpp1y/left-shift-1.C: New test.
	* gcc.dg/c90-left-shift-2.c: New test.
	* gcc.dg/c90-left-shift-3.c: New test.
	* gcc.dg/c99-left-shift-2.c: New test.
	* gcc.dg/c99-left-shift-3.c: New test.
	* gcc.dg/pr40501.c: Use -Wno-shift-overflow.
	* gcc.c-torture/execute/pr40386.c: Likewise.
	* gcc.dg/vect/pr33373.c: Likewise.
	* gcc.dg/vect/vect-shift-2-big-array.c: Likewise.
	* gcc.dg/vect/vect-shift-2.c: Likewise.

Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>

From-SVN: r225998
2015-07-20 13:43:45 +00:00
Kyrylo Tkachov 7040e90366 [simplify-rtx][2/2] Simplify - (y ? -x : x) -> (!y ? -x : x)
* simplify-rtx.c (simplify_unary_operation_1, NEG case):
	(neg (x ? (neg y) : y)) -> !x ? (neg y) : y.

	* gcc.target/aarch64/neg_abs_1.c: New test.

From-SVN: r225997
2015-07-20 12:51:45 +00:00
Kyrylo Tkachov 232c93296d [PATCH][combine][1/2] Try to simplify before substituting
* combine.c (combine_simplify_rtx): Move simplification step
	before various transformations/substitutions.

From-SVN: r225996
2015-07-20 12:49:36 +00:00
Mikhail Maltsev df2a7a38f6 Fix partial specialization syntax of wide int traits.
gcc/
	* wide-int.h (struct binary_traits): Fix partial specialization syntax.
	(struct int_traits): Likewise.

From-SVN: r225993
2015-07-20 05:30:12 +00:00