Commit Graph

30334 Commits

Author SHA1 Message Date
Aaron Sawdey 3095f65123 re PR target/79170 (memcmp builtin expansion sequence can overflow)
2017-01-27  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	PR target/79170
	* gcc.dg/memcmp-1.c: Improved to catch failures seen in PR 79170.

2017-01-27  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	PR target/79170
	* config/rs6000/altivec.md (*setb_internal): Rename to setb_signed.
	(setb_unsigned) New pattern for setb with CCUNS.
	* config/rs6000/rs6000.c (expand_block_compare): Use a different
	subfc./subfe sequence to avoid overflow problems.  Generate a
	shorter sequence with cmpld/setb for power9.
	* config/rs6000/rs6000.md (subf<mode>3_carry_dot2): Add a new pattern
	for generating subfc. instruction.
	(cmpstrsi): Add TARGET_POPCNTD predicate as the generate sequence
	now uses this instruction.

From-SVN: r245041
2017-01-30 17:24:24 -06:00
Martin Liska 8fd23c8e9f Fix aarch64 PGO bootstrap (bootstrap/78985)
2017-01-30  Martin Liska  <mliska@suse.cz>

	PR bootstrap/78985
	* config/aarch64/cortex-a57-fma-steering.c (func_fma_steering::analyze):
	Initialize variables with NULL value.

From-SVN: r245030
2017-01-30 15:16:33 +00:00
Richard Earnshaw bdef2c4ea8 re PR target/79260 (missing header files for plugins: arm-isa.h, arm-flags.h)
PR target/79260
	* config.gcc (arm*-*-*): Add arm/arm-flags.h and arm/arm-isa.h to
	tm_p_file.
	* arm/arm-protos.h: Don't directly include arm-flags.h and arm-isa.h.

From-SVN: r245029
2017-01-30 14:39:50 +00:00
Dominik Vogt ab4be5d1be S/390: PR target/79240: Fix assertion in s390_extzv_shift_ok.
2017-01-30  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	PR target/79240
	* config/s390/s390.md ("*r<noxa>sbg_<mode>_srl_bitmask")
	("*r<noxa>sbg_<mode>_sll_bitmask")
	("*extzv_<mode>_srl<clobbercc_or_nocc>")
	("*extzv_<mode>_sll<clobbercc_or_nocc>"):
	Use contiguous_bitmask_nowrap_operand.

2017-01-30  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	PR target/79240
	* gcc.target/s390/pr79240.c: New test.

From-SVN: r245022
2017-01-30 09:54:58 +00:00
Bill Schmidt 6687d58dbc re PR target/79268 (Wrong code generation for vec_xl and vec_xst intrinsics)
[gcc]

2017-01-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/79268
	* config/rs6000/altivec.h (vec_xl): Revise #define.
	(vec_xst): Likewise.

[gcc/testsuite]

2017-01-29  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/79268
	* gcc.target/powerpc/pr79268.c: New file.
	* gcc.target/powerpc/vsx-elemrev-1.c: Delete file.
	* gcc.target/powerpc/vsx-elemrev-2.c: Likewise.
	* gcc.target/powerpc/vsx-elemrev-3.c: Likewise.
	* gcc.target/powerpc/vsx-elemrev-4.c: Likewise.

From-SVN: r245021
2017-01-30 03:32:59 +00:00
Uros Bizjak 7b4bc98402 i386.c (print_reg): Use REGNO instead of true_regnum.
* config/i386/i386.c (print_reg): Use REGNO instead of true_regnum.

From-SVN: r245009
2017-01-28 19:43:56 +01:00
Richard Earnshaw 6ca513f9b2 [ARM] Fix PR target/79239 - unrecognized insn after pragma gcc pop_options
{committed for rearnsha}

It turns out that because the compiler uses a hash table to save the
cl_target_option structures it is unsafe to modify the result of
build_target_option_node() (doing so will cause the hash lookup to
fail).  This PR was due to not properly understanding this limitation.

The fix is to create temporary copies of the cl_target_option nodes for
use during target option processing and then only creating the tree node
once the options have been suitably modified.

gcc:
        PR target/79239
        * arm.c (arm_option_override): Don't call build_target_option_node
        until after doing all option overrides.
        (arm_valid_target_attribute_tree): Likewise.

gcc/testsuite:
        * gcc.target/arm/pr79239.c: New test.

From-SVN: r244965
2017-01-27 11:22:30 +00:00
Dominik Vogt d876f5cd02 S/390: Fix matching setmem_long_and*.
The attached patch reactivates the setmem_long_and* patterns on S/390
that have not been generated for a while.

gcc/ChangeLog:

2017-01-27  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.md ("*setmem_long_and")
	("*setmem_long_and_31z"): Use zero_extend instead of and.

gcc/testsuite/ChangeLog:

2017-01-27  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* gcc.target/s390/md/setmem_long-1.c: Remove xfail, skip with -O0.

From-SVN: r244963
2017-01-27 08:07:26 +00:00
Carl Love 0277816607 rs6000-c (altivec_overloaded_builtins): Remove bogus entries for the P8V_BUILTIN_VEC_VGBBD built-ins
gcc/ChangeLog:

2017-01-26  Carl Love  <cel@us.ibm.com>

        * config/rs6000/rs6000-c (altivec_overloaded_builtins): Remove
        bogus entries for the P8V_BUILTIN_VEC_VGBBD built-ins

From-SVN: r244943
2017-01-26 17:39:38 +00:00
Jakub Jelinek b5f75f0b64 avx512fintrin.h (_ktest_mask16_u8, [...]): Move to ...
* config/i386/avx512fintrin.h (_ktest_mask16_u8,
	_ktestz_mask16_u8, _ktestc_mask16_u8, _kadd_mask16): Move to ...
	* config/i386/avx512dqintrin.h (_ktest_mask16_u8,
	_ktestz_mask16_u8, _ktestc_mask16_u8, _kadd_mask16): ... here.
	* config/i386/i386-builtin.def (__builtin_ia32_ktestchi,
	__builtin_ia32_ktestzhi, __builtin_ia32_kaddhi): Use
	OPTION_MASK_ISA_AVX512DQ instead of OPTION_MASK_ISA_AVX512F.
	* config/i386/sse.md (SWI1248_AVX512BWDQ2): New mode iterator.
	(kadd<mode>, ktest<mode>): Use it instead of SWI1248_AVX512BWDQ.
testsuite/
	* gcc.target/i386/avx512f-kaddw-1.c: Renamed to ...
	* gcc.target/i386/avx512dq-kaddw-1.c: ... this.  New test.  Replace
	avx512f with avx512dq.
	* gcc.target/i386/avx512f-ktestw-1.c: Renamed to ...
	* gcc.target/i386/avx512dq-ktestw-1.c: ... this.  New test.  Replace
	avx512f with avx512dq.
	* gcc.target/i386/avx512f-ktestw-2.c: Renamed to ...
	* gcc.target/i386/avx512dq-ktestw-2.c: ... this.  New test.  Replace
	avx512f with avx512dq.

From-SVN: r244929
2017-01-26 13:24:58 +01:00
Jakub Jelinek 68edb9bafe update-copyright.py: Add libhsail-rt to self.default_dirs and call self.add_dir on it.
contrib/
	* update-copyright.py: Add libhsail-rt to self.default_dirs
	and call self.add_dir on it.  Add Intel Corporation to external
	authors.
gcc/
	* brig-builtins.def: Update copyright years.
	* config/arm/arm_acle_builtins.def: Update copyright years.
gcc/brig/
	Update copyright years.
gcc/testsuite/
	* brig.dg/dg.exp: Update copyright years.
	* lib/brig-dg.exp: Update copyright years.
	* lib/brig.exp: Update copyright years.
libhsail-rt/
	Update copyright years.
libstdc++-v3/
	* libsupc++/eh_atomics.h: Update copyright years.
	* testsuite/20_util/unique_ptr/cons/default.cc: Update copyright years.

From-SVN: r244919
2017-01-26 09:24:22 +01:00
Michael Meissner b5aa1281e1 re PR target/79179 (PowerPC64: -mcpu=power9 creates stxsd with bad offset)
[gcc]
2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79179
	* config/rs6000/vsx.md (vsx_extract_<mode>_store): Use wY
	constraint instead of o for the stxsd instruction.

[gcc/testsuite]
2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79179
	* gcc.target/powerpc/pr79179.c: New test.

From-SVN: r244917
2017-01-26 04:16:11 +00:00
Carl Love 5332c89ea0 rs6000-c (altivec_overloaded_builtins): Fix order of entries for ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD.
gcc/ChangeLog:

2017-01-25  Carl Love  <cel@us.ibm.com>

        * config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
        of entries for ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD.

gcc/testsuite/ChangeLog:

2017-01-25  Carl Love  <cel@us.ibm.com>
        * gcc.target/powerpc/builtins-3-p8.c:  Add missing tests for the
        vec_packs built-ins

From-SVN: r244904
2017-01-25 16:23:48 +00:00
Kyrylo Tkachov 9aa483a2d8 [ARM] PR target/79145 Fix xordi3 expander for immediate operands in iWMMXt
PR target/79145
	* config/arm/arm.md (xordi3): Force constant operand into a register
	for TARGET_IWMMXT.

	* gcc.target/arm/pr79145.c: New test.

From-SVN: r244894
2017-01-25 11:10:30 +00:00
Eric Botcazou b20ba138ef re PR target/77439 (wrong code for sibcall with longcall, APCS frame and VFP)
PR target/77439
	* config/arm/arm.c (arm_function_ok_for_sibcall): Add back restriction
	for long calls with APCS frame and VFP.

From-SVN: r244879
2017-01-24 17:15:02 +00:00
Jeff Law 82b239054d microblaze.h (ASM_FORMAT_PRIVATE_NAME): Increase buffer size.
* config/microblaze/microblaze.h (ASM_FORMAT_PRIVATE_NAME): Increase
	buffer size.

From-SVN: r244877
2017-01-24 08:49:32 -07:00
Andrew Pinski 5f407e5751 aarch64.c (thunderx2t99_addrcost_table): Improve cost table.
2017-01-23  Andrew Pinski  <apinski@cavium.com>

        * config/aarch64/aarch64.c (thunderx2t99_addrcost_table): Improve
        cost table.

From-SVN: r244851
2017-01-23 18:17:33 -08:00
Kelvin Nilsen 28826a66fb scalar-insert-exp-3.c: New test.
gcc/testsuite/ChangeLog:

2017-01-23  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: New test.
	* gcc.target/powerpc/bfp/scalar-insert-exp-4.c: New test.
	* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: New test.
	* gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Adjust return
	type of test function to reflect change in built-in function's
	return type.
	* gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Adjust return
	type and second argument type to reflect change in built-in
	function's type signature.
	* gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Adjust return
	type of test function to reflect change in built-in function's
	return type.
	* gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise.
	* gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise.
	* gcc.target/powerpc/bfp/vec-insert-exp-4.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-5.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-6.c: New test.
	* gcc.target/powerpc/bfp/vec-insert-exp-7.c: New test.
	* gcc.target/powerpc/bfp/vec-test-data-class-0.c: Adjust return
	type of test function to reflect change in built-in function's
	return type.
	* gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise.
	* gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise.
	* gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise.
	* gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise.
	* gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise.
	* gcc.target/powerpc/bfp/vec-test-data-class-6.c: Adjust types of
	test function's result and second argument to reflect change in
	built-in function's type signature.
	* gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise.

gcc/ChangeLog:

2017-01-23  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/rs6000-builtin.def (VSIEDPF): Add scalar insert
	exponent support with double type for first argument.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Changed
	type returned by __builtin_vec_extract_sig,
	__builtin_vec_extract_sig_sp, and __builtin_vec_extract_sig_dp
	functions from "vector int" to "vector unsigned int" or from
	"vector long long int" to "vector unsigned long long int".
	Changed type returned by __builtin_vec_extract_exp,
	__builtin_vec_extract_exp_sp, and __builtin_vec_extract_exp_dp
	functions from "vector int" to "vector unsigned int" or from
	"vector long long int" to "vector unsigned long long int".
	Changed return type of __builtin_vec_test_data_class,
	__builtin_vec_test_data_class_sp, and
	__builtin_vec_test_data_class_dp from "vector int" to
	"vector bool int" or from "vector long long int" to "vector bool
	long long int" and changed second argument type from "unsigned
	int" to "int".  Added new overloaded function forms "vector float
	__builtin_vec_insert_exp (vector float, vector unsigned int)" and
	"vector float __builtin_vec_insert_exp_sp (vector float, vector
	unsigned int)" and "vector double __builtin_vec_insert_exp (vector
	double, vector unsigned long long int)" and "vector double
	__builtin_vec_insert_exp_dp (vector double, vector unsigned long
	long int)".  Changed return type of
	__builtin_scalar_test_data_class and
	__builtin_scalar_test_data_class_sp and
	__builtin_scalar_test_data_class_dp from "unsigned int" to "bool
	int" and changed second argument from "unsigned int" to "int".
	Changed type returned by __builtin_scalar_test_neg,
	__builtin_scalar_test_neg_sp, and __builtin_scalar_test_neg_dp
	from "int" to "bool int".  Added new overloaded function form
	"double __builtin_scalar_insert_exp (double, unsigned long long int)".
	* config/rs6000/vsx.md (xsiexpdpf): New insn for scalar insert
	exponent double-precision with floating point first argument.
	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Adjust
	documentation of scalar_test_data_class, scalar_test_neg,
	scalar_extract_sig, scalar_extract_exp, scalar_insert_exp,
	vector_extract_exp, vec_extract_sig, vec_insert_exp, and
	vec_test_data_class built-in functions to reflect refinements in
	their type signatures.

From-SVN: r244834
2017-01-23 21:56:58 +00:00
Andreas Tobler 53d190c120 aarch64.c (aarch64_elf_asm_constructor): Increase size of buf.
2017-01-23  Andreas Tobler  <andreast@gcc.gnu.org>

    * config/aarch64/aarch64.c (aarch64_elf_asm_constructor): Increase
    size of buf.
    (aarch64_elf_asm_destructor): Likewise.

From-SVN: r244828
2017-01-23 20:35:50 +01:00
Bernd Schmidt e9c4fbe9c1 re PR rtl-optimization/78634 (30% performance drop after r242832.)
PR rtl-optimization/78634
	* config/i386/i386.c (ix86_max_noce_ifcvt_seq_cost): New function.
	(TARGET_MAX_NOCE_IFCVT_SEQ_COST): Define.
	* ifcvt.c (noce_try_cmove): Add missing cost check.

testsuite/
	PR rtl-optimization/78634
	* gcc.target/i386/funcspec-11.c: Also pass -mtune=i686.

From-SVN: r244816
2017-01-23 16:17:33 +00:00
Andrew Senkevich dea061117a Add AVX512 k-mask intrinsics
gcc/
	* config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics.
	* config/i386/avx512dqintrin.h: Ditto.
	* config/i386/avx512fintrin.h: Ditto.
	* gcc/config/i386/i386.c: Handle new builtins.
	* config/i386/i386-builtin.def: Add new builtins.
	* config/i386/sse.md (ktest<mode>, kortest<mode>): New.
	(UNSPEC_KORTEST, UNSPEC_KTEST): New.

gcc/testsuite/
	* gcc.target/i386/avx512bw-ktestd-1.c: New test.
	* gcc.target/i386/avx512bw-ktestq-1.c: Ditto.
	* gcc.target/i386/avx512dq-ktestb-1.c: Ditto.
	* gcc.target/i386/avx512f-ktestw-1.c: Ditto.
	* gcc.target/i386/avx512bw-kortestd-1.c: Ditto.
	* gcc.target/i386/avx512bw-kortestq-1.c: Ditto.
	* gcc.target/i386/avx512dq-kortestb-1.c: Ditto.
	* gcc.target/i386/avx512f-kortestw-1.c: Ditto.
	* gcc.target/i386/avx512bw-ktestd-2.c: Ditt
	* gcc.target/i386/avx512bw-ktestq-2.c: Ditto.
	* gcc.target/i386/avx512dq-ktestb-2.c: Ditto.
	* gcc.target/i386/avx512f-ktestw-2.c: Ditto.
	* gcc.target/i386/avx512bw-kortestd-2.c: Ditto.
	* gcc.target/i386/avx512bw-kortestq-2.c: Ditto.
	* gcc.target/i386/avx512dq-kortestb-2.c: Ditto.
	* gcc.target/i386/avx512f-kortestw-2.c: Ditto.

From-SVN: r244801
2017-01-23 12:52:39 +00:00
Segher Boessenkool 80b40b8784 rs6000: Small varargs for BE SVR4 (PR61729, PR77850)
The varargs code for SVR4 puts all (integer) arguments in 4-byte slots.
When it then reads an item from there as something not a multiple of 4
bytes, it needs to adjust the address if big endian.  We didn't yet do
that.

This fixes the g++.dg/abi/scoped1.C, gcc.dg/compat/scalar-by-value-4,
and gcc.dg/compat/scalar-return-4 testcases.


	PR target/61729
	PR target/77850
	* config/rs6000/rs6000.c (rs6000_gimplify_va_arg): Adjust address to
	read from, for big endian.

From-SVN: r244740
2017-01-21 04:11:49 +01:00
Jiong Wang a876231c40 [AArch64] Only build & test pauth code for LP64
gcc/
	* config/aarch64/aarch64-builtins.c (aarch64_init_builtins): Register
	register pauth builtins for LP64 only.

libgcc/
	* config/aarch64/aarch64-unwind.h: Empty this file on ILP32.
	* unwind-dw2.c (execute_cfa_program):  Only multiplexing
	DW_CFA_GNU_window_save for AArch64 and LP64.

gcc/testsuite/
	* testsuite/gcc.target/aarch64/return_address_sign_1.c: Enable on LP64
	only.
	* testsuite/gcc.target/aarch64/return_address_sign_2.c: Likewise.
	* testsuite/gcc.target/aarch64/return_address_sign_3.c: Likewise.

From-SVN: r244732
2017-01-20 21:03:41 +00:00
Kyrylo Tkachov 8b0fb476f2 [ARM] PR target/71270 fix neon_valid_immediate for big-endian
PR target/71270
	* config/arm/arm.c (neon_valid_immediate): Reject vector constants
	in big-endian mode when they are not a single duplicated value.

From-SVN: r244716
2017-01-20 14:36:57 +00:00
Graham Markall 7b96920e20 arc/nps: Use arclinux_nps linker emulation for nps
gcc/ChangeLog:

	* config/arc/arc.h (LINK_SPEC): Use arclinux_nps emulation when
	mcpu=nps400.

From-SVN: r244712
2017-01-20 13:37:28 +00:00
Andrew Senkevich d8ea3e7c3c Add AVX512 k-mask intrinsics.
gcc/
	* config/i386/avx512bwintrin.h: Add k-mask registers shift intrinsics.
	* config/i386/avx512dqintrin.h: Ditto.
	* config/i386/avx512fintrin.h: Ditto.
	* config/i386/i386-builtin-types.def: Add new types.
	* gcc/config/i386/i386.c: Handle new types.
	* config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi)
	(__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi)
	(__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi)
	(__builtin_ia32_kshiftrihi, __builtin_ia32_kshiftrisi)
	(__builtin_ia32_kshiftridi): New.
	* config/i386/sse.md (k<code><mode>): Rename *k<code><mode>.

gcc/testsuite/
	* gcc.target/i386/avx512bw-kshiftld-1.c: New test.
	* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
	* gcc.target/i386/avx512dq-kshiftlb-1.c: Ditto.
	* gcc.target/i386/avx512f-kshiftlw-1.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftrd-1.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
	* gcc.target/i386/avx512dq-kshiftrb-1.c: Ditto.
	* gcc.target/i386/avx512f-kshiftrw-1.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftld-2.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftlq-2.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftrd-2.c: Ditto.
	* gcc.target/i386/avx512bw-kshiftrq-2.c: Ditto.
	* gcc.target/i386/avx512dq-kshiftlb-2.c: Ditto.
	* gcc.target/i386/avx512dq-kshiftrb-2.c: Ditto.
	* gcc.target/i386/avx512f-kshiftlw-2.c: Ditto.
	* gcc.target/i386/avx512f-kshiftrw-2.c: Ditto.
	* gcc.target/i386/avx-1.c: Test new intrinsics.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.

From-SVN: r244685
2017-01-20 08:37:13 +00:00
Segher Boessenkool 01334be4a0 rs6000: Fix the new SSP guard configuration code (PR79140)
I foolishly tested this with r241087 reverted.  After that revision
default_stack_protect_guard is no longer called if the compiler defaults
to using the TLS guard, which of course is the wrong thing to do if
there is some other way to enable the global guard.

This fixes it.


	PR target/78875
	PR target/79140
	* config/rs6000/rs6000.c (TARGET_STACK_PROTECT_GUARD): Unconditionally
	define to rs6000_init_stack_protect_guard.
	(rs6000_init_stack_protect_guard): New function.

From-SVN: r244677
2017-01-20 02:22:27 +01:00
Matthew Fortune d821744c63 config.gcc (supported_defaults): Add madd4.
gcc/
2017-01-19  Matthew Fortune  <matthew.fortune@imgtec.com>
	    Yunqiang Su  <yunqiang.su@imgtec.com>

	* config.gcc (supported_defaults): Add madd4.
	(with_madd4): Add validation.
	(all_defaults): Add madd4.
	* config/mips/mips.opt (mmadd4): New option.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	mmadd4.
	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
	__mips_no_madd4.
	(ISA_HAS_UNFUSED_MADD4): Gate with mips_madd4.
	(ISA_HAS_FUSED_MADD4): Likewise.
	* gcc/doc/invoke.texi (-mmadd4): Document the new option.
	* gcc/doc/install.texi (--with-madd4): Document the new option.

gcc/testsuite/
2017-01-19  Matthew Fortune  <matthew.fortune@imgtec.com>

	* gcc.target/mips/madd4-1.c: New file.
	* gcc.target/mips/madd4-2.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
	HAS_MADD4.
	(mips_option_groups): Add -m[no-]madd4.
	(mips-dg-init): Detect default -mno-madd4.
	(mips-dg-options): Handle HAS_MADD4 arch upgrade/downgrade.
	* gcc.target/mips/mips-ps-type.c: Add -mmadd4 test option.
	* gcc.target/mips/mips-ps-type-2.c: Likewise.
	* gcc.target/mips/nmadd-1.c: Likewise.
	* gcc.target/mips/nmadd-2.c: Likewise.
	* gcc.target/mips/nmadd-3.c: Likewise.

Co-Authored-By: Yunqiang Su <yunqiang.su@imgtec.com>

From-SVN: r244676
2017-01-19 20:05:25 -05:00
Jiong Wang 312492bd5e [AArch64][3/4] New PAUTH builtins required by libgcc unwinder
gcc/
	* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): New
	entries for AARCH64_PAUTH_BUILTIN_XPACLRI,
	AARCH64_PAUTH_BUILTIN_PACIA1716, AARCH64_PAUTH_BUILTIN_AUTIA1716.
	(aarch64_init_pauth_hint_builtins): New.
	(aarch64_init_builtins): Call aarch64_init_pauth_hint_builtins.
	(aarch64_expand_builtin): Expand new builtins.

From-SVN: r244669
2017-01-20 00:10:11 +00:00
Jiong Wang 27169e45d4 [AArch64][2/4] Generate dwarf information for -msign-return-address
gcc/
	* reg-notes.def (CFA_TOGGLE_RA_MANGLE): New reg-note.
	* combine-stack-adj.c (no_unhandled_cfa): Handle
	REG_CFA_TOGGLE_RA_MANGLE.
	* dwarf2cfi.c (dwarf2out_frame_debug): Handle REG_CFA_TOGGLE_RA_MANGLE.
	* config/aarch64/aarch64.c (aarch64_expand_prologue): Generates DWARF
	info for return address signing.
	(aarch64_expand_epilogue): Likewise.

From-SVN: r244667
2017-01-20 00:05:30 +00:00
Jiong Wang db58fd8954 [AArch64][1/4] Support Return address protection on AArch64
gcc/
	* config/aarch64/aarch64-opts.h (aarch64_function_type): New enum.
	* config/aarch64/aarch64-protos.h
	(aarch64_return_address_signing_enabled): New declaration.
	* config/aarch64/aarch64.c (aarch64_return_address_signing_enabled):
	New function.
	(aarch64_expand_prologue): Sign return address before it's pushed onto
	stack.
	(aarch64_expand_epilogue): Authenticate return address fetched from
	stack.
	(aarch64_override_options): Sanity check for ILP32 and ISA level.
	(aarch64_attributes): New function attributes for "sign-return-address".
	* config/aarch64/aarch64.md (UNSPEC_AUTI1716, UNSPEC_AUTISP,
	UNSPEC_PACI1716, UNSPEC_PACISP, UNSPEC_XPACLRI): New unspecs.
	("*do_return"): Generate combined instructions according to key index.
	("<pauth_mnem_prefix>sp", "<pauth_mnem_prefix1716", "xpaclri"): New.
	* config/aarch64/iterators.md (PAUTH_LR_SP, PAUTH_17_16): New integer
	iterators.
	(pauth_mnem_prefix, pauth_hint_num_a): New integer attributes.
	* config/aarch64/aarch64.opt (msign-return-address=): New.
	* doc/extend.texi (AArch64 Function Attributes): Documents
	"sign-return-address=".
	* doc/invoke.texi (AArch64 Options): Documents "-msign-return-address=".

gcc/testsuite/
	* gcc.target/aarch64/return_address_sign_1.c: New testcase for no
	combined instructions.
	* gcc.target/aarch64/return_address_sign_2.c: New testcase for combined
	instructions.
	* gcc.target/aarch64/return_address_sign_3.c: New testcase for disable
	of pointer authentication.

From-SVN: r244666
2017-01-20 00:03:20 +00:00
Jiong Wang d766c52b7b [AArch64] Add commandline support for -march=armv8.3-a
gcc/
	* config/aarch64/aarch64-arches.def: New entry for "armv8.3-a".
	* config/aarch64/aarch64.h (AARCH64_FL_V8_3, AARCH64_FL_FOR_ARCH8_3,
	AARCH64_ISA_V8_3, TARGET_ARMV8_3): New.
	* doc/invoke.texi (AArch64 Options): Document "armv8.3-a".

From-SVN: r244663
2017-01-19 23:51:49 +00:00
Michael Meissner bd9cf60b31 rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Enable -mpower9-minmax by default for -mcpu=power9.
[gcc]
2017-01-19  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Enable
	-mpower9-minmax by default for -mcpu=power9.
	(ISA_3_MASKS_IEEE): Require -mvsx-small-integer to enable IEEE
	128-bit floating point.

[gcc/testsuite]
2017-01-19  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/float128-hw.c: Do not require IEEE 128-bit
	floating point hardware to run test.

From-SVN: r244662
2017-01-19 23:31:20 +00:00
Alan Modra 945a01f921 [RS6000] Don't expand strcmp and strncmp inline when -Os
* config/rs6000/rs6000.md (cmpstrnsi, cmpstrsi): Fail if
	optimizing for size.

From-SVN: r244660
2017-01-20 09:51:53 +10:30
Alan Modra 5699b9d115 [RS6000] PR79144, cmpstrnsi optimization breaks glibc
glibc compiled with current gcc-7 fails one test due to strcmp and
strncmp appearing in the PLT.  This is because the inline expansion of
those functions falls back to a function call, but doesn't use the asm
name for the call.

	PR target/79144
	* config/rs6000/rs6000.c (expand_strn_compare): Get the asm name
	for strcmp and strncmp from corresponding builtin decl.

From-SVN: r244659
2017-01-20 09:49:19 +10:30
Uros Bizjak d445d739b9 config.gcc (x86_64-*-rtems*): Use i386/rtemself.h instead of i386/rtems-64.h.
* config.gcc (x86_64-*-rtems*): Use i386/rtemself.h
	instead of i386/rtems-64.h.
	* config/i386/rtems-64.h: Remove.

From-SVN: r244655
2017-01-19 23:00:17 +01:00
Uros Bizjak fa9205536c re PR target/78478 (Compile Error for i386-rtems)
PR target/78478
	Revert:
	2013-11-05  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/rtemself.h (LONG_DOUBLE_TYPE_SIZE): New define.

From-SVN: r244653
2017-01-19 22:38:44 +01:00
Tamar Christina ab014eb3ae aarch64.c (aarch64_simd_gen_const_vector_dup): Change int to HOST_WIDE_INT.
gcc/
2017-01-19  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64.c (aarch64_simd_gen_const_vector_dup):
	Change int to HOST_WIDE_INT.
	* config/aarch64/aarch64-protos.h
	(aarch64_simd_gen_const_vector_dup): Likewise.
	* config/aarch64/aarch64-simd.md: Add copysign<mode>3.

gcc/testsuite/
2017-01-19  Tamar Christina  <tamar.christina@arm.com>

	* gcc/testsuite/lib/target-supports.exp
	(check_effective_target_vect_call_copysignf): Enable for AArch64.

From-SVN: r244649
2017-01-19 18:30:44 +00:00
Pat Haugen 86eb502b93 power9.md (power9-alu): Remove 'cmp' type and add define_bypass for CR latency.
* config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add
	define_bypass for CR latency.
	(power9-cracked-alu): Update bypass latency and remove power9-branch.
	(power9-alu2): Add define_bypass for CR latency.
	(power9-cmp): New.
	(power9-mul): Update insn latency.
	(power9-mul-compare): Update insn latency, bypass latency and remove
	power9-branch.

From-SVN: r244645
2017-01-19 17:11:34 +00:00
Kyrylo Tkachov 197d1c095d [AArch64] Purge leftover occurrences of aarch64_nopcrelative_literal_loads
* config/aarch64/aarch64-protos.h (aarch64_nopcrelative_literal_loads):
	Delete.
	* config/aarch64/aarch64.md
	(aarch64_reload_movcp<GPF_TF:mode><P:mode>): Delete reference to
	aarch64_nopcrelative_literal_loads.
	(aarch64_reload_movcp<VALL:mode><P:mode>): Likewise.

From-SVN: r244643
2017-01-19 16:59:43 +00:00
Chenghua Xu cedb7e2c85 MIPS: Make loongson3a use fused madd.d
gcc/
	* config/mips/mips.h (ISA_HAS_FUSED_MADD4): Enable for
	TARGET_LOONGSON_3A.
	(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_LOONGSON_3A.

From-SVN: r244641
2017-01-19 16:26:32 +00:00
Matthew Fortune ab6b44cb22 MIPS: PR target/78176 add -mlxc1-sxc1.
gcc/

	PR target/78176
	* config.gcc (supported_defaults): Add lxc1-sxc1.
	(with_lxc1_sxc1): Add validation.
	(all_defaults): Add lxc1-sxc1.
	* config/mips/mips.opt (mlxc1-sxc1): New option.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	mlxc1-sxc1.
	(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
	__mips_no_lxc1_sxc1.
	(ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1.
	* gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option.
	* doc/install.texi (--with-lxc1-sxc1): Document the new option.

gcc/testsuite/

	* gcc.target/mips/lxc1-sxc1-1.c: New file.
	* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
	* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
	HAS_LXC1.
	(mips_option_groups): Add -m[no-]lxc1-sxc1.
	(mips-dg-init): Detect default -mno-lxc1-sxc1.
	(mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade.

From-SVN: r244640
2017-01-19 16:05:59 +00:00
Peter Bergner f457ef94da re PR target/78516 (ICE in lra_assign for e500v2)
PR target/78516
	* config/rs6000/spe.md (mov_si<mode>_e500_subreg0): Fix constraints.
	Use the evmergelohi instruction.
	(mov_si<mode>_e500_subreg4_2_le): Likewise.
	(mov_sitf_e500_subreg8_2_be): Likewise.
	(mov_sitf_e500_subreg12_2_le): Likewise.
	(mov_si<mode>_e500_subreg0_2_le): Fix constraints.
	(mov_si<mode>_e500_subreg4_2_be): Likewise.
	(mov_sitf_e500_subreg8_2_le): Likewise.
	(mov_sitf_e500_subreg12_2_be): Likewise.

From-SVN: r244609
2017-01-18 20:23:35 -06:00
Bill Schmidt 20ca9ae25f altivec.md (altivec_vbpermq): Change "type" attribute from vecsimple to vecperm.
2017-01-18  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.md (altivec_vbpermq): Change "type"
	attribute from vecsimple to vecperm.
	(altivec_vbpermq2): Likewise.

From-SVN: r244603
2017-01-18 22:36:39 +00:00
Bill Schmidt 1c8bf56078 re PR target/79040 (vec_cntlz redefined)
2017-01-18  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/79040
	* config/rs6000/altivec.h: Fix typo of vec_cntlz to vec_cnttz.

From-SVN: r244602
2017-01-18 22:29:22 +00:00
Aaron Sawdey 0edd264dfc rs6000-protos.h (expand_strn_compare): Add arg.
2017-01-18  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
	* config/rs6000/rs6000-protos.h (expand_strn_compare): Add arg.
	* config/rs6000/rs6000.c (expand_strn_compare): Add ability to expand
	strcmp. Fix bug where comparison didn't stop with zero byte. Fix
	case where N arg is SIZE_MAX.
	* config/rs6000/rs6000.md (cmpstrnsi): Args to expand_strn_compare.
	(cmpstrsi): Add pattern.
2017-01-18  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>
	* gcc.dg/strcmp-1.c: New test.
	* gcc.dg/strncmp-1.c: Add test for a bug that escaped.

From-SVN: r244598
2017-01-18 14:56:16 -06:00
Michael Meissner b7d3a6a6b2 rs6000-c.c (altivec_overloaded_builtins): Add __builtin_vec_revb builtins.
[gcc]
2017-01-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	__builtin_vec_revb builtins.
	* config/rs6000/rs6000-builtins.def (P9V_BUILTIN_XXBRQ_V16QI): Add
	built-in functions to support generation of the ISA 3.0 XXBR<x>
	vector byte reverse instructions.
	(P9V_BUILTIN_XXBRQ_V1TI): Likewise.
	(P9V_BUILTIN_XXBRD_V2DI): Likewise.
	(P9V_BUILTIN_XXBRD_V2DF): Likewise.
	(P9V_BUILTIN_XXBGW_V4SI): Likewise.
	(P9V_BUILTIN_XXBGW_V4SF): Likewise.
	(P9V_BUILTIN_XXBGH_V8HI): Likewise.
	(P9V_BUILTIN_VEC_REVB): Likewise.
	* config/rs6000/vsx.md (p9_xxbrq_v1ti): New insns/expanders to
	generate the ISA 3.0 XXBR<x> vector byte reverse instructions.
	(p9_xxbrq_v16qi): Likewise.
	(p9_xxbrd_<mode>, VSX_D iterator): Likewise.
	(p9_xxbrw_<mode>, VSX_W iterator): Likewise.
	(p9_xxbrh_v8hi): Likewise.
	* config/rs6000/altivec.h (vec_revb): Define if ISA 3.0.
	* doc/extend.texi (RS/6000 Altivec Built-ins): Document the
	vec_revb built-in functions.

[gcc/testsuite]
2017-01-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-xxbr-1.c: New test.
	* gcc.target/powerpc/p9-xxbr-2.c: Likewise.

From-SVN: r244593
2017-01-18 19:30:38 +00:00
Uros Bizjak a711887ed9 re PR rtl-optimization/78952 (Combine does not convert 8-bit sign-extract to a zero-extract for QImode operations)
PR rtl-optimization/78952
	* config/i386/i386.md (any_extract): New code iterator.
	(*insvqi_2): Use any_extract for source operand.
	(*insvqi_3): Use any_shiftrt for source operand.

testsuite/ChangeLog:

	PR rtl-optimization/78952
	* gcc.target/i386/pr78952-1.c: New test.
	* gcc.target/i386/pr78952-2.c: Ditto.

From-SVN: r244591
2017-01-18 20:24:30 +01:00
Wilco Dijkstra 9bca63d44b SHA1H instructions may be scheduled after a SHA1C instruction that uses the same input register.
SHA1H instructions may be scheduled after a SHA1C instruction
that uses the same input register.  However SHA1C updates its input,
so if SHA1H is scheduled after it, it requires an extra move.
Increase the priority of SHA1H to ensure it gets scheduled
earlier, avoiding the move.

    gcc/
	* config/aarch64/aarch64.c (aarch64_sched_adjust_priority)
	New function.
	(TARGET_SCHED_ADJUST_PRIORITY): Define target hook.

From-SVN: r244586
2017-01-18 18:23:34 +00:00
Bill Schmidt dfc42f08ce altivec.h (vec_bperm): Change #define.
[gcc]

2016-01-18  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.h (vec_bperm): Change #define.
	* config/rs6000/altivec.md (UNSPEC_VBPERMD): New enum constant.
	(altivec_vbpermq2): New define_insn.
	(altivec_vbpermd): Likewise.
	* config/rs6000/rs6000-builtin.def (VBPERMQ2): New monomorphic
	function interface.
	(VBPERMD): Likewise.
	(VBPERM): New polymorphic function interface.
	* config/rs6000/r6000-c.c (altivec_overloaded_builtins_table):
	Add entries for P9V_BUILTIN_VEC_VBPERM.
	* doc/extend.texi: Add interfaces for vec_bperm.

[gcc/testsuite]

2016-01-18  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/p8vector-builtin-8.c: Add new form for
	vec_bperm.
	* gcc.target/powerpc/p9-vbpermd.c: New file.

From-SVN: r244578
2017-01-18 15:04:50 +00:00