PR rtl-optimization/83565
* rtlanal.c (nonzero_bits1): On WORD_REGISTER_OPERATIONS machines, do
not extend the result to a larger mode for rotate operations.
(num_sign_bit_copies1): Likewise.
From-SVN: r256572
gcc/testsuite:
PR libfortran/67412
* gfortran.dg/execute_command_line_2.f90: Remove dg-xfail-run-if
on *-*-solaris2.10.
libstdc++-v3:
PR libstdc++/64054
* testsuite/27_io/basic_ostream/inserters_arithmetic/char/hexfloat.cc:
Remove dg-xfail-run-if.
gcc:
PR target/40411
* config/sol2.h (STARTFILE_ARCH_SPEC): Don't use with -shared or
-symbolic.
Use values-Xc.o for -pedantic.
Link with values-xpg4.o for C90, values-xpg6.o otherwise.
From-SVN: r256568
2018-01-12 Martin Liska <mliska@suse.cz>
PR ipa/83054
* ipa-devirt.c (final_warning_record::grow_type_warnings):
New function.
(possible_polymorphic_call_targets): Use it.
(ipa_devirt): Likewise.
2018-01-12 Martin Liska <mliska@suse.cz>
PR ipa/83054
* g++.dg/warn/pr83054.C: New test.
From-SVN: r256566
2018-01-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* configure.ac (--with-long-double-format): Add support for the
configuration option to change the default long double format on
PowerPC systems.
* config.gcc (powerpc*-linux*-*): Likewise.
* configure: Regenerate.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If long
double is IEEE, define __KC__ and __KF__ to allow floatn.h to be
used without modification.
From-SVN: r256558
PR target/83203
* config/i386/i386.c (ix86_expand_vector_init_one_nonzero): If one_var
is 0, for V{8,16}S[IF] and V[48]D[IF]mode use gen_vec_set<mode>_0.
* config/i386/sse.md (VI8_AVX_AVX512F, VI4F_256_512): New mode
iterators.
(ssescalarmodesuffix): Add 512-bit vectors. Use "d" or "q" for
integral modes instead of "ss" and "sd".
(vec_set<mode>_0): New define_insns for 256-bit and 512-bit
vectors with 32-bit and 64-bit elements.
(vecdupssescalarmodesuffix): New mode attribute.
(vec_dup<mode>): Use it.
From-SVN: r256556
When a function call is removed, it may become a leaf function. But if
argument may be passed on stack, we need to align the stack frame when
there is no tail call.
Tested on Linux/i686 and Linux/x86-64.
gcc/
PR target/83330
* config/i386/i386.c (ix86_compute_frame_layout): Align stack
frame if argument is passed on stack.
gcc/testsuite/
PR target/83330
* gcc.target/i386/pr83330.c: New test.
From-SVN: r256555
2018-01-11 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/79383
* gfortran.dg/dtio_31.f03: New test.
* gfortran.dg/dtio_32.f03: New test.
From-SVN: r256554
gcc/testsuite/ChangeLog:
PR c++/43486
* g++.dg/wrappers: New subdirectory.
* g++.dg/wrappers/README: New file.
* g++.dg/wrappers/alloc.C: New test case.
* g++.dg/wrappers/cow-istream-string.C: New test case.
* g++.dg/wrappers/cp-stdlib.C: New test case.
* g++.dg/wrappers/sanitizer_coverage_libcdep_new.C: New test case.
* g++.dg/wrappers/wrapper-around-type-pack-expansion.C: New test
case.
From-SVN: r256552
PR middle-end/83718
* tree-inline.c (copy_cfg_body): Adjust num&den for scaling
after they are computed.
* g++.dg/torture/pr83718.C: New testcase.
From-SVN: r256544
This patch implements the lane-wise fp16fml intrinsics.
There's quite a few of them so I've split them up from
the other simpler fp16fml intrinsics.
These ones expose instructions such as
vfmal.f16 Dd, Sn, Sm[<index>] 0 <= index <= 1
vfmal.f16 Qd, Dn, Dm[<index>] 0 <= index <= 3
vfmsl.f16 Dd, Sn, Sm[<index>] 0 <= index <= 1
vfmsl.f16 Qd, Dn, Dm[<index>] 0 <= index <= 3
These instructions extract a single half-precision
floating-point value from one of the source regs
and perform a vfmal/vfmsl operation as per the
normal variant with that value.
The nuance here is that some of the intrinsics want
to do things like:
float32x2_t vfmlal_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b, const int __index)
where the float16x8_t value of '__b' is held in a Q
register, so we need to be a bit smart about finding
the right D or S sub-register and translating the
lane number to a lane in that sub-register, instead
of just passing the language-level const-int down to
the assembly instruction.
That's where most of the complexity of this patch comes from
but hopefully it's orthogonal enough to make sense.
Bootstrapped and tested on arm-none-linux-gnueabihf as well as
armeb-none-eabi.
* config/arm/arm_neon.h (vfmlal_lane_low_u32, vfmlal_lane_high_u32,
vfmlalq_laneq_low_u32, vfmlalq_lane_low_u32, vfmlal_laneq_low_u32,
vfmlalq_laneq_high_u32, vfmlalq_lane_high_u32, vfmlal_laneq_high_u32,
vfmlsl_lane_low_u32, vfmlsl_lane_high_u32, vfmlslq_laneq_low_u32,
vfmlslq_lane_low_u32, vfmlsl_laneq_low_u32, vfmlslq_laneq_high_u32,
vfmlslq_lane_high_u32, vfmlsl_laneq_high_u32): Define.
* config/arm/arm_neon_builtins.def (vfmal_lane_low,
vfmal_lane_lowv4hf, vfmal_lane_lowv8hf, vfmal_lane_high,
vfmal_lane_highv4hf, vfmal_lane_highv8hf, vfmsl_lane_low,
vfmsl_lane_lowv4hf, vfmsl_lane_lowv8hf, vfmsl_lane_high,
vfmsl_lane_highv4hf, vfmsl_lane_highv8hf): New sets of builtins.
* config/arm/iterators.md (VFMLSEL2, vfmlsel2): New mode attributes.
(V_lane_reg): Likewise.
* config/arm/neon.md (neon_vfm<vfml_op>l_lane_<vfml_half><VCVTF:mode>):
New define_expand.
(neon_vfm<vfml_op>l_lane_<vfml_half><vfmlsel2><mode>): Likewise.
(vfmal_lane_low<mode>_intrinsic,
vfmal_lane_low<vfmlsel2><mode>_intrinsic,
vfmal_lane_high<vfmlsel2><mode>_intrinsic,
vfmal_lane_high<mode>_intrinsic, vfmsl_lane_low<mode>_intrinsic,
vfmsl_lane_low<vfmlsel2><mode>_intrinsic,
vfmsl_lane_high<vfmlsel2><mode>_intrinsic,
vfmsl_lane_high<mode>_intrinsic): New define_insns.
* gcc.target/arm/simd/fp16fml_lane_high.c: New test.
* gcc.target/arm/simd/fp16fml_lane_low.c: New test.
From-SVN: r256540
This patch adds the +fp16fml extension that enables some
half-precision floating-point Advanced SIMD instructions,
available through arm_neon.h intrinsics.
This extension is on by default for armv8.4-a
if fp16 is available, so it can be enabled by -march=armv8.4-a+fp16.
fp16fml is also available for armv8.2-a and armv8.3-a through the
+fp16fml option that is added for these architectures.
The new instructions that this patch adds support for are:
vfmal.f16 Dr, Sm, Sn
vfmal.f16 Qr, Dm, Dn
vfmsl.f16 Dr, Sm, Sn
vfmsl.f16 Qr, Dm, Dn
They interpret their input registers as a vector of half-precision
floating-point values, extend them to single-precision vectors
and perform a fused multiply-add or subtract of them with the
destination vector.
This patch exposes these instructions through arm_neon.h intrinsics.
The set of intrinsics allows us to do stuff such as perform
the multiply-add/subtract operation on the low or top half of
float16x4_t and float16x8_t values. This maps naturally in aarch64
to the FMLAL and FMLAL2 instructions but on arm we have to use the
fact that consecutive NEON registers overlap the wider register
(i.e. d0 is s0 plus s1, q0 is d0 plus d1 etc). This just means
we have to be careful to use the right subreg operand print code.
New arm-specific builtins are defined to expand to the new patterns.
I've managed to compress the define_expands using code, mode and int
iterators but the define_insns don't compress very well without two-tiered
iterators (iterator attributes expanding to iterators) which we
don't support.
Bootstrapped and tested on arm-none-linux-gnueabihf and also on
armeb-none-eabi.
* config/arm/arm-cpus.in (fp16fml): New feature.
(ALL_SIMD): Add fp16fml.
(armv8.2-a): Add fp16fml as an option.
(armv8.3-a): Likewise.
(armv8.4-a): Add fp16fml as part of fp16.
* config/arm/arm.h (TARGET_FP16FML): Define.
* config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_FP16_FML
when appropriate.
* config/arm/arm-modes.def (V2HF): Define.
* config/arm/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_low_u32,
vfmlslq_low_u32, vfmlalq_high_u32, vfmlslq_high_u32): Define.
* config/arm/arm_neon_builtins.def (vfmal_low, vfmal_high,
vfmsl_low, vfmsl_high): New set of builtins.
* config/arm/iterators.md (PLUSMINUS): New code iterator.
(vfml_op): New code attribute.
(VFMLHALVES): New int iterator.
(VFML, VFMLSEL): New mode attributes.
(V_reg): Define mapping for V2HF.
(V_hi, V_lo): New mode attributes.
(VF_constraint): Likewise.
(vfml_half, vfml_half_selector): New int attributes.
* config/arm/neon.md (neon_vfm<vfml_op>l_<vfml_half><mode>): New
define_expand.
(vfmal_low<mode>_intrinsic, vfmsl_high<mode>_intrinsic,
vfmal_high<mode>_intrinsic, vfmsl_low<mode>_intrinsic):
New define_insn.
* config/arm/t-arm-elf (v8_fps): Add fp16fml.
* config/arm/t-multilib (v8_2_a_simd_variants): Add fp16fml.
* config/arm/unspecs.md (UNSPEC_VFML_LO, UNSPEC_VFML_HI): New unspecs.
* doc/invoke.texi (ARM Options): Document fp16fml. Update armv8.4-a
documentation.
* doc/sourcebuild.texi (arm_fp16fml_neon_ok, arm_fp16fml_neon):
Document new effective target and option set.
* gcc.target/arm/multilib.exp: Add combination tests for fp16fml.
* gcc.target/arm/simd/fp16fml_high.c: New test.
* gcc.target/arm/simd/fp16fml_low.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_fp16fml_neon_ok_nocache,
check_effective_target_arm_fp16fml_neon_ok,
add_options_for_arm_fp16fml_neon): New procedures.
From-SVN: r256539
This patch adds support for the Armv8.4-A architecture [1]
in the arm backend. This is done through the new
-march=armv8.4-a option.
With this patch armv8.4-a is recognised as an argument
and supports the extensions: simd, fp16, crypto, nocrypto,
nofp with the familiar meaning of these options.
Worth noting that there is no dotprod option like in
armv8.2-a and armv8.3-a because Dot Product support is
mandatory in Armv8.4-A when simd is available, so when using
+simd (of fp16 which enables +simd), the +dotprod is implied.
The various multilib selection makefile fragments are updated
too and the mutlilib.exp test gets a few armv8.4-a combination
tests.
Bootstrapped and tested on arm-none-linux-gnueabihf.
From-SVN: r256537
This patch records the integer value of the address offset in
aarch64_address_info, so that it doesn't need to be re-extracted
from the rtx. The SVE port will make more use of this. The patch
also uses poly_int64 routines to manipulate the offset, rather than
just handling CONST_INTs.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset
field.
(aarch64_classify_address): Initialize it. Track polynomial offsets.
(aarch64_print_address_internal): Use it to check for a zero offset.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256534
This patch switches the AArch64 port to use 2 poly_int coefficients
and updates code as necessary to keep it compiling.
One potentially-significant change is to
aarch64_hard_regno_caller_save_mode. The old implementation
was written in a pretty conservative way: it changed the default
behaviour for single-register values, but used the default handling
for multi-register values.
I don't think that's necessary, since the interesting cases for this
macro are usually the single-register ones. Multi-register modes take
up the whole of the constituent registers and the move patterns for all
multi-register modes should be equally good.
Using the original mode for multi-register cases stops us from using
SVE modes to spill multi-register NEON values. This was caught by
gcc.c-torture/execute/pr47538.c.
Also, aarch64_shift_truncation_mask used GET_MODE_BITSIZE - 1.
GET_MODE_UNIT_BITSIZE - 1 is equivalent for the cases that it handles
(which are all scalars), and I think it's more obvious, since if we ever
do use this for elementwise shifts of vector modes, the mask will depend
on the number of bits in each element rather than the number of bits in
the whole vector.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def (NUM_POLY_INT_COEFFS): Set to 2.
* config/aarch64/aarch64-protos.h (aarch64_initial_elimination_offset):
Return a poly_int64 rather than a HOST_WIDE_INT.
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* config/aarch64/aarch64.h (aarch64_frame): Protect with
HAVE_POLY_INT_H rather than HOST_WIDE_INT. Change locals_offset,
hard_fp_offset, frame_size, initial_adjust, callee_offset and
final_offset from HOST_WIDE_INT to poly_int64.
* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
to_constant when getting the number of units in an Advanced SIMD
mode.
(aarch64_builtin_vectorized_function): Check for a constant number
of units.
* config/aarch64/aarch64-simd.md (mov<mode>): Handle polynomial
GET_MODE_SIZE.
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use the nunits
attribute instead of GET_MODE_NUNITS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_class_max_nregs): Use the constant_lowest_bound of the
GET_MODE_SIZE for fixed-size registers.
(aarch64_const_vec_all_same_in_range_p): Use const_vec_duplicate_p.
(aarch64_hard_regno_call_part_clobbered, aarch64_classify_index)
(aarch64_mode_valid_for_sched_fusion_p, aarch64_classify_address)
(aarch64_legitimize_address_displacement, aarch64_secondary_reload)
(aarch64_print_operand, aarch64_print_address_internal)
(aarch64_address_cost, aarch64_rtx_costs, aarch64_register_move_cost)
(aarch64_short_vector_p, aapcs_vfp_sub_candidate)
(aarch64_simd_attr_length_rglist, aarch64_operands_ok_for_ldpstp):
Handle polynomial GET_MODE_SIZE.
(aarch64_hard_regno_caller_save_mode): Likewise. Return modes
wider than SImode without modification.
(tls_symbolic_operand_type): Use strip_offset instead of split_const.
(aarch64_pass_by_reference, aarch64_layout_arg, aarch64_pad_reg_upward)
(aarch64_gimplify_va_arg_expr): Assert that we don't yet handle
passing and returning SVE modes.
(aarch64_function_value, aarch64_layout_arg): Use gen_int_mode
rather than GEN_INT.
(aarch64_emit_probe_stack_range): Take the size as a poly_int64
rather than a HOST_WIDE_INT, but call sorry if it isn't constant.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_layout_frame): Cope with polynomial offsets.
(aarch64_save_callee_saves, aarch64_restore_callee_saves): Take the
start_offset as a poly_int64 rather than a HOST_WIDE_INT. Track
polynomial offsets.
(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p)
(aarch64_offset_7bit_signed_scaled_p): Take the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(aarch64_get_separate_components, aarch64_process_components)
(aarch64_expand_prologue, aarch64_expand_epilogue)
(aarch64_use_return_insn_p): Handle polynomial frame offsets.
(aarch64_anchor_offset): New function, split out from...
(aarch64_legitimize_address): ...here.
(aarch64_builtin_vectorization_cost): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(aarch64_simd_check_vect_par_cnst_half): Handle polynomial
GET_MODE_NUNITS.
(aarch64_simd_make_constant, aarch64_expand_vector_init): Get the
number of elements from the PARALLEL rather than the mode.
(aarch64_shift_truncation_mask): Use GET_MODE_UNIT_BITSIZE
rather than GET_MODE_BITSIZE.
(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_ext)
(aarch64_evpc_rev, aarch64_evpc_dup, aarch64_evpc_zip)
(aarch64_expand_vec_perm_const_1): Handle polynomial
d->perm.length () and d->perm elements.
(aarch64_evpc_tbl): Likewise. Use nelt rather than GET_MODE_NUNITS.
Apply to_constant to d->perm elements.
(aarch64_simd_valid_immediate, aarch64_vec_fpconst_pow_of_2): Handle
polynomial CONST_VECTOR_NUNITS.
(aarch64_move_pointer): Take amount as a poly_int64 rather
than an int.
(aarch64_progress_pointer): Avoid temporary variable.
* config/aarch64/aarch64.md (aarch64_<crc_variant>): Use
the mode attribute instead of GET_MODE.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256533
The port had aarch64_add_offset and aarch64_add_constant routines
that did similar things. This patch replaces them with an expanded
version of aarch64_add_offset that takes separate source and
destination registers. The new routine also takes a poly_int64 offset
instead of a HOST_WIDE_INT offset, but it leaves the HOST_WIDE_INT
case to aarch64_add_offset_1, which is basically a repurposed
aarch64_add_constant_internal. The SVE patch will put the handling
of VL-based constants in aarch64_add_offset, while still using
aarch64_add_offset_1 for the constant part.
The vcall_offset == 0 path in aarch64_output_mi_thunk will use temp0
as well as temp1 once SVE is added.
A side-effect of the patch is that we now generate:
mov x29, sp
instead of:
add x29, sp, 0
in the pr70044.c test.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_force_temporary): Assert that
x exists before using it.
(aarch64_add_constant_internal): Rename to...
(aarch64_add_offset_1): ...this. Replace regnum with separate
src and dest rtxes. Handle the case in which they're different,
including when the offset is zero. Replace scratchreg with an rtx.
Use 2 additions if there is no spare register into which we can
move a 16-bit constant.
(aarch64_add_constant): Delete.
(aarch64_add_offset): Replace reg with separate src and dest
rtxes. Take a poly_int64 offset instead of a HOST_WIDE_INT.
Use aarch64_add_offset_1.
(aarch64_add_sp, aarch64_sub_sp): Take the scratch register as
an rtx rather than an int. Take the delta as a poly_int64
rather than a HOST_WIDE_INT. Use aarch64_add_offset.
(aarch64_expand_mov_immediate): Update uses of aarch64_add_offset.
(aarch64_expand_prologue): Update calls to aarch64_sub_sp,
aarch64_allocate_and_probe_stack_space and aarch64_add_offset.
(aarch64_expand_epilogue): Update calls to aarch64_add_offset
and aarch64_add_sp.
(aarch64_output_mi_thunk): Use aarch64_add_offset rather than
aarch64_add_constant.
gcc/testsuite/
* gcc.target/aarch64/pr70044.c: Allow "mov x29, sp" too.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256532
In preparation for the switch to NUM_POLY_INT_COEFFS==2.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64.c (aarch64_reinterpret_float_as_int):
Use scalar_float_mode.
From-SVN: r256531
This patch replaces GET_MODE_NUNITS in some of the v8.4 support
with equivalent values, in preparation for the switch to
NUM_POLY_INT_COEFFS==2.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_fml<f16mac1>l<f16quad>_low<mode>): Avoid GET_MODE_NUNITS.
(aarch64_fml<f16mac1>l<f16quad>_high<mode>): Likewise.
(aarch64_fml<f16mac1>l_lane_lowv2sf): Likewise.
(aarch64_fml<f16mac1>l_lane_highv2sf): Likewise.
(aarch64_fml<f16mac1>lq_laneq_lowv4sf): Likewise.
(aarch64_fml<f16mac1>lq_laneq_highv4sf): Likewise.
(aarch64_fml<f16mac1>l_laneq_lowv2sf): Likewise.
(aarch64_fml<f16mac1>l_laneq_highv2sf): Likewise.
(aarch64_fml<f16mac1>lq_lane_lowv4sf): Likewise.
(aarch64_fml<f16mac1>lq_lane_highv4sf): Likewise.
From-SVN: r256530
2018-01-11 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
PR target/83514
* config/arm/arm.c (arm_declare_function_name): Set arch_to_print if
targ_options->x_arm_arch_string is non NULL.
From-SVN: r256529
2018-01-11 Richard Biener <rguenther@suse.de>
Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR lto/81968
libiberty/
* simple-object-common.h (struct simple_object_functions):
Change copy_lto_debug_sections callback signature.
* simple-object-elf.c (SHN_HIRESERVE, SHT_SYMTAB_SHNDX,
SHF_INFO_LINK): Add defines.
(simple_object_elf_copy_lto_debug_sections): Instead of
leaving not to be copied sections empty unnamed SHT_NULL
remove them from the target section headers and adjust section
reference everywhere. Handle SHN_XINDEX in the symbol table
processing properly.
* simple-object.c (handle_lto_debug_sections): Change
interface to return a modified string and handle renaming
of relocation sections.
Co-Authored-By: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
From-SVN: r256528
The bug reported a particular test di-longlong64-sync-1.c failing when run
on arm-linux-gnueabi with options -mthumb -march=armv5t -O[g,1,2,3] and
-mthumb -march=armv6 -O[g,1,2,3].
The crash was caused because of the explicit VOIDmode argument that is sent
to emit_store_flag_force () and that the emit_store_flag_force () was not
handling the VOIDmode adequately. This patch fixes that.
ChangeLog entries:
*** gcc/ChangeLog ***
2017-01-11 Sudakshina Das <sudi.das@arm.com>
PR target/82096
* expmed.c (emit_store_flag_force): Swap if const op0
and change VOIDmode to mode of op0.
*** gcc/testsuite/ChangeLog ***
2017-01-11 Sudakshina Das <sudi.das@arm.com>
PR target/82096
* gcc.c-torture/compile/pr82096.c: New test.
From-SVN: r256526
The new opt_mode asserts triggered for replace_reg_with_saved_mem
because it was passing bytes rather than bits to mode_for_size.
Previously we ended up with a BLKmode register instead, but
presumably that didn't matter because this is "only" used for
debug insns.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
PR rtl-optimization/83761
* caller-save.c (replace_reg_with_saved_mem): Pass bits rather
than bytes to mode_for_size.
From-SVN: r256525
When an object of a type with a specified Default_Value aspect is
declared without an explicit initial value and the default value is
out of range of the objects subtype, the compiler now issues a warning
that Constraint_Error will be raised due to an out-of-range value.
The test below must output a compiler warning as follows:
$ gcc -c -gnatj70 default_warning.adb
default_warning.adb:7:08: warning: value not in range of type
"Subint" defined at line 5,
"Constraint_Error" will be raised at run
time
procedure Default_Warning is
type Int_With_Default is new Integer with Default_Value => 0;
subtype Subint is Int_With_Default range 1 .. 100;
S : Subint;
begin
null;
end Default_Warning;
2018-01-11 Gary Dismukes <dismukes@adacore.com>
gcc/ada/
* exp_ch3.adb (Default_Initialize_Object): Call New_Copy_Tree on the
result of Get_Simple_Init_Value and pass the source location of the
object declaration's object_definition.
From-SVN: r256524
The presence of an address clause complicates the build-in-place expansion
because the indicated address must be processed before the indirect call is
generated, including the definition of a local pointer to the object.
The address clause may come from an aspect specification or from an explicit
attribute specification appearing after the object declaration. These two
cases require different processing.
2018-01-11 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* exp_ch6.adb (Make_Build_In_Place_Call_In_Object_Declaration): Handle
properly object declarations with initializations that are
build-in-place function calls, when there is an address specification,
either as an aspect specification or an explicit attribute
specification clause, for the initialized object.
* freeze.adb (Check_Address_Clause): Do not remove side-effects from
initial expressions in the case of a build-in-place call.
gcc/testsuite/
* gnat.dg/bip_overlay.adb, gnat.dg/bip_overlay.ads: New testcase.
From-SVN: r256523
Frontend only calls Is_Null_Range and Not_Null_Range routines on full views
of types, but backends (for example GNATprove) might call them also on
private types. This patch adapts those routines to transparently retrieve
the full type when called on a private type.
No frontend test, because only external backends are affected.
2018-01-11 Piotr Trojanek <trojanek@adacore.com>
gcc/ada/
* sem_eval.adb (Is_Null_Range): Retrieve the full view when called on a
private (sub)type; refactor to avoid early return statement.
(Not_Null_Range): Same as above.
From-SVN: r256522
This patch ensures that single concurrent type declarations are marked as Ghost
when they appear within a Ghost region. In addition, the patch verifies that no
concurrent type is declared within a Ghost region and issues an error.
------------
-- Source --
------------
-- types.ads
package Types with Ghost is
protected Prot_Obj is -- Error
end Prot_Obj;
protected type Prot_Typ is -- Error
end Prot_Typ;
task Task_Obj; -- Error
task type Task_Typ; -- Error
end Types;
----------------------------
-- Compilation and output --
----------------------------
$ gcc -c types.ads
types.ads:2:14: ghost type "Prot_Obj" cannot be concurrent
types.ads:5:19: ghost type "Prot_Typ" cannot be concurrent
types.ads:8:09: ghost type "Task_Obj" cannot be concurrent
types.ads:10:14: ghost type "Task_Typ" cannot be concurrent
2018-01-11 Hristian Kirtchev <kirtchev@adacore.com>
gcc/ada/
* freeze.adb (Freeze_Entity): Ensure that a Ghost type is not
concurrent, nor effectively volatile.
* ghost.adb (Check_Ghost_Type): New routine.
* ghost.ads (Check_Ghost_Type): New routine.
* sem_util.adb (Is_Declaration): Reimplemented. The routine can now
consider specific subsets of declarations.
(Is_Declaration_Other_Than_Renaming): Removed. Its functionality is
replicated by Is_Declaration.
* sem_util.ads (Is_Declaration): New parameter profile. Update the
comment on usage.
(Is_Declaration_Other_Than_Renaming): Removed.
From-SVN: r256521
This patch modifies the analysis of assignment statements to detect an illegal
attempt to alter the value of single protected type Part_Of constituent when
inside a protected function.
2018-01-11 Hristian Kirtchev <kirtchev@adacore.com>
gcc/ada/
* sem_ch5.adb (Analyze_Assignment): Assignments to variables that act
as Part_Of consituents of single protected types are illegal when they
take place inside a protected function.
(Diagnose_Non_Variable_Lhs): Use Within_Function to check for an
enclosing function.
(Is_Protected_Part_Of_Constituent): New routine.
(Within_Function): New routine.
gcc/testsuite/
* gnat.dg/protected_func.adb, gnat.dg/protected_func.ads: New testcase.
From-SVN: r256520
This patch fixes an issue whereby an expression within an expression
function declaration or completion without proper parenthesization is
incorrectly accepted by the compiler.
2018-01-11 Justin Squirek <squirek@adacore.com>
gcc/ada/
* par-ch6.adb (Scan_Body_Or_Expression_Function): Add additional check
to make sure a given expression function is properly parenthesized.
gcc/testsuite/
* gnat.dg/expr_func4.adb: New testcase.
From-SVN: r256517
This patch modifies the analysis of subprogram bodies to catch a case where a
pure subprogram body unit depends on non-pure units.
2018-01-11 Hristian Kirtchev <kirtchev@adacore.com>
gcc/ada/
* sem_ch6.adb (Analyze_Subprogram_Body_Helper): Check the
categorization of a subprogram body which does not complete a previous
declaration.
gcc/testsuite/
* gnat.dg/pure_subp_body.adb, gnat.dg/pure_subp_body_pkg.ads: New
testcase.
From-SVN: r256516
