gcc/
* config/riscv/riscv-protos.h (riscv_expand_epilogue): Change bool arg
to int.
* config/riscv/riscv.c (riscv_for_each_saved_reg): New args epilogue
and maybe_eh_return. Change regno to unsigned int. Use new args to
handle EH_RETURN_DATA_REGNO registers properly.
(riscv_expand_prologue): Pass new args to riscv_for_each_saved_reg.
(riscv_expand_epilogue): Update comment. Change argument name and
type. Update code to use new name and type. Pass new args to
riscv_for_each_saved_reg. Only use EH_RETURN_STACKADJ_RTX when
EXCEPTION_RETURN.
* config/riscv/riscv.md (NORMAL_RETURN): New.
(SIBCALL_RETURN, EXCEPTION_RETURN): New.
(epilogue, sibcall_epilogue): Update riscv_expand_epilogue arg.
(eh_return): Call gen_eh_return_internal and emit barrier.
(eh_return_internal): Call riscv_expand_epilogue.
From-SVN: r261176
* gimple-ssa-store-merging.c (struct merged_store_group): Move up
bit_insertion field and declare can_be_merged_into method.
(merged_store_group::can_be_merged_into): New method.
(imm_store_chain_info::coalesce_immediate): Call it to decide whether
consecutive non-overlapping stores can be merged. Turn MEM_REF stores
into BIT_INSERT_EXPR stores if the group contains a non-MEM_REF store.
From-SVN: r261173
This patch fixes type traversal to avoid compiler crashes for test
cases where a type T includes an expression that refers back to the
type without actually explicitly mentioning T. Examples include
var x [uintptr(unsafe.Sizeof(&x))]byte
var a [len(a)]int
The fix involves expanding the set of types that the traversal code
"remembers" (to avoid cycles) to include array types, and introducing an
additional guard in Builtin_call_expression::do_is_constant to catch
cyclic type constructs.
Fixesgolang/go#25299Fixesgolang/go#25679Fixesgolang/go#25315Fixesgolang/go#25680
Reviewed-on: https://go-review.googlesource.com/115796
From-SVN: r261168
2018-06-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/85955
* builtins.c (fold_builtin_sincos): Convert pointers to
destination to appropriate type before dereferencing.
* gcc.dg/pr85955.c: New testcase.
From-SVN: r261165
Without this patch absif2 always FAILs. There is no testcase for
that, nor do we see it during bootstrap, but it is obvious.
* config/rs6000/rs6000.md (abs<mode>2 for FLOAT128): Handle IFmode.
From-SVN: r261158
The handling of bitfield references in expand_expr_real_1 includes:
machine_mode ext_mode = mode;
if (ext_mode == BLKmode
&& ! (target != 0 && MEM_P (op0)
&& MEM_P (target)
&& multiple_p (bitpos, BITS_PER_UNIT)))
ext_mode = int_mode_for_size (bitsize, 1).else_blk ();
if (ext_mode == BLKmode)
{
[...]
gcc_assert (MEM_P (op0)
Here "mode" is the TYPE_MODE of the result, so when mode == BLKmode,
the target must be a MEM if nonnull, since no other rtl objects can
have BLKmode. But there's no guarantee that the source value op0 is also
BLKmode and thus also a MEM: we can reach the assert for any source if
the bitsize being extracted is larger than the largest integer mode
(or larger than MAX_FIXED_MODE_SIZE).
This triggered for SVE with -msve-vector-bits=512, where we could
sometimes try to extract a BLKmode value from a 512-bit vector,
and where int_mode_for_size would rightly fail for large bitsizes.
The patch reuses the existing:
/* Otherwise, if this is a constant or the object is not in memory
and need be, put it there. */
else if (CONSTANT_P (op0) || (!MEM_P (op0) && must_force_mem))
{
memloc = assign_temp (TREE_TYPE (tem), 1, 1);
emit_move_insn (memloc, op0);
op0 = memloc;
clear_mem_expr = true;
}
to handle this case.
2018-05-29 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* expr.c (expand_expr_real_1): Force the operand into memory if
its TYPE_MODE is BLKmode and if there is no integer mode for
the number of bits being extracted.
gcc/testsuite/
* gcc.target/aarch64/sve/extract_5.c: New test.
From-SVN: r261150
2018-06-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/86038
* tracer.c (find_best_successor): Check probability for
being initialized, bail out if not.
* gcc.dg/pr86038.c: New testcase.
From-SVN: r261142
The XScale cpu configuration in GCC has always been somewhat
non-conforming. Although XScale isn't an architecture (it's simply an
implementation of ARMv5te), we do by tradition emit a specific
pre-define for it. We achieve this effect by adding an additional
feature bit to the xscale CPU definition that isn't part of the base
architecture.
When I restructured the options last year I overlooked this oddity and
the result, of course, is that this configuration now fails to build
as intended.
What happens is that the driver (correctly) constructs an architecture
for the xscale cpu name (as armv5te) and passes it in addition to the
CPU name. The backend code, on finding both a cpu and an architecture
specifies attempts to correlate the two and finds a difference due to
the additional feature bit and reports an inconsistency (fatally if
-werror is specified).
I think the best fix to this is to treat the xscale feature bit using
the same mechanism that we use for other 'quirks' in CPU
implementations and simply filter it out before comparing the
capabilities. It has the additional benefit that it's also the
simplest fix.
PR target/86003
* config/arm/arm-cpus.in (ALL_QUIRKS): Add xscale feature to the list
of bits to ignore when comparing architectures.
From-SVN: r261140
PR tree-optimization/69615
* fold-const.c (merge_ranges): If range1 is - [x, x] and x is the
maximum or minimum of the type, try to merge it also as if
range1 is + [-, x - 1] or + [x + 1, -].
* gcc.dg/pr69615.c: New test.
From-SVN: r261139
PR tree-optimization/86034
* gimple-ssa-store-merging.c (output_merged_store): Convert the RHS to
the unsigned bitfield type in a bit insertion sequence if it does not
have a larger precision than the bitfield size.
(process_store): Also bypass widening conversions for BIT_INSERT_EXPR.
From-SVN: r261128
2018-06-03 Paul Thomas <pault@gcc.gnu.org>
PR fortran/36497
* decl.c (variable_decl): Use gfc_add_type for cray pointees.
2018-06-03 Paul Thomas <pault@gcc.gnu.org>
PR fortran/36497
* gfortran.dg/cray_pointer_12.f90: New test.
From-SVN: r261127
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Constant>: If this is
not a definition, retrieve the expression only if it's a compile-time
known value if we are just annotating types.
* gcc-interface/utils.c (convert): Do not try to upcast properly for a
conversion between tagged types in type_annotate_only mode.
From-SVN: r261113
* gcc-interface/ada-tree.h (TYPE_PADDING_FOR_COMPONENT): New macro.
* gcc-interface/decl.c (gnat_to_gnu_component_type): Cache the padding
type built for an aliased component with variable size.
From-SVN: r261106
gcc/testsuite/ChangeLog:
2018-06-01 Carl Love <cel@us.ibm.com>
Commit 260294 on 2018-05-16 by Carl Love was supposed to add the
following files.
* gcc.target/powerpc/vsx-vector-6-be.p7.c: New test file.
* gcc.target/powerpc/vsx-vector-6-be.p8.c: New test file.
From-SVN: r261098
gcc/testsuite/ChangeLog:
2018-06-01 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/altivec-12.c (main): Fix declaration of ucz
to make it consistent with the naming convention in the file.
* gcc.target/powerpc/altivec-7-be.c: Move BE specific checks
to altivec-7.c. Delete file.
* gcc.target/powerpc/altivec-7-le.c: Move LE specific checks
to altivec-7.c. Delete file.
* gcc.target/powerpc/altivec-7.h: Move to altivec-7.c.
* gcc.target/powerpc/altivec-7.c (main): Add vec_unpackh and
vec_unpackl tests. Update instruction counts.
* gcc.target/powerpc/builtins-1-le.c: Move LE specific checks to
tests to builtins-1.c.
* gcc.target/powerpc/builtins-1-be.c: Move BE specific
tests to builtins-1.c.
* gcc.target/powerpc/builtins-1.h: Move to file builtins-1.c.
* gcc.target/powerpc/builtins-1.c (main): Add test case for vec_and.
vec_round, vec_rsqrt, vec_rsqrte, vec_mergee, vec_mergh, vec_mergo.
Remove vec_ctf tests returning double. Remove vec_cts with
double args. Remove vec_sel with invalid arguments. Add tests for
vec_splat.
Add instruction counts for new tests.
* gcc.target/powerpc/builtins-3-runnable.c (main): Add test for
vec_doublee, vec_doubleo, vec_doublel, vec_doubleh, vec_signed,
vec_unsigned.
* gcc.target/powerpc/builtins-3.c: Add tests test_sll_vuill_vuill_vuc,
test_sll_vsill_vsill_vuc.
* gcc.target/powerpc/p9-xxbr-2.c (rev_bool_long_long): Added test for
vec_revb.
* gcc.target/powerpc/vsx-7.h: Rename to vsx-7.c. Remove redundant
tests from altivec-7.h.
* gcc.target/powerpc/vsx-7-be.c: Remove file.
* gcc.target/powerpc/vsx-builtin-7.c: Add test functions splat_sc_s8,
splat_uc_u8, splat_ssi_s16, splat_usi_s16, splat_si_s32, splat_ui_u32,
splat_sll, splat_uc, splat_int128, splat_uint128.
Make second argument of vec_extract and vec_insert a signed int.
* gcc.target/powerpc/vsx-vector-5.c (vrint): Add vrint test for float
argument.
From-SVN: r261097
The loclists_base attribute is used to point to the beginning of the
loclists index of a DWARF5 loclists table when using DW_FORM_loclistsx.
For split compile units the base is not given by the attribute, but is
either the first (and only) index in the .debug_loclists.dwo section,
or (when placed in a .dwp file) given by the DW_SECT_LOCLISTS row in
the .debug_cu_index section.
The loclists_base attribute is only valid for the full (or skeleton)
compile unit DIE in the main (relocatable) object. But GCC only ever
generates a loclists table index for the .debug_loclists section put
into the split DWARF .dwo file.
For split compile unit DIEs it is confusing (and not according to spec)
to also have a DW_AT_loclists_base attribute (which might be wrong,
since its relocatable offset won't actually be relocated).
gcc/ChangeLog
* dwarf2out.c (dwarf2out_finish): Remove generation of
DW_AT_loclists_base.
From-SVN: r261092
* gimple-ssa-store-merging.c: Include gimple-fold.h.
(struct store_immediate_info): Document BIT_INSERT_EXPR stores.
(struct merged_store_group): Add bit_insertion field.
(dump_char_array): Use standard hexadecimal format.
(merged_store_group::merged_store_group): Set bit_insertion to false.
(merged_store_group::apply_stores): Use optimal buffer size. Deal
with BIT_INSERT_EXPR stores. Move up code updating the mask and
also print the mask in the dump file.
(pass_store_merging::gate): Minor tweak.
(imm_store_chain_info::coalesce_immediate): Fix wrong association
of stores with groups in dump. Allow coalescing of BIT_INSERT_EXPR
stores with INTEGER_CST stores.
(count_multiple_uses) <BIT_INSERT_EXPR>: New case.
(imm_store_chain_info::output_merged_store): Add try_bitpos variable
and use it throughout. Generate bit insertion sequences if need be.
(pass_store_merging::process_store): Remove redundant condition.
Record stores from a SSA name to a bit-field with BIT_INSERT_EXPR.
From-SVN: r261089
gcc/testsuite/ChangeLog:
2018-06-01 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/altivec-35.c (foo): Add builtin test vec_madds.
* gcc.target/powerpc/builtins-6-runnable.c (main): Fix typo for output.
Add vec_xst_be for signed and unsigned arguments.
From-SVN: r261088
