This improves a few things in change_zero_ext. Firstly, it should use
the passed in pattern in recog_for_combine, not the pattern of the insn
(they are not the same if the whole pattern was replaced). Secondly,
it handled zero_ext of a subreg, but with hard registers we do not get
a subreg, instead the mode of the reg is changed. So this handles that.
Thirdly, after changing a zero_ext to an AND, the resulting RTL may become
non-canonical, like (ior (ashift ..) (and ..)); the AND should be first,
it is commutative. And lastly, zero_extract as a set_dest wasn't handled
at all, but now it is.
This fixes the testcase in PR71847, and improves code generation in some
other edge cases too.
PR target/71847
* combine.c (change_zero_ext): Handle zero_ext of hard registers.
Swap commutative operands in new RTL if needed. Handle zero_ext
in the set_dest.
(recog_for_combine): Pass *pnewpat to change_zero_ext instead of
PATTERN (insn).
From-SVN: r241664
PR go/78144
libgo: incorporate fix for timezone test
This brings over the test-only fix for issue 17276 into gccgo/libgo
(with tzdata-2016g there is a new zone abbreviation). This is a
copy of https://golang.org/cl/29995.
Reviewed-on: https://go-review.googlesource.com/32182
From-SVN: r241661
PR go/78143
runtime: build lfstack_32bit.go on ppc
Missed a build tag. This is GCC PR 78143.
Reviewed-on: https://go-review.googlesource.com/32295
From-SVN: r241659
* include/experimental/bits/fs_path.h (__is_path_src)
(_S_range_begin, _S_range_end): Overload to treat string_view as a
Source object.
(path::operator+=, path::compare): Overload for basic_string_view.
* testsuite/experimental/filesystem/path/construct/string_view.cc:
New test.
* testsuite/experimental/filesystem/path/construct/
string_view_cxx17.cc: New test.
From-SVN: r241658
* dojump.c (do_jump_by_parts_greater_rtx): Invert probability when
swapping the arms of the branch.
* internal-fn.c (expand_addsub_overflow): Use a straight-line code
sequence for the generic signed-signed-signed case.
From-SVN: r241656
* include/experimental/bits/fs_path.h
(path::_S_convert<_Iter>(_Iter, _Iter)): Remove cv-qualifiers from
iterator's value_type.
(path::_S_convert<_Iter>(_Iter __first, __null_terminated)): Likewise.
Do not use operation not supported by input iterators.
(path::__is_path_iter_src): Add partial specialization for const
encoded character types.
* testsuite/experimental/filesystem/path/construct/range.cc: Test
construction from input iterators with const value types.
From-SVN: r241654
This patch makes scheduling not reorder prologue insns relative to
epilogue insns and vice versa. This fixes PR78029.
The problem in that PR:
We have two insns, in this order:
(insn/f 300 299 267 8 (set (reg:DI 65 lr)
(reg:DI 0 0)) 579 {*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 0 0)
(expr_list:REG_CFA_RESTORE (reg:DI 65 lr)
(nil))))
...
(insn/f 310 268 134 8 (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
(const_int 144 [0x90])) [6 S8 A8])
(reg:DI 0 0)) 579 {*movdi_internal64}
(expr_list:REG_DEAD (reg:DI 0 0)
(expr_list:REG_CFA_OFFSET (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
(const_int 144 [0x90])) [6 S8 A8])
(reg:DI 65 lr))
(nil))))
and sched swaps them (when compiling for power6, it tries to put memory
stores together, so insn 310 is moved up past 300 to go together with
some other store). But the REG_CFA_RESTORE and REG_CFA_OFFSET cannot be
swapped (they both say where the orig value of LR now lives).
PR rtl-optimization/78029
* function.c (prologue_contains, epilogue_contains): New functions.
(record_prologue_seq, record_epilogue_seq): New functions.
* function.h (prologue_contains, epilogue_contains,
record_prologue_seq, record_epilogue_seq): New declarations.
* sched-deps.c (sched_analyze_insn): Make dependencies to prevent
mixing prologue and epilogue insns.
(init_deps): Initialize the new fields in struct deps_desc.
* sched-int.h (struct deps_desc): New fields last_prologue,
last_epilogue, and last_logue_was_epilogue.
* shrink-wrap.c (emit_common_heads_for_components): Record all
emitted prologue and epilogue insns.
(emit_common_tails_for_components): Ditto.
(insert_prologue_epilogue_for_components): Ditto.
From-SVN: r241650
2016-10-28 Richard Biener <rguenther@suse.de>
PR middle-end/78128
PR middle-end/71002
* fold-const.c (make_bit_field_ref): Only adjust alias set
when the original alias set was zero.
From-SVN: r241645
This patch adds a magic OSC (operand store compare) break instruction
which is necessary if a store is followed closely by a load with same
base+indx+displ while either base or index get modified in between.
The patch improves several SpecCPU testcases running on IBM z13.
gcc/testsuite/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/oscbreak-1.c: New test.
gcc/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_adjust_loop_scan_osc): New function.
(s390_adjust_loops): New function.
(s390_reorg): Invoke s390_adjust_loops.
* config/s390/s390.md: (UNSPEC_OSC_BREAK): New constant.
("osc_break"): New insn definition.
From-SVN: r241644
This patch adds an alternate CPU level naming following the
architecture level number in the Principles of Operations manual. So
instead of having z196, zEC12, and z13 you can use arch9, arch10, and
arch11. The old cpu names stay valid and should preferably be used.
The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.
gcc/testsuite/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/target-attribute/tattr-m64-33.c: New test.
gcc/ChangeLog:
2016-10-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.opt: Support alternate cpu level naming (archXX).
* config.gcc: Support alternate archXX cpu levels with
--with-arch= and --with-tune=.
* config/s390/linux.h: Translate new archXX cpu levels to the
original names when calling GAS.
* config/s390/tpf.h: Likewise.
* doc/invoke.texi: Document the alternate cpu level names.
From-SVN: r241643
PR rtl-optimization/77919
* expr.c (expand_expr_real_1) <normal_inner_ref>: Force CONCAT into
MEM if mode1 is not a complex mode.
* g++.dg/torture/pr77919.C: New test.
From-SVN: r241642
PR rtl-optimization/78132
* ree.c (combine_reaching_defs): Give up if copy_needed and
!HARD_REGNO_MODE_OK (REGNO (src_reg), dst_mode).
* gcc.target/i386/pr78132.c: New test.
From-SVN: r241641
[gcc]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wH constraint): Add new
constraints for allowing 32-bit integers (and eventually 8/16-bit
integers) into the vector registers.
(wI constraint): Likewise.
(wJ constraint): Likewise.
(wK constraint): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mvsx-small-integer as a default option for ISA 2.07
(i.e. power8).
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
switch to turn off small integer support in vector registers.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
test for -mupper-regs-di, since it is already done with the
reg_add[mode].scalar_in_vsx_p. Add support for the switch
-mvsx-small-integer.
(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
constraints.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Add consistency checks for
-mvsx-small-integer.
(rs6000_secondary_reload_simple_move): SImode is a simple move if
-mvsx-small-integer.
(rs6000_secondary_reload): Use std::swap.
(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
VSX_REGS for small integers in vector registers, since there is no
D-FORM address mode for such types.
(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
(rs6000_opt_masks): Add -mvsx-small-integer.
* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
support.
(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
extracts can be done on ISA 2.07.
(vsx_extract_<mode>): Add support for small integers in vsx
registers.
(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
(vsx_extract_si): New insn to support extraction of SImode in ISA
2.07 using either xxextractuw or vspltw.
(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
wJ, and wK constraints.
* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
storing SDmode with VSX instructions.
(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
GPR load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add MFVSRWZ and XXEXTRACTUW instructions to support
small integers in vector registers.
(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add VEXTSW2D support for small integers in vector
registers.
(lfiwax): Remove ! constraint. Add VEXTSW2D support for small
integers in vector registers.
(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(lfiwzx): Remove ! constraint. Add XXEXTRACTUW support for small
integers in vector registers.
(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(movsi_internal1): Add support for -mvsx-small-integer. Align
columns so that it is more readable.
(SImode splitter for ISA 3.0 constants): Add splitter for
-128..127 constants that can easily be constructed on ISA 3.0.
* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
constraints.
[gcc/testsuite]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-simode.c: New test.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
From-SVN: r241631
PR fortran/78026
* parse.c (decode_statement): Don't create namespace for possible
select type here and destroy it afterwards.
(parse_select_type_block): Set gfc_current_ns to new_st.ext.block.ns.
(parse_executable, gfc_parse_file): Formatting fixes.
* match.c (gfc_match_select_type): Create namespace for select type
here, only after matching select type. Formatting fixes. Free that
namespace if not returning MATCH_YES, after gfc_undo_symbols,
otherwise remember it in new_st.ext.block.ns and switch to parent
namespace anyway.
* gfortran.dg/gomp/pr78026.f03: New test.
* gfortran.dg/select_type_38.f03: New test.
From-SVN: r241630
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Use end() function to get end iterator.
* testsuite/experimental/filesystem/iterators/pop.cc: Remove printf
statements that were present for debugging.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Use end() function to get end
iterator.
* testsuite/experimental/filesystem/operations/last_write_time.cc:
Only require file timestamps to be accurate to one second.
From-SVN: r241616
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.c (arm_split_atomic_op): Add function comment. Add
logic to to decide whether to copy over old value to register for new
value.
* config/arm/sync.md: Add comments explaning why mode and code
attribute are not defined in iterators.md
(thumb1_atomic_op_str): New code attribute.
(thumb1_atomic_newop_str): Likewise.
(thumb1_atomic_fetch_op_str): Likewise.
(thumb1_atomic_fetch_newop_str): Likewise.
(thumb1_atomic_fetch_oldop_str): Likewise.
(atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
mirror the more restrictive constraints of the Thumb-1 insns after
split compared to Thumb-2 counterpart insns.
(atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints
in sync with non atomic version.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<sync_optab><mode>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(atomic_<sync_optab>_fetch<mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
* config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
in sync with atomic version.
(thumb1_subsi3_insn): Likewise.
(thumb1_andsi3_insn): Likewise.
(thumb1_iorsi3_insn): Likewise.
(thumb1_xorsi3_insn): Likewise.
From-SVN: r241614
2016-10-26 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/78092
* trans-intrinsic.c (gfc_conv_intrinsic_sizeof): Fix reference to an
array element of type CLASS.
2016-10-26 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/78092
* gfortran.dg/pr78092.f90: New test.
From-SVN: r241610
gcc/ChangeLog:
2016-10-26 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/78056
* config/rs6000/rs6000.c (spe_init_builtins): Modify loops to not
define builtin functions from the bdesc_spe_predicates or
bdesc_spe_evsel arrays if the builtin mask is not compatible with
the current compiler configuration.
(paired_init_builtins): Modify loop to not define define builtin
functions from the bdesc_paried_preds array if the builtin mask is
not compatible with the current compiler configuration.
(altivec_init_builtins): Modify loops to not define the
__builtin_altivec_stxvl function nor the builtin functions from
the bdesc_dst or bdesc_altivec_preds, or bdesc_abs arrays if the
builtin mask is not compatible with the current compiler
configuration.
gcc/testsuite/ChangeLog:
2016-10-26 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/78056
* gcc.target/powerpc/vsu/vec-any-eqz-7.c (test_any_equal): Change
expected error message.
* gcc.target/powerpc/vsu/vec-xst-len-12.c (store_data): Change
expected error message.
* gcc.target/powerpc/vsu/vec-all-nez-7.c
(test_all_not_equal_and_not_zero): Change expected error message.
From-SVN: r241599
2016-10-26 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR libstdc++/78110
* libsupc++/new_opa.cc: Don't include <malloc.h> in a free standing
environment. Declare memalign directly in that case.
From-SVN: r241591
