2017-07-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/81502
* tree-ssa.c (non_rewritable_lvalue_p): Handle BIT_INSERT_EXPR
with incompatible but same sized type.
(execute_update_addresses_taken): Likewise.
* gcc.target/i386/vect-insert-1.c: New testcase.
From-SVN: r250620
While answering a user question on the equivalence of
-ftree-loop-vectorize + -ftree-slp-vectorize and -ftree-vectorize I
spotted one case which broke the equivalence. pass_ch::process_loop_p
was guarded on flag_tree_vectorize, meaning you would get it for
-ftree-vectorize, but not for -ftree-loop-vectorize/-ftree-slp-vectorize.
This patch fixes that, getting rid of the only use of flag_tree_vectorize
in the code base.
gcc/
* tree-ssa-loop-ch.c (pass_ch::process_loop_p): Guard on
flag_tree_loop_vectorize rather than flag_tree_vectorize.
From-SVN: r250619
The HI/QI atomic_fetch_<atomic><mode>" expander accepted symbolic
references and emitted CAS patterns whose insn predicates rejected them.
Fixed by allowing symbolic references there as well. Reload will get
rid of them due to the constraint letter.
Regression tested on s390x.
gcc/ChangeLog:
2017-07-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
PR target/81534
* config/s390/s390.md ("*atomic_compare_and_swap<mode>_1")
("*atomic_compare_and_swapdi_2", "*atomic_compare_and_swapsi_3"):
Change s_operand to memory_operand.
gcc/testsuite/ChangeLog:
2017-07-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
PR target/81534
* gcc.target/s390/pr81534.c: New test.
From-SVN: r250617
The little-endian VSX code uses rotates to swap the two 64-bit halves of
128-bit scalar modes. This is fine for TImode and V1TImode, but it
isn't really valid to use RTL rotates on floating-point modes like
KFmode and TFmode, and doing that triggered an assert added by the
SVE series. This patch uses bit-casts to V1TImode instead.
2017-07-27 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_permute): Declare.
* config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Replace with...
(rs6000_emit_le_vsx_permute): ...this. Take the destination as input.
Emit instructions rather than returning an expression. Handle TFmode
and KFmode by casting to TImode.
(rs6000_emit_le_vsx_load): Update to use rs6000_emit_le_vsx_permute.
(rs6000_emit_le_vsx_store): Likewise.
* config/rs6000/vsx.md (VSX_TI): New iterator.
(*vsx_le_permute_<mode>): Use it instead of VSX_LE_128.
(*vsx_le_undo_permute_<mode>): Likewise.
(*vsx_le_perm_load_<mode>): Use rs6000_emit_le_vsx_permute to
emit the split sequence.
(*vsx_le_perm_store_<mode>): Likewise.
From-SVN: r250615
PR tree-optimization/81555
PR tree-optimization/81556
* tree-ssa-reassoc.c (rewrite_expr_tree): Add NEXT_CHANGED argument,
if true, force CHANGED for the recursive invocation.
(reassociate_bb): Remember original length of ops array, pass
len != orig_len as NEXT_CHANGED in rewrite_expr_tree call.
* gcc.c-torture/execute/pr81555.c: New test.
* gcc.c-torture/execute/pr81556.c: New test.
From-SVN: r250609
* attribs.c (decl_attributes): Imply noinline, noclone and no_icf
attributes for noipa attribute. For naked attribute use
lookup_attribute first before lookup_attribute_spec.
* final.c (rest_of_handle_final): Disable IPA RA for functions with
noipa attribute.
* ipa-visibility.c (non_local_p): Fix comment typos. Return true
for functions with noipa attribute.
(cgraph_externally_visible_p): Return true for functions with noipa
attribute.
* cgraph.c (cgraph_node::get_availability): Return AVAIL_INTERPOSABLE
for functions with noipa attribute.
* doc/extend.texi: Document noipa function attribute.
* tree-ssa-structalias.c (refered_from_nonlocal_fn): Set *nonlocal_p
also for functions with noipa attribute.
(ipa_pta_execute): Set nonlocal_p also for nodes with noipa attribute.
c-family/
* c-attribs.c (c_common_attribute_table): Add noipa attribute.
(handle_noipa_attribute): New function.
testsuite/
* gcc.dg/attr-noipa.c: New test.
* gcc.dg/ipa/ipa-pta-18.c: New test.
* gcc.dg/ipa/ipa-sra-11.c: New test.
From-SVN: r250607
2017-07-26 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (thunderx_vector_cost): Decrease cost of
vec_unalign_load_cost and vec_unalign_store_cost.
From-SVN: r250597
[gcc]
2017-07-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify
code, only testing for DImode being allowed in non-VSX floating
point registers.
(rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER
to TARGET_P8_VECTOR test. Remove redundant VSX test inside of
another VSX test.
(rs6000_option_override_internal): Delete -mvsx-small-integer.
(rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER,
since TARGET_P9_VECTOR was already tested.
(rs6000_opt_masks): Remove -mvsx-small-integer.
* config/rs6000/vsx.md (vsx_extract_<mode>): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a
test for TARGET_VEXTRACTUB was used, and that uses
TARGET_P9_VECTOR.
(p9 extract splitter): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test
for TARGET_P9_VECTOR was used. Delete code that is now dead with
the elimination of TARGET_VSX_SMALL_INTEGER.
(vsx_extract_<mode>_p8): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.md (sign extend splitter): Change
TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(splitter for loading small constants): Likewise.
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
From-SVN: r250595
/cp
2017-07-26 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/71570
* lambda.c (add_capture): Early return if we cannot capture by
reference.
/testsuite
2017-07-26 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/71570
* g++.dg/cpp0x/lambda/lambda-ice17.C: New.
From-SVN: r250591
* configure.ac: Check for XCOFF32/XCOFF64. Check for loadquery.
* filetype.awk: Separate AIX XCOFF32 and XCOFF64.
* xcoff.c: Add support for AIX XCOFF32 and XCOFF64 formats.
* configure, config.h.in: Regenerate.
From-SVN: r250590
X86 prologue saves register at CFA offset. Since its location on stack
is computed as CFA - its CFA_OFFSET, CFA_OFFSET points the end of the
saved register area on stack. This patch updates sp_valid_at and
fp_valid_at to properly check saved register CFA offset.
gcc/
PR target/81563
* config/i386/i386.c (sp_valid_at): Properly check CFA offset.
(fp_valid_at): Likewise.
gcc/testsuite/
PR target/81563
* gcc.target/i386/pr81563.c: New test
From-SVN: r250587
The special case address cost tables for Cortex-A57 and qdf24xx are no
different from the generic address cost table. We should just use the
address cost table directly. If this changes in future, a core is welcome
to add new address cost tables.
gcc/
* config/aarch64/aarch64.c (cortexa57_addrcost_table): Remove.
(qdf24xx_addrcost_table): Likewise.
(cortexa57_tunings): Update to use generic_branch_cost.
(cortexa72_tunings): Likewise.
(cortexa73_tunings): Likewise.
(qdf24xx_tunings): Likewise.
From-SVN: r250585
PR c++/67054 - Inherited ctor with non-default-constructible members
* method.c (walk_field_subobs) Consider member initializers (NSDMIs)
when deducing an inheriting constructor.
From-SVN: r250583
All the cores in AArch64 use the pair {1, 3} for their branch costs. As
that is covered by generic_branch_cost, we can just use that directly and
save the tiny amount of redundant code. If in future any core wants to
modify this, they can always add a special-case branch-cost back.
gcc/
* config/aarch64/aarch64.c (cortexa57_branch_cost): Remove.
(thunderx2t99_branch_cost): Likewise.
(cortexa35_tunings): Update to use generic_branch_cost.
(cortexa53_tunings): Likewise.
(cortexa57_tunings): Likewise.
(cortexa72_tunings): Likewise.
(cortexa73_tunings): Likewise.
(thunderx2t99_tunings): Likewise.
From-SVN: r250582
Add the -mfsmuld option to control the generation of the FsMULd
instruction. In general, this instruction is available in architecture
version V8 and V9 CPUs with FPU. Some CPUs of this category do not
support this instruction properly, e.g. AT697E, AT697F and UT699. Some
CPUs of this category do not implement it in hardware, e.g. LEON3/4 with
GRFPU-lite.
gcc/
* config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD.
(sparc_option_override): Honour MASK_FSMULD.
* config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD.
* config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD.
* config/sparc/sparc.opt (mfsmuld): New option.
* doc/invoke.texi (mfsmuld): Document option.
From-SVN: r250570
2017-07-26 Richard Biener <rguenther@suse.de>
* gimple-match-head.c (do_valueize): Return OP if valueize
returns NULL_TREE.
(get_def): New helper to get at the def stmt of a SSA name
if valueize allows.
* genmatch.c (dt_node::gen_kids_1): Use get_def instead of
do_valueize to get at the def stmt.
(dt_operand::gen_gimple_expr): Simplify do_valueize calls.
* gcc/testsuite/gcc.dg/pr70920-2.c: Adjust for transform already
happening in ccp1.
* gcc/testsuite/gcc.dg/pr70920-4.c: Likewise.
From-SVN: r250565
Block auto increment on frame pointer references. This is never
beneficial since the SFP expands into SP+C or FP+C during register
allocation. The generated code for the testcase is now as expected:
str x30, [sp, -32]!
strb w0, [sp, 31]
add x0, sp, 31
bl foo3
ldr x30, [sp], 32
ret
gcc/
PR middle-end/46932
* auto-inc-dec.c (parse_add_or_inc): Block autoinc on sfp.
gcc/testsuite/
PR middle-end/46932
* gcc.dg/pr46932.c: New testcase.
From-SVN: r250564
2017-07-26 Martin Liska <mliska@suse.cz>
PR sanitize/81186
* function.c (expand_function_start): Make expansion of
nonlocal_goto_save_area after parm_birth_insn.
2017-07-26 Martin Liska <mliska@suse.cz>
PR sanitize/81186
* gcc.dg/asan/pr81186.c: New test.
From-SVN: r250561
All TARGET_DEFAULT defines set MASK_FPU. There is no need to set it in
some CPU target flags enable.
gcc/
* config/sparc/sparc.c (sparc_option_override): Remove MASK_FPU
from all CPU target flags enable members.
From-SVN: r250557
2017-07-25 Richard Biener <rguenther@suse.de>
* genmatch.c (dt_simplify::gen): Make iterator vars const.
(decision_tree::gen): Make 'type' const.
(write_predicate): Likewise.
From-SVN: r250556
gcc/ChangeLog:
2017-07-25 Carl Love <cel@us.ibm.com>
* doc/extend.texi: Update the built-in documentation file for the
existing built-in functions
vector signed char vec_cnttz (vector signed char);
vector unsigned char vec_cnttz (vector unsigned char);
vector signed short vec_cnttz (vector signed short);
vector unsigned short vec_cnttz (vector unsigned short);
vector signed int vec_cnttz (vector signed int);
vector unsigned int vec_cnttz (vector unsigned int);
vector signed long long vec_cnttz (vector signed long long);
vector unsigned long long vec_cnttz (vector unsigned long long);
gcc/testsuite/ChangeLog:
2017-07-25 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-4-p9-runnable.c: Add test file for
vec_cnttz builtins.
From-SVN: r250549
Add a new helper routine Type::finish_pointer_types that walks through
the pointer type cache and looks for placeholder types that may have
been created at some point before conversion of named types, and
invokes Type::finish_backend() on said placeholders. This is needed
to handle cases where the compiler manufactures a pointer type as part
of lowering, then a placeholder is created for it due to a call to
Type::backend_type_size(), but there is no explicit reference to the
type in user code.
Reviewed-on: https://go-review.googlesource.com/51131
From-SVN: r250548
* include/bits/ios_base.h (ios_base::io_state, ios_base::open_mode)
(ios_base::seek_dir): Remove for C++17.
* include/std/streambuf (basic_streambuf::stossc): Remove for C++17.
Add deprecated attribute for C++11 and C++14.
* testsuite/27_io/types/1.cc: Don't run for C++17 and later.
* testsuite/27_io/types/4.cc: New.
From-SVN: r250531
2017-07-25 Andrew Pinski <apinski@cavium.com>
* tree-ssa-uninit.c (warn_uninitialized_vars): Don't warn about memory
accesses where the use is for the first operand of a BIT_INSERT.
From-SVN: r250530
gcc/
PR bootstrap/81521
* config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look
for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS.
From-SVN: r250529
* config/i386/i386.c (ix86_decompose_address): Do not check for
register RTX when looking at index_reg or base_reg.
* config/i386/i386.h (INCOMING_RETURN_ADDR_RTX): Use stack_pointer_rtx.
From-SVN: r250526
* gimple.c (gimple_assign_set_rhs_with_ops): Do not ask gsi_replace
to update EH info here.
ada/
* checks.adb (Apply_Divide_Checks): Ensure that operands are not
evaluated twice.
From-SVN: r250525
2017-07-07 Torsten Duwe <duwe@suse.de>
c-family/
* c-attribs.c (c_common_attribute_table): Add entry for
"patchable_function_entry".
lto/
* lto-lang.c (lto_attribute_table): Add entry for
"patchable_function_entry".
* common.opt: Introduce -fpatchable-function-entry
command line option, and its variables function_entry_patch_area_size
and function_entry_patch_area_start.
* opts.c (common_handle_option): Add -fpatchable_function_entry_ case,
including a two-value parser.
* target.def (print_patchable_function_entry): New target hook.
* targhooks.h (default_print_patchable_function_entry): New function.
* targhooks.c (default_print_patchable_function_entry): Likewise.
* toplev.c (process_options): Switch off IPA-RA if
patchable function entries are being generated.
* varasm.c (assemble_start_function): Look at the
patchable-function-entry command line switch and current
function attributes and maybe generate NOP instructions by
calling the print_patchable_function_entry hook.
* doc/extend.texi: Document patchable_function_entry attribute.
* doc/invoke.texi: Document -fpatchable_function_entry
command line option.
* doc/tm.texi.in (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY):
New target hook.
* doc/tm.texi: Re-generate.
* c-c++-common/patchable_function_entry-default.c: New test.
* c-c++-common/patchable_function_entry-decl.c: Likewise.
* c-c++-common/patchable_function_entry-definition.c: Likewise.
From-SVN: r250521
PR target/81532
* config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for
TARGET_AVX512DQ rather than TARGET_AVX512BW.
* gcc.target/i386/pr80833-3.c: New test.
* gcc.target/i386/avx512dq-pr81532.c: New test.
* gcc.target/i386/avx512bw-pr81532.c: New test.
From-SVN: r250520
2017-07-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/81455
* tree-ssa-loop-unswitch.c (find_loop_guard): Make sure to
not walk in cycles when looking for guards.
* gcc.dg/pr81455.c: New testcase.
From-SVN: r250518
* dwarf2asm.c (dw2_asm_output_nstring): Encode double quote
character for AIX.
* dwarf2out.c (output_macinfo): Copy debug_line_section_label
to dl_section_ref. On AIX, append an expression to subtract
the size of the section length to dl_section_ref.
From-SVN: r250516
Martin Liska
Richard Biener
James Greenhalgh
Andreas Krebbel
Richard Sandiford
Jakub Jelinek
GCC Administrator
Andrew Pinski
Michael Meissner
Jonathan Wakely
Ian Lance Taylor
Paolo Carlini
Tony Reix
Ian Lance Taylor
H.J. Lu
Jason Merrill
Leonid Koppel
Sebastian Huber
Wilco Dijkstra
Marek Polacek
Carl Love
Jim Wilson
Uros Bizjak
Eric Botcazou
Alexander Monakov
Alexander Monakov
Torsten Duwe
Jakub Jelinek
Tamar Christina
David Edelsohn