c-family/ChangeLog
2014-06-20 Hale Wang <hale.wang@arm.com>
PR lto/61123
* c.opt (fshort-enums): Add to LTO.
* c.opt (fshort-wchar): Likewise.
testsuite/ChangeLog
2014-06-20 Hale Wang <hale.wang@arm.com>
* gcc.target/arm/lto/: New folder to verify the LTO option.
* gcc.target/arm/lto/pr61123-enum-size_0.c: New test case.
* gcc.target/arm/lto/pr61123-enum-size_1.c: Likewise.
* gcc.target/arm/lto/lto.exp: New exp file used to test LTO option.
* lib/lto.exp (object-readelf): New procedure.
From-SVN: r211832
2014-06-19 Tom de Vries <tom@codesourcery.com>
* config/aarch64/aarch64-protos.h (aarch64_emit_call_insn): Change
return type to void.
* config/aarch64/aarch64.c (aarch64_emit_call_insn): Same.
From-SVN: r211823
2014-06-19 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* loop-invariant.c (get_inv_cost): Skip invariants, which are marked
as "move", from depends_on.
From-SVN: r211818
A comment in rs6000.h says "cr5 is not supposed to be used". I checked
all ABIs, going as far back as PowerOpen (1994), and found no mention
of this.
Also document cr6 is used by some vector instructions.
From-SVN: r211811
gcc/
* config/mips/constraints.md ("d"): BASE_REG_CLASS replaced by
"TARGET_MIPS16 ? M16_REGS : GR_REGS".
* config/mips/mips.c (mips_regno_to_class): Update for M16_SP_REGS.
(mips_regno_mode_ok_for_base_p): Remove use of !strict_p for MIPS16.
(mips_register_priority): New function that implements the target
hook TARGET_REGISTER_PRIORITY.
(mips_spill_class): Likewise for TARGET_SPILL_CLASS.
(mips_lra_p): Likewise for TARGET_LRA_P.
(TARGET_REGISTER_PRIORITY): Define macro.
(TARGET_SPILL_CLASS): Likewise.
(TARGET_LRA_P): Likewise.
* config/mips/mips.h (reg_class): Add M16_SP_REGS and SPILL_REGS
classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(BASE_REG_CLASS): Use M16_SP_REGS.
* config/mips/mips.md (*mul_acc_si): Add alternative tuned for LRA.
New set attribute to enable alternatives depending on the register
allocator used.
(*mul_acc_si_r3900, *mul_sub_si): Likewise.
(*lea64): Disable pattern for MIPS16.
* config/mips/mips.opt (mlra): New option.
From-SVN: r211805
2014-06-18 Radovan Obradovic <robradovic@mips.com>
Tom de Vries <tom@codesourcery.com>
* config/arm/arm-protos.h (arm_emit_call_insn): Add bool parameter.
* config/arm/arm.c (TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS):
Redefine to true.
(arm_emit_call_insn): Add and use sibcall parameter. Add IP and CC
clobbers to CALL_INSN_FUNCTION_USAGE.
(define_expand "sibcall_internal")
(define_expand "sibcall_value_internal"): New.
(define_expand "call", define_expand "call_value"): Add argument to
arm_emit_call_insn.
(define_expand "sibcall"): Use sibcall_internal and arm_emit_call_insn.
(define_expand "sibcall_value"): Use sibcall_value_internal and
arm_emit_call_insn.
* gcc.target/arm/fuse-caller-save.c: New test.
Co-Authored-By: Tom de Vries <tom@codesourcery.com>
From-SVN: r211798
2014-06-18 Charles Baylis <charles.baylis@linaro.org>
* config/arm/bpabi.S (__aeabi_ldivmod): Perform division using
__udivmoddi4, and fixups for negative operands.
From-SVN: r211794
2014-06-18 Charles Baylis <charles.baylis@linaro.org>
* config/arm/bpabi.S (__aeabi_uldivmod): Perform division using call
to __udivmoddi4.
From-SVN: r211792
2014-06-18 Charles Baylis <charles.baylis@linaro.org>
* config/arm/bpabi.S (__aeabi_uldivmod, __aeabi_ldivmod): Add comment
describing register usage on function entry and exit.
From-SVN: r211790
PR tree-optimization/61518
gcc/
* tree-if-conv.c (is_cond_scalar_reduction): Add missed check that
reduction var is used in reduction stmt or phi-function only.
gcc/testsuite/
* gcc.dg/torture/pr61518.c: New test.
From-SVN: r211780
2014-06-18 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
PR tree-optimization/61517
* tree-ssa-math-opts.c (find_bswap_or_nop_1): Adapt to return a stmt
whose rhs's first tree is the source expression instead of the
expression itself.
(find_bswap_or_nop): Likewise.
(bsap_replace): Rename stmt in cur_stmt. Pass gsi by value and src as a
gimple stmt whose rhs's first tree is the source. In the memory source
case, move the stmt to be replaced close to one of the original load to
avoid the problem of a store between the load and the stmt's original
location.
(pass_optimize_bswap::execute): Adapt to change in bswap_replace's
signature.
gcc/testsuite/
* gcc.c-torture/execute/bswap-2.c (incorrect_read_le32): New.
(incorrect_read_be32): Likewise.
(main): Call incorrect_read_* to test stmt replacement is made by
bswap at the right place.
* gcc.c-torture/execute/pr61517.c: New test.
From-SVN: r211778
PR rtl-optimization/54555
* postreload.c (move2add_use_add2_insn): Substitute
STRICT_LOW_PART only if it is cheaper.
testsuite/:
PR rtl-optimization/54555
* gcc.target/m68k/pr54555.c: New test.
From-SVN: r211777
* config/i386/i386.md (*sibcall_memory): Rename from *sibcall_intern.
Do not use unspec as call operand. Use memory_operand instead of
memory_nox32_operand and add "m" operand constraint. Disable
pattern for TARGET_X32.
(*sibcall_pop_memory): Ditto.
(*sibcall_value_memory): Ditto.
(*sibcall_value_pop_memory): Ditto.
(sibcall peepholes): Merge SImode and DImode patterns using
W mode iterator. Use memory_operand instead of memory_nox32_operand.
Disable pattern for TARGET_X32. Check if eliminated register is
really dead after call insn. Generate call RTX without unspec operand.
(sibcall_value peepholes): Ditto.
(sibcall_pop peepholes): Fix call insn RTXes. Use memory_operand
instead of memory_nox32_operand. Check if eliminated register is
really dead after call insn. Generate call RTX without unspec operand.
(sibcall_value_pop peepholes): Ditto.
* config/i386/predicates.md (memory_nox32_operand): Remove predicate.
From-SVN: r211776
2014-06-18 Terry Guo <terry.guo@arm.com>
PR target/61544
* config/arm/arm.c (thumb1_reorg): Move to next basic block if we
reach the head.
From-SVN: r211775
2014-06-18 Paolo Carlini <paolo.carlini@oracle.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR libstdc++/61536
* config/abi/pre/gnu.ver: Adjust for out of line comparisons.
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
From-SVN: r211774
2014-06-18 Olivier Hainque <hainque@adacore.com>
improve sloc assignment on bind_expr entry/exit code
gcc/
* tree-core.h (tree_block): Add an "end_locus" field, allowing
memorization of the end of block source location.
* tree.h (BLOCK_SOURCE_END_LOCATION): New accessor.
* gimplify.c (gimplify_bind_expr): Propagate the block start and
end source location info we have on the block entry/exit code we
generate.
testsuite/
* gnat.dg/blocklocs.adb: New test.
From-SVN: r211773
* genattrtab.c (n_bypassed): New variable.
(process_bypasses): Initialise n_bypassed.
Count number of bypassed reservations.
(make_automaton_attrs): Allocate space for bypassed reservations
rather than number of bypasses.
From-SVN: r211771
2014-06-18 Richard Biener <rguenther@suse.de>
* tree-ssa-propagate.c (replace_phi_args_in): Return whether
we propagated anything.
(substitute_and_fold_dom_walker::before_dom_children): Something
changed if we propagated into PHI arguments.
* tree-ssa-pre.c (eliminate): Always schedule cfg-cleanup if
we removed a stmt.
From-SVN: r211770
gcc/
* config/i386/i386.c (ix86_reassociation_width): Add alternative for
vector case.
* config/i386/i386.h (TARGET_VECTOR_PARALLEL_EXECUTION): New.
* config/i386/x86-tune.def (X86_TUNE_VECTOR_PARALLEL_EXECUTION): New.
* tree-vect-data-refs.c (vect_shift_permute_load_chain): New.
Introduces alternative way of loads group permutaions.
(vect_transform_grouped_load): Try alternative way of permutations.
gcc/testsuite/
PR tree-optimization/52252
* gcc.target/i386/pr52252-atom.c: Test on loads group of size 3.
* gcc.target/i386/pr52252-core.c: Ditto.
PR tree-optimization/61403
* gcc.target/i386/pr61403.c: Test on loads and stores group of size 3.
From-SVN: r211769
