115 lines
3.9 KiB
C++
115 lines
3.9 KiB
C++
//===-- sanitizer_atomic_clang_x86.h ----------------------------*- C++ -*-===//
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of ThreadSanitizer/AddressSanitizer runtime.
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// Not intended for direct inclusion. Include sanitizer_atomic.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SANITIZER_ATOMIC_CLANG_X86_H
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#define SANITIZER_ATOMIC_CLANG_X86_H
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namespace __sanitizer {
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INLINE void proc_yield(int cnt) {
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__asm__ __volatile__("" ::: "memory");
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for (int i = 0; i < cnt; i++)
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__asm__ __volatile__("pause");
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__asm__ __volatile__("" ::: "memory");
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}
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template<typename T>
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INLINE typename T::Type atomic_load(
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const volatile T *a, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_consume
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| memory_order_acquire | memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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typename T::Type v;
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if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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// Assume that aligned loads are atomic.
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if (mo == memory_order_relaxed) {
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v = a->val_dont_use;
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} else if (mo == memory_order_consume) {
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// Assume that processor respects data dependencies
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// (and that compiler won't break them).
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__asm__ __volatile__("" ::: "memory");
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v = a->val_dont_use;
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__asm__ __volatile__("" ::: "memory");
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} else if (mo == memory_order_acquire) {
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__asm__ __volatile__("" ::: "memory");
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v = a->val_dont_use;
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// On x86 loads are implicitly acquire.
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__asm__ __volatile__("" ::: "memory");
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} else { // seq_cst
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// On x86 plain MOV is enough for seq_cst store.
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__asm__ __volatile__("" ::: "memory");
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v = a->val_dont_use;
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__asm__ __volatile__("" ::: "memory");
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}
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} else {
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// 64-bit load on 32-bit platform.
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__asm__ __volatile__(
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"movq %1, %%mm0;" // Use mmx reg for 64-bit atomic moves
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"movq %%mm0, %0;" // (ptr could be read-only)
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"emms;" // Empty mmx state/Reset FP regs
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: "=m" (v)
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: "m" (a->val_dont_use)
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: // mark the FP stack and mmx registers as clobbered
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"st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
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#ifdef __MMX__
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"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
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#endif // #ifdef __MMX__
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"memory");
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}
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return v;
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}
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template<typename T>
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INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_release
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| memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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// Assume that aligned loads are atomic.
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if (mo == memory_order_relaxed) {
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a->val_dont_use = v;
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} else if (mo == memory_order_release) {
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// On x86 stores are implicitly release.
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__asm__ __volatile__("" ::: "memory");
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a->val_dont_use = v;
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__asm__ __volatile__("" ::: "memory");
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} else { // seq_cst
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// On x86 stores are implicitly release.
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__asm__ __volatile__("" ::: "memory");
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a->val_dont_use = v;
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__sync_synchronize();
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}
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} else {
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// 64-bit store on 32-bit platform.
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__asm__ __volatile__(
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"movq %1, %%mm0;" // Use mmx reg for 64-bit atomic moves
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"movq %%mm0, %0;"
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"emms;" // Empty mmx state/Reset FP regs
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: "=m" (a->val_dont_use)
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: "m" (v)
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: // mark the FP stack and mmx registers as clobbered
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"st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
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#ifdef __MMX__
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"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
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#endif // #ifdef __MMX__
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"memory");
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if (mo == memory_order_seq_cst)
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__sync_synchronize();
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}
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}
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} // namespace __sanitizer
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#endif // #ifndef SANITIZER_ATOMIC_CLANG_X86_H
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