aa4945c138
gcc/
2009-11-11 Jon Beniston <jon@beniston.com>
* config.gcc: Add lm32 elf and uclinux targets.
* config/lm32: New directory.
* config/lm32/lm32.c: New file.
* config/lm32/lm32.h: New file.
* config/lm32/lm32.md: New file.
* config/lm32/lm32.opt: New file.
* config/lm32/lm32-protos.h: New file.
* config/lm32/constraints.md: New file.
* config/lm32/predicates.md: New file.
* config/lm32/sfp-machine.h: New file.
* config/lm32/t-fprules-softfp: New file.
* config/lm32/uclinux-elf.h: New file.
* doc/invoke.texi: Document lm32 options.
* doc/contrib.texi: Document lm32 porter.
* doc/install.texi: Document lm32 targets.
gcc/testsuite/
2009-11-11 Jon Beniston <jon@beniston.com>
* lib/target-supports.exp (check_profiling_available): lm32 target
doesn't support profiling.
* gcc.dg/20020312-2.c: Add lm32 support.
* g++.dg/other/packed1.C: Expect to fail on lm32.
* g++.old-deja/g++.jason/thunk3.C: Likewise.
libgcc/
2009-11-11 Jon Beniston <jon@beniston.com>
* config.host: Add lm32 targets.
* config/lm32: New directory.
* config/lm32/libgcc_lm32.h: New file.
* config/lm32/_mulsi3.c: New file.
* config/lm32/_udivmodsi4.c: New file.
* config/lm32/_divsi3.c: New file.
* config/lm32/_modsi3.c: New file.
* config/lm32/_udivsi3.c: New file.
* config/lm32/_umodsi3.c: New file.
* config/lm32/_lshrsi3.S: New file.
* config/lm32/_ashrsi3.S: New file.
* config/lm32/_ashlsi3.S: New file.
* config/lm32/crti.S: New file.
* config/lm32/crtn.S: New file.
* config/lm32/t-lm32: New file.
* config/lm32/t-elf: New file.
* config/lm32/t-uclinux: New file.
From-SVN: r154096
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/* _divsi3 for Lattice Mico32.
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Contributed by Jon Beniston <jon@beniston.com>
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Copyright (C) 2009 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 3, or (at your option) any
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "libgcc_lm32.h"
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/* Signed integer division. */
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static const UQItype __divsi3_table[] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 4, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 5, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 6, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 7, 3, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 8, 4, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
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0, 9, 4, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
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0, 10, 5, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
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0, 11, 5, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
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0, 12, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 13, 6, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
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0, 14, 7, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0,
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0, 15, 7, 5, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
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};
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SItype
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__divsi3 (SItype a, SItype b)
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{
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int neg = 0;
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SItype res;
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int cfg;
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if (b == 0)
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{
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/* Raise divide by zero exception. */
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int eba, sr;
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/* Save interrupt enable. */
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__asm__ __volatile__ ("rcsr %0, IE":"=r" (sr));
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sr = (sr & 1) << 1;
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__asm__ __volatile__ ("wcsr IE, %0"::"r" (sr));
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/* Branch to exception handler. */
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__asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
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eba += 32 * 5;
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__asm__ __volatile__ ("mv ea, ra");
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__asm__ __volatile__ ("b %0"::"r" (eba));
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__builtin_unreachable ();
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}
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if (((USItype) (a | b)) < 16)
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res = __divsi3_table[(a << 4) + b];
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else
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{
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if (a < 0)
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{
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a = -a;
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neg = !neg;
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}
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if (b < 0)
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{
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b = -b;
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neg = !neg;
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}
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__asm__ ("rcsr %0, CFG":"=r" (cfg));
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if (cfg & 2)
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__asm__ ("divu %0, %1, %2": "=r" (res):"r" (a), "r" (b));
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else
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res = __udivmodsi4 (a, b, 0);
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if (neg)
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res = -res;
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}
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return res;
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}
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