141 lines
3.5 KiB
C++
141 lines
3.5 KiB
C++
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@redhat.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifdef HAVE_SYS_AUXV_H
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#include <sys/auxv.h>
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#endif
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namespace GTM HIDDEN {
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typedef int v128 __attribute__((vector_size(16), may_alias, aligned(16)));
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typedef struct gtm_jmpbuf
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{
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#if defined(__ALTIVEC__) || defined(__VSX__)
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v128 vr[12]; /* vr20-vr31 */
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unsigned long long vscr; /* long long for padding only */
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#endif
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#ifndef _SOFT_FLOAT
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double fr[18]; /* f14-f31 */
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double fpscr;
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#endif
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unsigned long gr[18]; /* r14-r31 */
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void *cfa;
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unsigned long pc;
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unsigned long toc; /* r2 on aix, r13 on darwin */
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unsigned long cr;
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} gtm_jmpbuf;
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/* The size of one line in hardware caches (in bytes). */
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#if defined (__powerpc64__) || defined (__ppc64__)
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# define HW_CACHELINE_SIZE 128
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#else
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# define HW_CACHELINE_SIZE 32
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#endif
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static inline void
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cpu_relax (void)
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{
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__asm volatile ("" : : : "memory");
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}
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// Use HTM if it is supported by the system.
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// See gtm_thread::begin_transaction for how these functions are used.
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#if defined (__linux__) \
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&& defined (HAVE_AS_HTM) \
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&& defined (HAVE_GETAUXVAL) \
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&& defined (AT_HWCAP2) \
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&& defined (PPC_FEATURE2_HAS_HTM)
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#include <htmintrin.h>
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#define USE_HTM_FASTPATH
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#define _TBEGIN_STARTED 0
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#define _TBEGIN_INDETERMINATE 1
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#define _TBEGIN_PERSISTENT 2
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/* Number of retries for transient failures. */
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#define _HTM_RETRIES 10
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static inline bool
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htm_available (void)
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{
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return (getauxval (AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) ? true : false;
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}
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static inline uint32_t
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htm_init (void)
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{
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// Maximum number of times we try to execute a transaction
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// as a HW transaction.
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return htm_available () ? _HTM_RETRIES : 0;
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}
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static inline uint32_t
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htm_begin (void)
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{
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if (__builtin_expect (__builtin_tbegin (0), 1))
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return _TBEGIN_STARTED;
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if (_TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ()))
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return _TBEGIN_PERSISTENT;
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return _TBEGIN_INDETERMINATE;
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}
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static inline bool
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htm_begin_success (uint32_t begin_ret)
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{
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return begin_ret == _TBEGIN_STARTED;
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}
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static inline void
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htm_commit (void)
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{
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__builtin_tend (0);
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}
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static inline void
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htm_abort (void)
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{
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__builtin_tabort (0);
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}
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static inline bool
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htm_abort_should_retry (uint32_t begin_ret)
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{
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return begin_ret != _TBEGIN_PERSISTENT;
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}
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/* Returns true iff a hardware transaction is currently being executed. */
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static inline bool
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htm_transaction_active (void)
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{
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return (_HTM_STATE (__builtin_ttest ()) == _HTM_TRANSACTIONAL);
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}
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#endif
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} // namespace GTM
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