1224 lines
33 KiB
C
1224 lines
33 KiB
C
/* DDG - Data Dependence Graph implementation.
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Copyright (C) 2004-2018 Free Software Foundation, Inc.
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Contributed by Ayal Zaks and Mustafa Hagog <zaks,mustafa@il.ibm.com>
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "backend.h"
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#include "rtl.h"
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#include "df.h"
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#include "insn-attr.h"
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#include "sched-int.h"
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#include "ddg.h"
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#include "rtl-iter.h"
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#ifdef INSN_SCHEDULING
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/* A flag indicating that a ddg edge belongs to an SCC or not. */
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enum edge_flag {NOT_IN_SCC = 0, IN_SCC};
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/* Forward declarations. */
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static void add_backarc_to_ddg (ddg_ptr, ddg_edge_ptr);
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static void add_backarc_to_scc (ddg_scc_ptr, ddg_edge_ptr);
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static void add_scc_to_ddg (ddg_all_sccs_ptr, ddg_scc_ptr);
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static void create_ddg_dep_from_intra_loop_link (ddg_ptr, ddg_node_ptr,
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ddg_node_ptr, dep_t);
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static void create_ddg_dep_no_link (ddg_ptr, ddg_node_ptr, ddg_node_ptr,
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dep_type, dep_data_type, int);
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static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type,
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dep_data_type, int, int);
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static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr);
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/* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */
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static bool mem_ref_p;
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/* Auxiliary function for mem_read_insn_p. */
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static void
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mark_mem_use (rtx *x, void *)
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{
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subrtx_iterator::array_type array;
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FOR_EACH_SUBRTX (iter, array, *x, NONCONST)
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if (MEM_P (*iter))
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{
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mem_ref_p = true;
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break;
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}
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}
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/* Returns nonzero if INSN reads from memory. */
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static bool
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mem_read_insn_p (rtx_insn *insn)
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{
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mem_ref_p = false;
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note_uses (&PATTERN (insn), mark_mem_use, NULL);
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return mem_ref_p;
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}
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static void
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mark_mem_store (rtx loc, const_rtx setter ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
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{
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if (MEM_P (loc))
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mem_ref_p = true;
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}
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/* Returns nonzero if INSN writes to memory. */
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static bool
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mem_write_insn_p (rtx_insn *insn)
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{
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mem_ref_p = false;
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note_stores (PATTERN (insn), mark_mem_store, NULL);
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return mem_ref_p;
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}
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/* Returns nonzero if X has access to memory. */
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static bool
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rtx_mem_access_p (rtx x)
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{
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int i, j;
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const char *fmt;
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enum rtx_code code;
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if (x == 0)
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return false;
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if (MEM_P (x))
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return true;
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code = GET_CODE (x);
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fmt = GET_RTX_FORMAT (code);
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for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
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{
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if (fmt[i] == 'e')
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{
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if (rtx_mem_access_p (XEXP (x, i)))
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return true;
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}
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else if (fmt[i] == 'E')
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for (j = 0; j < XVECLEN (x, i); j++)
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{
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if (rtx_mem_access_p (XVECEXP (x, i, j)))
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return true;
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}
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}
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return false;
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}
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/* Returns nonzero if INSN reads to or writes from memory. */
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static bool
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mem_access_insn_p (rtx_insn *insn)
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{
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return rtx_mem_access_p (PATTERN (insn));
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}
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/* Return true if DEF_INSN contains address being auto-inc or auto-dec
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which is used in USE_INSN. Otherwise return false. The result is
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being used to decide whether to remove the edge between def_insn and
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use_insn when -fmodulo-sched-allow-regmoves is set. This function
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doesn't need to consider the specific address register; no reg_moves
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will be allowed for any life range defined by def_insn and used
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by use_insn, if use_insn uses an address register auto-inc'ed by
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def_insn. */
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bool
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autoinc_var_is_used_p (rtx_insn *def_insn, rtx_insn *use_insn)
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{
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rtx note;
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for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1))
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if (REG_NOTE_KIND (note) == REG_INC
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&& reg_referenced_p (XEXP (note, 0), PATTERN (use_insn)))
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return true;
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return false;
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}
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/* Return true if one of the definitions in INSN has MODE_CC. Otherwise
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return false. */
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static bool
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def_has_ccmode_p (rtx_insn *insn)
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{
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df_ref def;
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FOR_EACH_INSN_DEF (def, insn)
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{
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machine_mode mode = GET_MODE (DF_REF_REG (def));
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if (GET_MODE_CLASS (mode) == MODE_CC)
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return true;
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}
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return false;
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}
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/* Computes the dependence parameters (latency, distance etc.), creates
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a ddg_edge and adds it to the given DDG. */
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static void
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create_ddg_dep_from_intra_loop_link (ddg_ptr g, ddg_node_ptr src_node,
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ddg_node_ptr dest_node, dep_t link)
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{
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ddg_edge_ptr e;
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int latency, distance = 0;
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dep_type t = TRUE_DEP;
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dep_data_type dt = (mem_access_insn_p (src_node->insn)
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&& mem_access_insn_p (dest_node->insn) ? MEM_DEP
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: REG_DEP);
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gcc_assert (src_node->cuid < dest_node->cuid);
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gcc_assert (link);
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/* Note: REG_DEP_ANTI applies to MEM ANTI_DEP as well!! */
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if (DEP_TYPE (link) == REG_DEP_ANTI)
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t = ANTI_DEP;
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else if (DEP_TYPE (link) == REG_DEP_OUTPUT)
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t = OUTPUT_DEP;
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gcc_assert (!DEBUG_INSN_P (dest_node->insn) || t == ANTI_DEP);
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gcc_assert (!DEBUG_INSN_P (src_node->insn) || t == ANTI_DEP);
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/* We currently choose not to create certain anti-deps edges and
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compensate for that by generating reg-moves based on the life-range
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analysis. The anti-deps that will be deleted are the ones which
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have true-deps edges in the opposite direction (in other words
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the kernel has only one def of the relevant register).
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If the address that is being auto-inc or auto-dec in DEST_NODE
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is used in SRC_NODE then do not remove the edge to make sure
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reg-moves will not be created for this address.
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TODO: support the removal of all anti-deps edges, i.e. including those
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whose register has multiple defs in the loop. */
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if (flag_modulo_sched_allow_regmoves
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&& (t == ANTI_DEP && dt == REG_DEP)
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&& !def_has_ccmode_p (dest_node->insn)
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&& !autoinc_var_is_used_p (dest_node->insn, src_node->insn))
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{
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rtx set;
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set = single_set (dest_node->insn);
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/* TODO: Handle registers that REG_P is not true for them, i.e.
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subregs and special registers. */
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if (set && REG_P (SET_DEST (set)))
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{
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int regno = REGNO (SET_DEST (set));
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df_ref first_def;
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struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (g->bb);
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first_def = df_bb_regno_first_def_find (g->bb, regno);
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gcc_assert (first_def);
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if (bitmap_bit_p (&bb_info->gen, DF_REF_ID (first_def)))
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return;
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}
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}
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latency = dep_cost (link);
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e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
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add_edge_to_ddg (g, e);
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}
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/* The same as the above function, but it doesn't require a link parameter. */
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static void
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create_ddg_dep_no_link (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to,
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dep_type d_t, dep_data_type d_dt, int distance)
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{
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ddg_edge_ptr e;
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int l;
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enum reg_note dep_kind;
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struct _dep _dep, *dep = &_dep;
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gcc_assert (!DEBUG_INSN_P (to->insn) || d_t == ANTI_DEP);
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gcc_assert (!DEBUG_INSN_P (from->insn) || d_t == ANTI_DEP);
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if (d_t == ANTI_DEP)
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dep_kind = REG_DEP_ANTI;
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else if (d_t == OUTPUT_DEP)
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dep_kind = REG_DEP_OUTPUT;
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else
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{
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gcc_assert (d_t == TRUE_DEP);
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dep_kind = REG_DEP_TRUE;
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}
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init_dep (dep, from->insn, to->insn, dep_kind);
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l = dep_cost (dep);
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e = create_ddg_edge (from, to, d_t, d_dt, l, distance);
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if (distance > 0)
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add_backarc_to_ddg (g, e);
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else
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add_edge_to_ddg (g, e);
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}
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/* Given a downwards exposed register def LAST_DEF (which is the last
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definition of that register in the bb), add inter-loop true dependences
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to all its uses in the next iteration, an output dependence to the
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first def of the same register (possibly itself) in the next iteration
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and anti-dependences from its uses in the current iteration to the
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first definition in the next iteration. */
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static void
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add_cross_iteration_register_deps (ddg_ptr g, df_ref last_def)
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{
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int regno = DF_REF_REGNO (last_def);
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struct df_link *r_use;
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int has_use_in_bb_p = false;
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rtx_insn *def_insn = DF_REF_INSN (last_def);
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ddg_node_ptr last_def_node = get_node_of_insn (g, def_insn);
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ddg_node_ptr use_node;
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df_ref first_def = df_bb_regno_first_def_find (g->bb, regno);
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gcc_assert (last_def_node);
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gcc_assert (first_def);
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if (flag_checking && DF_REF_ID (last_def) != DF_REF_ID (first_def))
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{
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struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (g->bb);
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gcc_assert (!bitmap_bit_p (&bb_info->gen, DF_REF_ID (first_def)));
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}
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/* Create inter-loop true dependences and anti dependences. */
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for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next)
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{
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rtx_insn *use_insn = DF_REF_INSN (r_use->ref);
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if (BLOCK_FOR_INSN (use_insn) != g->bb)
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continue;
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/* ??? Do not handle uses with DF_REF_IN_NOTE notes. */
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use_node = get_node_of_insn (g, use_insn);
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gcc_assert (use_node);
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has_use_in_bb_p = true;
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if (use_node->cuid <= last_def_node->cuid)
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{
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/* Add true deps from last_def to it's uses in the next
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iteration. Any such upwards exposed use appears before
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the last_def def. */
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create_ddg_dep_no_link (g, last_def_node, use_node,
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DEBUG_INSN_P (use_insn) ? ANTI_DEP : TRUE_DEP,
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REG_DEP, 1);
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}
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else if (!DEBUG_INSN_P (use_insn))
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{
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/* Add anti deps from last_def's uses in the current iteration
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to the first def in the next iteration. We do not add ANTI
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dep when there is an intra-loop TRUE dep in the opposite
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direction, but use regmoves to fix such disregarded ANTI
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deps when broken. If the first_def reaches the USE then
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there is such a dep. */
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ddg_node_ptr first_def_node = get_node_of_insn (g,
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DF_REF_INSN (first_def));
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gcc_assert (first_def_node);
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/* Always create the edge if the use node is a branch in
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order to prevent the creation of reg-moves.
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If the address that is being auto-inc or auto-dec in LAST_DEF
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is used in USE_INSN then do not remove the edge to make sure
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reg-moves will not be created for that address. */
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if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
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|| !flag_modulo_sched_allow_regmoves
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|| JUMP_P (use_node->insn)
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|| autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn)
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|| def_has_ccmode_p (DF_REF_INSN (last_def)))
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create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
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REG_DEP, 1);
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}
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}
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/* Create an inter-loop output dependence between LAST_DEF (which is the
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last def in its block, being downwards exposed) and the first def in
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its block. Avoid creating a self output dependence. Avoid creating
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an output dependence if there is a dependence path between the two
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defs starting with a true dependence to a use which can be in the
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next iteration; followed by an anti dependence of that use to the
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first def (i.e. if there is a use between the two defs.) */
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if (!has_use_in_bb_p)
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{
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ddg_node_ptr dest_node;
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if (DF_REF_ID (last_def) == DF_REF_ID (first_def))
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return;
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dest_node = get_node_of_insn (g, DF_REF_INSN (first_def));
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gcc_assert (dest_node);
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create_ddg_dep_no_link (g, last_def_node, dest_node,
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OUTPUT_DEP, REG_DEP, 1);
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}
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}
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/* Build inter-loop dependencies, by looking at DF analysis backwards. */
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static void
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build_inter_loop_deps (ddg_ptr g)
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{
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unsigned rd_num;
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struct df_rd_bb_info *rd_bb_info;
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bitmap_iterator bi;
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rd_bb_info = DF_RD_BB_INFO (g->bb);
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/* Find inter-loop register output, true and anti deps. */
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EXECUTE_IF_SET_IN_BITMAP (&rd_bb_info->gen, 0, rd_num, bi)
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{
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df_ref rd = DF_DEFS_GET (rd_num);
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||
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add_cross_iteration_register_deps (g, rd);
|
||
}
|
||
}
|
||
|
||
|
||
/* Return true if two specified instructions have mem expr with conflict
|
||
alias sets. */
|
||
static bool
|
||
insns_may_alias_p (rtx_insn *insn1, rtx_insn *insn2)
|
||
{
|
||
subrtx_iterator::array_type array1;
|
||
subrtx_iterator::array_type array2;
|
||
FOR_EACH_SUBRTX (iter1, array1, PATTERN (insn1), NONCONST)
|
||
{
|
||
const_rtx x1 = *iter1;
|
||
if (MEM_P (x1))
|
||
FOR_EACH_SUBRTX (iter2, array2, PATTERN (insn2), NONCONST)
|
||
{
|
||
const_rtx x2 = *iter2;
|
||
if (MEM_P (x2) && may_alias_p (x2, x1))
|
||
return true;
|
||
}
|
||
}
|
||
return false;
|
||
}
|
||
|
||
/* Given two nodes, analyze their RTL insns and add intra-loop mem deps
|
||
to ddg G. */
|
||
static void
|
||
add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
|
||
{
|
||
|
||
if ((from->cuid == to->cuid)
|
||
|| !insns_may_alias_p (from->insn, to->insn))
|
||
/* Do not create edge if memory references have disjoint alias sets
|
||
or 'to' and 'from' are the same instruction. */
|
||
return;
|
||
|
||
if (mem_write_insn_p (from->insn))
|
||
{
|
||
if (mem_read_insn_p (to->insn))
|
||
create_ddg_dep_no_link (g, from, to,
|
||
DEBUG_INSN_P (to->insn)
|
||
? ANTI_DEP : TRUE_DEP, MEM_DEP, 0);
|
||
else
|
||
create_ddg_dep_no_link (g, from, to,
|
||
DEBUG_INSN_P (to->insn)
|
||
? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0);
|
||
}
|
||
else if (!mem_read_insn_p (to->insn))
|
||
create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0);
|
||
}
|
||
|
||
/* Given two nodes, analyze their RTL insns and add inter-loop mem deps
|
||
to ddg G. */
|
||
static void
|
||
add_inter_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
|
||
{
|
||
if (!insns_may_alias_p (from->insn, to->insn))
|
||
/* Do not create edge if memory references have disjoint alias sets. */
|
||
return;
|
||
|
||
if (mem_write_insn_p (from->insn))
|
||
{
|
||
if (mem_read_insn_p (to->insn))
|
||
create_ddg_dep_no_link (g, from, to,
|
||
DEBUG_INSN_P (to->insn)
|
||
? ANTI_DEP : TRUE_DEP, MEM_DEP, 1);
|
||
else if (from->cuid != to->cuid)
|
||
create_ddg_dep_no_link (g, from, to,
|
||
DEBUG_INSN_P (to->insn)
|
||
? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 1);
|
||
}
|
||
else
|
||
{
|
||
if (mem_read_insn_p (to->insn))
|
||
return;
|
||
else if (from->cuid != to->cuid)
|
||
{
|
||
create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 1);
|
||
if (DEBUG_INSN_P (from->insn) || DEBUG_INSN_P (to->insn))
|
||
create_ddg_dep_no_link (g, to, from, ANTI_DEP, MEM_DEP, 1);
|
||
else
|
||
create_ddg_dep_no_link (g, to, from, TRUE_DEP, MEM_DEP, 1);
|
||
}
|
||
}
|
||
|
||
}
|
||
|
||
/* Perform intra-block Data Dependency analysis and connect the nodes in
|
||
the DDG. We assume the loop has a single basic block. */
|
||
static void
|
||
build_intra_loop_deps (ddg_ptr g)
|
||
{
|
||
int i;
|
||
/* Hold the dependency analysis state during dependency calculations. */
|
||
struct deps_desc tmp_deps;
|
||
rtx_insn *head, *tail;
|
||
|
||
/* Build the dependence information, using the sched_analyze function. */
|
||
init_deps_global ();
|
||
init_deps (&tmp_deps, false);
|
||
|
||
/* Do the intra-block data dependence analysis for the given block. */
|
||
get_ebb_head_tail (g->bb, g->bb, &head, &tail);
|
||
sched_analyze (&tmp_deps, head, tail);
|
||
|
||
/* Build intra-loop data dependencies using the scheduler dependency
|
||
analysis. */
|
||
for (i = 0; i < g->num_nodes; i++)
|
||
{
|
||
ddg_node_ptr dest_node = &g->nodes[i];
|
||
sd_iterator_def sd_it;
|
||
dep_t dep;
|
||
|
||
if (! INSN_P (dest_node->insn))
|
||
continue;
|
||
|
||
FOR_EACH_DEP (dest_node->insn, SD_LIST_BACK, sd_it, dep)
|
||
{
|
||
rtx_insn *src_insn = DEP_PRO (dep);
|
||
ddg_node_ptr src_node;
|
||
|
||
/* Don't add dependencies on debug insns to non-debug insns
|
||
to avoid codegen differences between -g and -g0. */
|
||
if (DEBUG_INSN_P (src_insn) && !DEBUG_INSN_P (dest_node->insn))
|
||
continue;
|
||
|
||
src_node = get_node_of_insn (g, src_insn);
|
||
|
||
if (!src_node)
|
||
continue;
|
||
|
||
create_ddg_dep_from_intra_loop_link (g, src_node, dest_node, dep);
|
||
}
|
||
|
||
/* If this insn modifies memory, add an edge to all insns that access
|
||
memory. */
|
||
if (mem_access_insn_p (dest_node->insn))
|
||
{
|
||
int j;
|
||
|
||
for (j = 0; j <= i; j++)
|
||
{
|
||
ddg_node_ptr j_node = &g->nodes[j];
|
||
if (DEBUG_INSN_P (j_node->insn))
|
||
continue;
|
||
if (mem_access_insn_p (j_node->insn))
|
||
{
|
||
/* Don't bother calculating inter-loop dep if an intra-loop dep
|
||
already exists. */
|
||
if (! bitmap_bit_p (dest_node->successors, j))
|
||
add_inter_loop_mem_dep (g, dest_node, j_node);
|
||
/* If -fmodulo-sched-allow-regmoves
|
||
is set certain anti-dep edges are not created.
|
||
It might be that these anti-dep edges are on the
|
||
path from one memory instruction to another such that
|
||
removing these edges could cause a violation of the
|
||
memory dependencies. Thus we add intra edges between
|
||
every two memory instructions in this case. */
|
||
if (flag_modulo_sched_allow_regmoves
|
||
&& !bitmap_bit_p (dest_node->predecessors, j))
|
||
add_intra_loop_mem_dep (g, j_node, dest_node);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
/* Free the INSN_LISTs. */
|
||
finish_deps_global ();
|
||
free_deps (&tmp_deps);
|
||
|
||
/* Free dependencies. */
|
||
sched_free_deps (head, tail, false);
|
||
}
|
||
|
||
|
||
/* Given a basic block, create its DDG and return a pointer to a variable
|
||
of ddg type that represents it.
|
||
Initialize the ddg structure fields to the appropriate values. */
|
||
ddg_ptr
|
||
create_ddg (basic_block bb, int closing_branch_deps)
|
||
{
|
||
ddg_ptr g;
|
||
rtx_insn *insn, *first_note;
|
||
int i;
|
||
int num_nodes = 0;
|
||
|
||
g = (ddg_ptr) xcalloc (1, sizeof (struct ddg));
|
||
|
||
g->bb = bb;
|
||
g->closing_branch_deps = closing_branch_deps;
|
||
|
||
/* Count the number of insns in the BB. */
|
||
for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
|
||
insn = NEXT_INSN (insn))
|
||
{
|
||
if (! INSN_P (insn) || GET_CODE (PATTERN (insn)) == USE)
|
||
continue;
|
||
|
||
if (DEBUG_INSN_P (insn))
|
||
g->num_debug++;
|
||
else
|
||
{
|
||
if (mem_read_insn_p (insn))
|
||
g->num_loads++;
|
||
if (mem_write_insn_p (insn))
|
||
g->num_stores++;
|
||
}
|
||
num_nodes++;
|
||
}
|
||
|
||
/* There is nothing to do for this BB. */
|
||
if ((num_nodes - g->num_debug) <= 1)
|
||
{
|
||
free (g);
|
||
return NULL;
|
||
}
|
||
|
||
/* Allocate the nodes array, and initialize the nodes. */
|
||
g->num_nodes = num_nodes;
|
||
g->nodes = (ddg_node_ptr) xcalloc (num_nodes, sizeof (struct ddg_node));
|
||
g->closing_branch = NULL;
|
||
i = 0;
|
||
first_note = NULL;
|
||
for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
|
||
insn = NEXT_INSN (insn))
|
||
{
|
||
if (! INSN_P (insn))
|
||
{
|
||
if (! first_note && NOTE_P (insn)
|
||
&& NOTE_KIND (insn) != NOTE_INSN_BASIC_BLOCK)
|
||
first_note = insn;
|
||
continue;
|
||
}
|
||
if (JUMP_P (insn))
|
||
{
|
||
gcc_assert (!g->closing_branch);
|
||
g->closing_branch = &g->nodes[i];
|
||
}
|
||
else if (GET_CODE (PATTERN (insn)) == USE)
|
||
{
|
||
if (! first_note)
|
||
first_note = insn;
|
||
continue;
|
||
}
|
||
|
||
g->nodes[i].cuid = i;
|
||
g->nodes[i].successors = sbitmap_alloc (num_nodes);
|
||
bitmap_clear (g->nodes[i].successors);
|
||
g->nodes[i].predecessors = sbitmap_alloc (num_nodes);
|
||
bitmap_clear (g->nodes[i].predecessors);
|
||
g->nodes[i].first_note = (first_note ? first_note : insn);
|
||
g->nodes[i++].insn = insn;
|
||
first_note = NULL;
|
||
}
|
||
|
||
/* We must have found a branch in DDG. */
|
||
gcc_assert (g->closing_branch);
|
||
|
||
|
||
/* Build the data dependency graph. */
|
||
build_intra_loop_deps (g);
|
||
build_inter_loop_deps (g);
|
||
return g;
|
||
}
|
||
|
||
/* Free all the memory allocated for the DDG. */
|
||
void
|
||
free_ddg (ddg_ptr g)
|
||
{
|
||
int i;
|
||
|
||
if (!g)
|
||
return;
|
||
|
||
for (i = 0; i < g->num_nodes; i++)
|
||
{
|
||
ddg_edge_ptr e = g->nodes[i].out;
|
||
|
||
while (e)
|
||
{
|
||
ddg_edge_ptr next = e->next_out;
|
||
|
||
free (e);
|
||
e = next;
|
||
}
|
||
sbitmap_free (g->nodes[i].successors);
|
||
sbitmap_free (g->nodes[i].predecessors);
|
||
}
|
||
if (g->num_backarcs > 0)
|
||
free (g->backarcs);
|
||
free (g->nodes);
|
||
free (g);
|
||
}
|
||
|
||
void
|
||
print_ddg_edge (FILE *file, ddg_edge_ptr e)
|
||
{
|
||
char dep_c;
|
||
|
||
switch (e->type)
|
||
{
|
||
case OUTPUT_DEP :
|
||
dep_c = 'O';
|
||
break;
|
||
case ANTI_DEP :
|
||
dep_c = 'A';
|
||
break;
|
||
default:
|
||
dep_c = 'T';
|
||
}
|
||
|
||
fprintf (file, " [%d -(%c,%d,%d)-> %d] ", INSN_UID (e->src->insn),
|
||
dep_c, e->latency, e->distance, INSN_UID (e->dest->insn));
|
||
}
|
||
|
||
/* Print the DDG nodes with there in/out edges to the dump file. */
|
||
void
|
||
print_ddg (FILE *file, ddg_ptr g)
|
||
{
|
||
int i;
|
||
|
||
for (i = 0; i < g->num_nodes; i++)
|
||
{
|
||
ddg_edge_ptr e;
|
||
|
||
fprintf (file, "Node num: %d\n", g->nodes[i].cuid);
|
||
print_rtl_single (file, g->nodes[i].insn);
|
||
fprintf (file, "OUT ARCS: ");
|
||
for (e = g->nodes[i].out; e; e = e->next_out)
|
||
print_ddg_edge (file, e);
|
||
|
||
fprintf (file, "\nIN ARCS: ");
|
||
for (e = g->nodes[i].in; e; e = e->next_in)
|
||
print_ddg_edge (file, e);
|
||
|
||
fprintf (file, "\n");
|
||
}
|
||
}
|
||
|
||
/* Print the given DDG in VCG format. */
|
||
DEBUG_FUNCTION void
|
||
vcg_print_ddg (FILE *file, ddg_ptr g)
|
||
{
|
||
int src_cuid;
|
||
|
||
fprintf (file, "graph: {\n");
|
||
for (src_cuid = 0; src_cuid < g->num_nodes; src_cuid++)
|
||
{
|
||
ddg_edge_ptr e;
|
||
int src_uid = INSN_UID (g->nodes[src_cuid].insn);
|
||
|
||
fprintf (file, "node: {title: \"%d_%d\" info1: \"", src_cuid, src_uid);
|
||
print_rtl_single (file, g->nodes[src_cuid].insn);
|
||
fprintf (file, "\"}\n");
|
||
for (e = g->nodes[src_cuid].out; e; e = e->next_out)
|
||
{
|
||
int dst_uid = INSN_UID (e->dest->insn);
|
||
int dst_cuid = e->dest->cuid;
|
||
|
||
/* Give the backarcs a different color. */
|
||
if (e->distance > 0)
|
||
fprintf (file, "backedge: {color: red ");
|
||
else
|
||
fprintf (file, "edge: { ");
|
||
|
||
fprintf (file, "sourcename: \"%d_%d\" ", src_cuid, src_uid);
|
||
fprintf (file, "targetname: \"%d_%d\" ", dst_cuid, dst_uid);
|
||
fprintf (file, "label: \"%d_%d\"}\n", e->latency, e->distance);
|
||
}
|
||
}
|
||
fprintf (file, "}\n");
|
||
}
|
||
|
||
/* Dump the sccs in SCCS. */
|
||
void
|
||
print_sccs (FILE *file, ddg_all_sccs_ptr sccs, ddg_ptr g)
|
||
{
|
||
unsigned int u = 0;
|
||
sbitmap_iterator sbi;
|
||
int i;
|
||
|
||
if (!file)
|
||
return;
|
||
|
||
fprintf (file, "\n;; Number of SCC nodes - %d\n", sccs->num_sccs);
|
||
for (i = 0; i < sccs->num_sccs; i++)
|
||
{
|
||
fprintf (file, "SCC number: %d\n", i);
|
||
EXECUTE_IF_SET_IN_BITMAP (sccs->sccs[i]->nodes, 0, u, sbi)
|
||
{
|
||
fprintf (file, "insn num %d\n", u);
|
||
print_rtl_single (file, g->nodes[u].insn);
|
||
}
|
||
}
|
||
fprintf (file, "\n");
|
||
}
|
||
|
||
/* Create an edge and initialize it with given values. */
|
||
static ddg_edge_ptr
|
||
create_ddg_edge (ddg_node_ptr src, ddg_node_ptr dest,
|
||
dep_type t, dep_data_type dt, int l, int d)
|
||
{
|
||
ddg_edge_ptr e = (ddg_edge_ptr) xmalloc (sizeof (struct ddg_edge));
|
||
|
||
e->src = src;
|
||
e->dest = dest;
|
||
e->type = t;
|
||
e->data_type = dt;
|
||
e->latency = l;
|
||
e->distance = d;
|
||
e->next_in = e->next_out = NULL;
|
||
e->aux.info = 0;
|
||
return e;
|
||
}
|
||
|
||
/* Add the given edge to the in/out linked lists of the DDG nodes. */
|
||
static void
|
||
add_edge_to_ddg (ddg_ptr g ATTRIBUTE_UNUSED, ddg_edge_ptr e)
|
||
{
|
||
ddg_node_ptr src = e->src;
|
||
ddg_node_ptr dest = e->dest;
|
||
|
||
/* Should have allocated the sbitmaps. */
|
||
gcc_assert (src->successors && dest->predecessors);
|
||
|
||
bitmap_set_bit (src->successors, dest->cuid);
|
||
bitmap_set_bit (dest->predecessors, src->cuid);
|
||
e->next_in = dest->in;
|
||
dest->in = e;
|
||
e->next_out = src->out;
|
||
src->out = e;
|
||
}
|
||
|
||
|
||
|
||
/* Algorithm for computing the recurrence_length of an scc. We assume at
|
||
for now that cycles in the data dependence graph contain a single backarc.
|
||
This simplifies the algorithm, and can be generalized later. */
|
||
static void
|
||
set_recurrence_length (ddg_scc_ptr scc, ddg_ptr g)
|
||
{
|
||
int j;
|
||
int result = -1;
|
||
|
||
for (j = 0; j < scc->num_backarcs; j++)
|
||
{
|
||
ddg_edge_ptr backarc = scc->backarcs[j];
|
||
int length;
|
||
int distance = backarc->distance;
|
||
ddg_node_ptr src = backarc->dest;
|
||
ddg_node_ptr dest = backarc->src;
|
||
|
||
length = longest_simple_path (g, src->cuid, dest->cuid, scc->nodes);
|
||
if (length < 0 )
|
||
{
|
||
/* fprintf (stderr, "Backarc not on simple cycle in SCC.\n"); */
|
||
continue;
|
||
}
|
||
length += backarc->latency;
|
||
result = MAX (result, (length / distance));
|
||
}
|
||
scc->recurrence_length = result;
|
||
}
|
||
|
||
/* Create a new SCC given the set of its nodes. Compute its recurrence_length
|
||
and mark edges that belong to this scc as IN_SCC. */
|
||
static ddg_scc_ptr
|
||
create_scc (ddg_ptr g, sbitmap nodes)
|
||
{
|
||
ddg_scc_ptr scc;
|
||
unsigned int u = 0;
|
||
sbitmap_iterator sbi;
|
||
|
||
scc = (ddg_scc_ptr) xmalloc (sizeof (struct ddg_scc));
|
||
scc->backarcs = NULL;
|
||
scc->num_backarcs = 0;
|
||
scc->nodes = sbitmap_alloc (g->num_nodes);
|
||
bitmap_copy (scc->nodes, nodes);
|
||
|
||
/* Mark the backarcs that belong to this SCC. */
|
||
EXECUTE_IF_SET_IN_BITMAP (nodes, 0, u, sbi)
|
||
{
|
||
ddg_edge_ptr e;
|
||
ddg_node_ptr n = &g->nodes[u];
|
||
|
||
for (e = n->out; e; e = e->next_out)
|
||
if (bitmap_bit_p (nodes, e->dest->cuid))
|
||
{
|
||
e->aux.count = IN_SCC;
|
||
if (e->distance > 0)
|
||
add_backarc_to_scc (scc, e);
|
||
}
|
||
}
|
||
|
||
set_recurrence_length (scc, g);
|
||
return scc;
|
||
}
|
||
|
||
/* Cleans the memory allocation of a given SCC. */
|
||
static void
|
||
free_scc (ddg_scc_ptr scc)
|
||
{
|
||
if (!scc)
|
||
return;
|
||
|
||
sbitmap_free (scc->nodes);
|
||
if (scc->num_backarcs > 0)
|
||
free (scc->backarcs);
|
||
free (scc);
|
||
}
|
||
|
||
|
||
/* Add a given edge known to be a backarc to the given DDG. */
|
||
static void
|
||
add_backarc_to_ddg (ddg_ptr g, ddg_edge_ptr e)
|
||
{
|
||
int size = (g->num_backarcs + 1) * sizeof (ddg_edge_ptr);
|
||
|
||
add_edge_to_ddg (g, e);
|
||
g->backarcs = (ddg_edge_ptr *) xrealloc (g->backarcs, size);
|
||
g->backarcs[g->num_backarcs++] = e;
|
||
}
|
||
|
||
/* Add backarc to an SCC. */
|
||
static void
|
||
add_backarc_to_scc (ddg_scc_ptr scc, ddg_edge_ptr e)
|
||
{
|
||
int size = (scc->num_backarcs + 1) * sizeof (ddg_edge_ptr);
|
||
|
||
scc->backarcs = (ddg_edge_ptr *) xrealloc (scc->backarcs, size);
|
||
scc->backarcs[scc->num_backarcs++] = e;
|
||
}
|
||
|
||
/* Add the given SCC to the DDG. */
|
||
static void
|
||
add_scc_to_ddg (ddg_all_sccs_ptr g, ddg_scc_ptr scc)
|
||
{
|
||
int size = (g->num_sccs + 1) * sizeof (ddg_scc_ptr);
|
||
|
||
g->sccs = (ddg_scc_ptr *) xrealloc (g->sccs, size);
|
||
g->sccs[g->num_sccs++] = scc;
|
||
}
|
||
|
||
/* Given the instruction INSN return the node that represents it. */
|
||
ddg_node_ptr
|
||
get_node_of_insn (ddg_ptr g, rtx_insn *insn)
|
||
{
|
||
int i;
|
||
|
||
for (i = 0; i < g->num_nodes; i++)
|
||
if (insn == g->nodes[i].insn)
|
||
return &g->nodes[i];
|
||
return NULL;
|
||
}
|
||
|
||
/* Given a set OPS of nodes in the DDG, find the set of their successors
|
||
which are not in OPS, and set their bits in SUCC. Bits corresponding to
|
||
OPS are cleared from SUCC. Leaves the other bits in SUCC unchanged. */
|
||
void
|
||
find_successors (sbitmap succ, ddg_ptr g, sbitmap ops)
|
||
{
|
||
unsigned int i = 0;
|
||
sbitmap_iterator sbi;
|
||
|
||
EXECUTE_IF_SET_IN_BITMAP (ops, 0, i, sbi)
|
||
{
|
||
const sbitmap node_succ = NODE_SUCCESSORS (&g->nodes[i]);
|
||
bitmap_ior (succ, succ, node_succ);
|
||
};
|
||
|
||
/* We want those that are not in ops. */
|
||
bitmap_and_compl (succ, succ, ops);
|
||
}
|
||
|
||
/* Given a set OPS of nodes in the DDG, find the set of their predecessors
|
||
which are not in OPS, and set their bits in PREDS. Bits corresponding to
|
||
OPS are cleared from PREDS. Leaves the other bits in PREDS unchanged. */
|
||
void
|
||
find_predecessors (sbitmap preds, ddg_ptr g, sbitmap ops)
|
||
{
|
||
unsigned int i = 0;
|
||
sbitmap_iterator sbi;
|
||
|
||
EXECUTE_IF_SET_IN_BITMAP (ops, 0, i, sbi)
|
||
{
|
||
const sbitmap node_preds = NODE_PREDECESSORS (&g->nodes[i]);
|
||
bitmap_ior (preds, preds, node_preds);
|
||
};
|
||
|
||
/* We want those that are not in ops. */
|
||
bitmap_and_compl (preds, preds, ops);
|
||
}
|
||
|
||
|
||
/* Compare function to be passed to qsort to order the backarcs in descending
|
||
recMII order. */
|
||
static int
|
||
compare_sccs (const void *s1, const void *s2)
|
||
{
|
||
const int rec_l1 = (*(const ddg_scc_ptr *)s1)->recurrence_length;
|
||
const int rec_l2 = (*(const ddg_scc_ptr *)s2)->recurrence_length;
|
||
return ((rec_l2 > rec_l1) - (rec_l2 < rec_l1));
|
||
|
||
}
|
||
|
||
/* Order the backarcs in descending recMII order using compare_sccs. */
|
||
static void
|
||
order_sccs (ddg_all_sccs_ptr g)
|
||
{
|
||
qsort (g->sccs, g->num_sccs, sizeof (ddg_scc_ptr),
|
||
(int (*) (const void *, const void *)) compare_sccs);
|
||
}
|
||
|
||
/* Check that every node in SCCS belongs to exactly one strongly connected
|
||
component and that no element of SCCS is empty. */
|
||
static void
|
||
check_sccs (ddg_all_sccs_ptr sccs, int num_nodes)
|
||
{
|
||
int i = 0;
|
||
auto_sbitmap tmp (num_nodes);
|
||
|
||
bitmap_clear (tmp);
|
||
for (i = 0; i < sccs->num_sccs; i++)
|
||
{
|
||
gcc_assert (!bitmap_empty_p (sccs->sccs[i]->nodes));
|
||
/* Verify that every node in sccs is in exactly one strongly
|
||
connected component. */
|
||
gcc_assert (!bitmap_intersect_p (tmp, sccs->sccs[i]->nodes));
|
||
bitmap_ior (tmp, tmp, sccs->sccs[i]->nodes);
|
||
}
|
||
}
|
||
|
||
/* Perform the Strongly Connected Components decomposing algorithm on the
|
||
DDG and return DDG_ALL_SCCS structure that contains them. */
|
||
ddg_all_sccs_ptr
|
||
create_ddg_all_sccs (ddg_ptr g)
|
||
{
|
||
int i;
|
||
int num_nodes = g->num_nodes;
|
||
auto_sbitmap from (num_nodes);
|
||
auto_sbitmap to (num_nodes);
|
||
auto_sbitmap scc_nodes (num_nodes);
|
||
ddg_all_sccs_ptr sccs = (ddg_all_sccs_ptr)
|
||
xmalloc (sizeof (struct ddg_all_sccs));
|
||
|
||
sccs->ddg = g;
|
||
sccs->sccs = NULL;
|
||
sccs->num_sccs = 0;
|
||
|
||
for (i = 0; i < g->num_backarcs; i++)
|
||
{
|
||
ddg_scc_ptr scc;
|
||
ddg_edge_ptr backarc = g->backarcs[i];
|
||
ddg_node_ptr src = backarc->src;
|
||
ddg_node_ptr dest = backarc->dest;
|
||
|
||
/* If the backarc already belongs to an SCC, continue. */
|
||
if (backarc->aux.count == IN_SCC)
|
||
continue;
|
||
|
||
bitmap_clear (scc_nodes);
|
||
bitmap_clear (from);
|
||
bitmap_clear (to);
|
||
bitmap_set_bit (from, dest->cuid);
|
||
bitmap_set_bit (to, src->cuid);
|
||
|
||
if (find_nodes_on_paths (scc_nodes, g, from, to))
|
||
{
|
||
scc = create_scc (g, scc_nodes);
|
||
add_scc_to_ddg (sccs, scc);
|
||
}
|
||
}
|
||
order_sccs (sccs);
|
||
|
||
if (flag_checking)
|
||
check_sccs (sccs, num_nodes);
|
||
|
||
return sccs;
|
||
}
|
||
|
||
/* Frees the memory allocated for all SCCs of the DDG, but keeps the DDG. */
|
||
void
|
||
free_ddg_all_sccs (ddg_all_sccs_ptr all_sccs)
|
||
{
|
||
int i;
|
||
|
||
if (!all_sccs)
|
||
return;
|
||
|
||
for (i = 0; i < all_sccs->num_sccs; i++)
|
||
free_scc (all_sccs->sccs[i]);
|
||
|
||
free (all_sccs->sccs);
|
||
free (all_sccs);
|
||
}
|
||
|
||
|
||
/* Given FROM - a bitmap of source nodes - and TO - a bitmap of destination
|
||
nodes - find all nodes that lie on paths from FROM to TO (not excluding
|
||
nodes from FROM and TO). Return nonzero if nodes exist. */
|
||
int
|
||
find_nodes_on_paths (sbitmap result, ddg_ptr g, sbitmap from, sbitmap to)
|
||
{
|
||
int change;
|
||
unsigned int u = 0;
|
||
int num_nodes = g->num_nodes;
|
||
sbitmap_iterator sbi;
|
||
|
||
auto_sbitmap workset (num_nodes);
|
||
auto_sbitmap reachable_from (num_nodes);
|
||
auto_sbitmap reach_to (num_nodes);
|
||
auto_sbitmap tmp (num_nodes);
|
||
|
||
bitmap_copy (reachable_from, from);
|
||
bitmap_copy (tmp, from);
|
||
|
||
change = 1;
|
||
while (change)
|
||
{
|
||
change = 0;
|
||
bitmap_copy (workset, tmp);
|
||
bitmap_clear (tmp);
|
||
EXECUTE_IF_SET_IN_BITMAP (workset, 0, u, sbi)
|
||
{
|
||
ddg_edge_ptr e;
|
||
ddg_node_ptr u_node = &g->nodes[u];
|
||
|
||
for (e = u_node->out; e != (ddg_edge_ptr) 0; e = e->next_out)
|
||
{
|
||
ddg_node_ptr v_node = e->dest;
|
||
int v = v_node->cuid;
|
||
|
||
if (!bitmap_bit_p (reachable_from, v))
|
||
{
|
||
bitmap_set_bit (reachable_from, v);
|
||
bitmap_set_bit (tmp, v);
|
||
change = 1;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
bitmap_copy (reach_to, to);
|
||
bitmap_copy (tmp, to);
|
||
|
||
change = 1;
|
||
while (change)
|
||
{
|
||
change = 0;
|
||
bitmap_copy (workset, tmp);
|
||
bitmap_clear (tmp);
|
||
EXECUTE_IF_SET_IN_BITMAP (workset, 0, u, sbi)
|
||
{
|
||
ddg_edge_ptr e;
|
||
ddg_node_ptr u_node = &g->nodes[u];
|
||
|
||
for (e = u_node->in; e != (ddg_edge_ptr) 0; e = e->next_in)
|
||
{
|
||
ddg_node_ptr v_node = e->src;
|
||
int v = v_node->cuid;
|
||
|
||
if (!bitmap_bit_p (reach_to, v))
|
||
{
|
||
bitmap_set_bit (reach_to, v);
|
||
bitmap_set_bit (tmp, v);
|
||
change = 1;
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
return bitmap_and (result, reachable_from, reach_to);
|
||
}
|
||
|
||
|
||
/* Updates the counts of U_NODE's successors (that belong to NODES) to be
|
||
at-least as large as the count of U_NODE plus the latency between them.
|
||
Sets a bit in TMP for each successor whose count was changed (increased).
|
||
Returns nonzero if any count was changed. */
|
||
static int
|
||
update_dist_to_successors (ddg_node_ptr u_node, sbitmap nodes, sbitmap tmp)
|
||
{
|
||
ddg_edge_ptr e;
|
||
int result = 0;
|
||
|
||
for (e = u_node->out; e; e = e->next_out)
|
||
{
|
||
ddg_node_ptr v_node = e->dest;
|
||
int v = v_node->cuid;
|
||
|
||
if (bitmap_bit_p (nodes, v)
|
||
&& (e->distance == 0)
|
||
&& (v_node->aux.count < u_node->aux.count + e->latency))
|
||
{
|
||
v_node->aux.count = u_node->aux.count + e->latency;
|
||
bitmap_set_bit (tmp, v);
|
||
result = 1;
|
||
}
|
||
}
|
||
return result;
|
||
}
|
||
|
||
|
||
/* Find the length of a longest path from SRC to DEST in G,
|
||
going only through NODES, and disregarding backarcs. */
|
||
int
|
||
longest_simple_path (struct ddg * g, int src, int dest, sbitmap nodes)
|
||
{
|
||
int i;
|
||
unsigned int u = 0;
|
||
int change = 1;
|
||
int num_nodes = g->num_nodes;
|
||
auto_sbitmap workset (num_nodes);
|
||
auto_sbitmap tmp (num_nodes);
|
||
|
||
|
||
/* Data will hold the distance of the longest path found so far from
|
||
src to each node. Initialize to -1 = less than minimum. */
|
||
for (i = 0; i < g->num_nodes; i++)
|
||
g->nodes[i].aux.count = -1;
|
||
g->nodes[src].aux.count = 0;
|
||
|
||
bitmap_clear (tmp);
|
||
bitmap_set_bit (tmp, src);
|
||
|
||
while (change)
|
||
{
|
||
sbitmap_iterator sbi;
|
||
|
||
change = 0;
|
||
bitmap_copy (workset, tmp);
|
||
bitmap_clear (tmp);
|
||
EXECUTE_IF_SET_IN_BITMAP (workset, 0, u, sbi)
|
||
{
|
||
ddg_node_ptr u_node = &g->nodes[u];
|
||
|
||
change |= update_dist_to_successors (u_node, nodes, tmp);
|
||
}
|
||
}
|
||
return g->nodes[dest].aux.count;
|
||
}
|
||
|
||
#endif /* INSN_SCHEDULING */
|