832c1192eb
Windows ABI (MinGW) is different than Linux ABI when bitfileds are involved. The following patch adds __attribute__ ((gcc_struct)) to struct fenv in order to match the layout of x87 state image in memory. 2020-06-01 Uroš Bizjak <ubizjak@gmail.com> libatomic/ChangeLog: * config/x86/fenv.c (struct fenv): Add __attribute__ ((gcc_struct)). libgcc/ChangeLog: * config/i386/sfp-exceptions.c (struct fenv): Add __attribute__ ((gcc_struct)). libgfortran/ChangeLog: PR libfortran/95418 * config/fpu-387.h (struct fenv): Add __attribute__ ((gcc_struct)).
498 lines
12 KiB
C
498 lines
12 KiB
C
/* FPU-related code for x86 and x86_64 processors.
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Copyright (C) 2005-2020 Free Software Foundation, Inc.
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Contributed by Francois-Xavier Coudert <coudert@clipper.ens.fr>
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This file is part of the GNU Fortran 95 runtime library (libgfortran).
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Libgfortran is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public
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License as published by the Free Software Foundation; either
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version 3 of the License, or (at your option) any later version.
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Libgfortran is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef __SSE_MATH__
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#include "cpuid.h"
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#endif
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static int
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has_sse (void)
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{
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#ifndef __SSE_MATH__
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unsigned int eax, ebx, ecx, edx;
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if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
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return 0;
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return edx & bit_SSE;
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#else
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return 1;
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#endif
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}
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/* i387 exceptions -- see linux <fpu_control.h> header file for details. */
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#define _FPU_MASK_IM 0x01
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#define _FPU_MASK_DM 0x02
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#define _FPU_MASK_ZM 0x04
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#define _FPU_MASK_OM 0x08
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#define _FPU_MASK_UM 0x10
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#define _FPU_MASK_PM 0x20
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#define _FPU_MASK_ALL 0x3f
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#define _FPU_EX_ALL 0x3f
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/* i387 rounding modes. */
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#define _FPU_RC_NEAREST 0x0
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#define _FPU_RC_DOWN 0x1
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#define _FPU_RC_UP 0x2
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#define _FPU_RC_ZERO 0x3
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#define _FPU_RC_MASK 0x3
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/* Enable flush to zero mode. */
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#define MXCSR_FTZ (1 << 15)
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/* This structure corresponds to the layout of the block
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written by FSTENV. */
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struct fenv
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{
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unsigned short int __control_word;
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unsigned short int __unused1;
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unsigned short int __status_word;
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unsigned short int __unused2;
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unsigned short int __tags;
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unsigned short int __unused3;
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unsigned int __eip;
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unsigned short int __cs_selector;
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unsigned int __opcode:11;
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unsigned int __unused4:5;
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unsigned int __data_offset;
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unsigned short int __data_selector;
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unsigned short int __unused5;
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unsigned int __mxcsr;
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} __attribute__ ((gcc_struct));
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/* Check we can actually store the FPU state in the allocated size. */
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_Static_assert (sizeof(struct fenv) <= (size_t) GFC_FPE_STATE_BUFFER_SIZE,
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"GFC_FPE_STATE_BUFFER_SIZE is too small");
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#ifdef __SSE_MATH__
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# define __math_force_eval_div(x, y) \
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do { \
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__asm__ ("" : "+x" (x)); __asm__ __volatile__ ("" : : "x" (x / y)); \
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} while (0)
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#else
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# define __math_force_eval_div(x, y) \
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do { \
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__asm__ ("" : "+t" (x)); __asm__ __volatile__ ("" : : "f" (x / y)); \
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} while (0)
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#endif
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/* Raise the supported floating-point exceptions from EXCEPTS. Other
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bits in EXCEPTS are ignored. Code originally borrowed from
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libatomic/config/x86/fenv.c. */
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static void
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local_feraiseexcept (int excepts)
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{
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struct fenv temp;
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if (excepts & _FPU_MASK_IM)
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{
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float f = 0.0f;
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__math_force_eval_div (f, f);
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}
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if (excepts & _FPU_MASK_DM)
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{
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__asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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temp.__status_word |= _FPU_MASK_DM;
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__asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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__asm__ __volatile__ ("fwait");
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}
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if (excepts & _FPU_MASK_ZM)
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{
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float f = 1.0f, g = 0.0f;
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__math_force_eval_div (f, g);
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}
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if (excepts & _FPU_MASK_OM)
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{
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__asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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temp.__status_word |= _FPU_MASK_OM;
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__asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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__asm__ __volatile__ ("fwait");
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}
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if (excepts & _FPU_MASK_UM)
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{
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__asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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temp.__status_word |= _FPU_MASK_UM;
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__asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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__asm__ __volatile__ ("fwait");
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}
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if (excepts & _FPU_MASK_PM)
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{
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float f = 1.0f, g = 3.0f;
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__math_force_eval_div (f, g);
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}
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}
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void
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set_fpu_trap_exceptions (int trap, int notrap)
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{
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int exc_set = 0, exc_clr = 0;
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unsigned short cw;
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if (trap & GFC_FPE_INVALID) exc_set |= _FPU_MASK_IM;
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if (trap & GFC_FPE_DENORMAL) exc_set |= _FPU_MASK_DM;
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if (trap & GFC_FPE_ZERO) exc_set |= _FPU_MASK_ZM;
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if (trap & GFC_FPE_OVERFLOW) exc_set |= _FPU_MASK_OM;
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if (trap & GFC_FPE_UNDERFLOW) exc_set |= _FPU_MASK_UM;
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if (trap & GFC_FPE_INEXACT) exc_set |= _FPU_MASK_PM;
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if (notrap & GFC_FPE_INVALID) exc_clr |= _FPU_MASK_IM;
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if (notrap & GFC_FPE_DENORMAL) exc_clr |= _FPU_MASK_DM;
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if (notrap & GFC_FPE_ZERO) exc_clr |= _FPU_MASK_ZM;
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if (notrap & GFC_FPE_OVERFLOW) exc_clr |= _FPU_MASK_OM;
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if (notrap & GFC_FPE_UNDERFLOW) exc_clr |= _FPU_MASK_UM;
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if (notrap & GFC_FPE_INEXACT) exc_clr |= _FPU_MASK_PM;
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__asm__ __volatile__ ("fstcw\t%0" : "=m" (cw));
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cw |= exc_clr;
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cw &= ~exc_set;
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__asm__ __volatile__ ("fnclex\n\tfldcw\t%0" : : "m" (cw));
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if (has_sse())
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{
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unsigned int cw_sse;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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/* The SSE exception masks are shifted by 7 bits. */
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cw_sse |= (exc_clr << 7);
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cw_sse &= ~(exc_set << 7);
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/* Clear stalled exception flags. */
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cw_sse &= ~_FPU_EX_ALL;
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__asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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}
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}
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void
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set_fpu (void)
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{
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set_fpu_trap_exceptions (options.fpe, 0);
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}
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int
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get_fpu_trap_exceptions (void)
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{
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unsigned short cw;
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int mask;
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int res = 0;
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__asm__ __volatile__ ("fstcw\t%0" : "=m" (cw));
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mask = cw;
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if (has_sse())
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{
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unsigned int cw_sse;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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/* The SSE exception masks are shifted by 7 bits. */
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mask |= (cw_sse >> 7);
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}
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mask = ~mask & _FPU_MASK_ALL;
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if (mask & _FPU_MASK_IM) res |= GFC_FPE_INVALID;
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if (mask & _FPU_MASK_DM) res |= GFC_FPE_DENORMAL;
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if (mask & _FPU_MASK_ZM) res |= GFC_FPE_ZERO;
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if (mask & _FPU_MASK_OM) res |= GFC_FPE_OVERFLOW;
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if (mask & _FPU_MASK_UM) res |= GFC_FPE_UNDERFLOW;
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if (mask & _FPU_MASK_PM) res |= GFC_FPE_INEXACT;
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return res;
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}
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int
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support_fpu_trap (int flag __attribute__((unused)))
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{
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return 1;
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}
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int
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get_fpu_except_flags (void)
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{
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unsigned short cw;
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int excepts;
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int res = 0;
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__asm__ __volatile__ ("fnstsw\t%0" : "=am" (cw));
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excepts = cw;
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if (has_sse())
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{
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unsigned int cw_sse;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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excepts |= cw_sse;
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}
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excepts &= _FPU_EX_ALL;
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if (excepts & _FPU_MASK_IM) res |= GFC_FPE_INVALID;
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if (excepts & _FPU_MASK_DM) res |= GFC_FPE_DENORMAL;
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if (excepts & _FPU_MASK_ZM) res |= GFC_FPE_ZERO;
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if (excepts & _FPU_MASK_OM) res |= GFC_FPE_OVERFLOW;
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if (excepts & _FPU_MASK_UM) res |= GFC_FPE_UNDERFLOW;
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if (excepts & _FPU_MASK_PM) res |= GFC_FPE_INEXACT;
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return res;
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}
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void
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set_fpu_except_flags (int set, int clear)
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{
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struct fenv temp;
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int exc_set = 0, exc_clr = 0;
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/* Translate from GFC_PE_* values to _FPU_MASK_* values. */
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if (set & GFC_FPE_INVALID)
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exc_set |= _FPU_MASK_IM;
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if (clear & GFC_FPE_INVALID)
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exc_clr |= _FPU_MASK_IM;
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if (set & GFC_FPE_DENORMAL)
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exc_set |= _FPU_MASK_DM;
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if (clear & GFC_FPE_DENORMAL)
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exc_clr |= _FPU_MASK_DM;
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if (set & GFC_FPE_ZERO)
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exc_set |= _FPU_MASK_ZM;
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if (clear & GFC_FPE_ZERO)
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exc_clr |= _FPU_MASK_ZM;
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if (set & GFC_FPE_OVERFLOW)
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exc_set |= _FPU_MASK_OM;
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if (clear & GFC_FPE_OVERFLOW)
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exc_clr |= _FPU_MASK_OM;
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if (set & GFC_FPE_UNDERFLOW)
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exc_set |= _FPU_MASK_UM;
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if (clear & GFC_FPE_UNDERFLOW)
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exc_clr |= _FPU_MASK_UM;
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if (set & GFC_FPE_INEXACT)
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exc_set |= _FPU_MASK_PM;
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if (clear & GFC_FPE_INEXACT)
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exc_clr |= _FPU_MASK_PM;
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/* Change the flags. This is tricky on 387 (unlike SSE), because we have
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FNSTSW but no FLDSW instruction. */
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__asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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temp.__status_word &= ~exc_clr;
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__asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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/* Change the flags on SSE. */
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if (has_sse())
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{
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unsigned int cw_sse;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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cw_sse &= ~exc_clr;
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__asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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}
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local_feraiseexcept (exc_set);
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}
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int
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support_fpu_flag (int flag __attribute__((unused)))
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{
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return 1;
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}
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void
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set_fpu_rounding_mode (int round)
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{
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int round_mode;
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unsigned short cw;
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switch (round)
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{
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case GFC_FPE_TONEAREST:
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round_mode = _FPU_RC_NEAREST;
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break;
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case GFC_FPE_UPWARD:
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round_mode = _FPU_RC_UP;
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break;
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case GFC_FPE_DOWNWARD:
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round_mode = _FPU_RC_DOWN;
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break;
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case GFC_FPE_TOWARDZERO:
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round_mode = _FPU_RC_ZERO;
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break;
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default:
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return; /* Should be unreachable. */
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}
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__asm__ __volatile__ ("fnstcw\t%0" : "=m" (cw));
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/* The x87 round control bits are shifted by 10 bits. */
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cw &= ~(_FPU_RC_MASK << 10);
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cw |= round_mode << 10;
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__asm__ __volatile__ ("fldcw\t%0" : : "m" (cw));
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if (has_sse())
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{
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unsigned int cw_sse;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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/* The SSE round control bits are shifted by 13 bits. */
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cw_sse &= ~(_FPU_RC_MASK << 13);
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cw_sse |= round_mode << 13;
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__asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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}
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}
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int
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get_fpu_rounding_mode (void)
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{
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int round_mode;
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#ifdef __SSE_MATH__
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unsigned int cw;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw));
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/* The SSE round control bits are shifted by 13 bits. */
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round_mode = cw >> 13;
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#else
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unsigned short cw;
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__asm__ __volatile__ ("fnstcw\t%0" : "=m" (cw));
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/* The x87 round control bits are shifted by 10 bits. */
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round_mode = cw >> 10;
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#endif
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round_mode &= _FPU_RC_MASK;
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switch (round_mode)
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{
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case _FPU_RC_NEAREST:
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return GFC_FPE_TONEAREST;
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case _FPU_RC_UP:
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return GFC_FPE_UPWARD;
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case _FPU_RC_DOWN:
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return GFC_FPE_DOWNWARD;
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case _FPU_RC_ZERO:
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return GFC_FPE_TOWARDZERO;
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default:
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return 0; /* Should be unreachable. */
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}
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}
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int
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support_fpu_rounding_mode (int mode __attribute__((unused)))
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{
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return 1;
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}
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void
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get_fpu_state (void *state)
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{
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struct fenv *envp = state;
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__asm__ __volatile__ ("fnstenv\t%0" : "=m" (*envp));
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/* fnstenv has the side effect of masking all exceptions, so we need
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to restore the control word after that. */
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__asm__ __volatile__ ("fldcw\t%0" : : "m" (envp->__control_word));
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if (has_sse())
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (envp->__mxcsr));
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}
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void
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set_fpu_state (void *state)
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{
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struct fenv *envp = state;
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/* glibc sources (sysdeps/x86_64/fpu/fesetenv.c) do something more
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complex than this, but I think it suffices in our case. */
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__asm__ __volatile__ ("fldenv\t%0" : : "m" (*envp));
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if (has_sse())
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__asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (envp->__mxcsr));
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}
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int
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support_fpu_underflow_control (int kind)
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{
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if (!has_sse())
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return 0;
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return (kind == 4 || kind == 8) ? 1 : 0;
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}
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int
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get_fpu_underflow_mode (void)
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{
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unsigned int cw_sse;
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if (!has_sse())
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return 1;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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/* Return 0 for abrupt underflow (flush to zero), 1 for gradual underflow. */
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return (cw_sse & MXCSR_FTZ) ? 0 : 1;
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}
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void
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set_fpu_underflow_mode (int gradual)
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{
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unsigned int cw_sse;
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if (!has_sse())
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return;
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__asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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if (gradual)
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cw_sse &= ~MXCSR_FTZ;
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else
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cw_sse |= MXCSR_FTZ;
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__asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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}
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