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The INDEX patterns handle partial modes by choosing the container size rather than the element size, so that the number of lanes (and thus number of additions) matches the mode. This means that all VNx4 modes use .s and all VNx2 modes use .d, etc. When adding this, I'd forgotten that the choice between Wn and Xn registers would need to be updated to use the container size too. For partial VNx2s, we were using .d containers with Wn rather than Xn source registers. 2019-12-10 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (vccore): New iterator. * config/aarch64/aarch64-sve.md (vec_series<mode>): Use it instead of vwcore. (*vec_series<mode>_plus): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/mixed_size_6.c: New test. From-SVN: r279173 |
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| config | ||
| contrib | ||
| fixincludes | ||
| gcc | ||
| gnattools | ||
| gotools | ||
| include | ||
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| intl | ||
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| libgfortran | ||
| libgo | ||
| libgomp | ||
| libhsail-rt | ||
| libiberty | ||
| libitm | ||
| libobjc | ||
| liboffloadmic | ||
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| libquadmath | ||
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| libstdc++-v3 | ||
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| lto-plugin | ||
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| .dir-locals.el | ||
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| libtool-ldflags | ||
| libtool.m4 | ||
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| ltsugar.m4 | ||
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