227 lines
7.2 KiB
ArmAsm
227 lines
7.2 KiB
ArmAsm
; Copyright (C) 2014-2015 Free Software Foundation, Inc.
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; Contributed by Red Hat.
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;
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; This file is free software; you can redistribute it and/or modify it
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; under the terms of the GNU General Public License as published by the
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; Free Software Foundation; either version 3, or (at your option) any
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; later version.
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;
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; This file is distributed in the hope that it will be useful, but
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; WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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; General Public License for more details.
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;
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; Under Section 7 of GPL version 3, you are granted additional
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; permissions described in the GCC Runtime Library Exception, version
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; 3.1, as published by the Free Software Foundation.
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;
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; You should have received a copy of the GNU General Public License and
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; a copy of the GCC Runtime Library Exception along with this program;
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; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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; <http://www.gnu.org/licenses/>.
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.macro start_func name
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.pushsection .text.\name,"ax",@progbits
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.p2align 1
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.global \name
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.type \name , @function
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\name:
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PUSH.W sr ; Save current interrupt state
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DINT ; Disable interrupts
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NOP ; Account for latency
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.endm
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.macro end_func name
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#ifdef __MSP430X_LARGE__
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POP.W sr
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RETA
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#else
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RETI
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#endif
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.size \name , . - \name
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.popsection
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.endm
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.macro mult16 OP1, OP2, RESULT
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;* * 16-bit hardware multiply: int16 = int16 * int16
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;*
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;* - Operand 1 is in R12
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;* - Operand 2 is in R13
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;* - Result is in R12
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;*
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;* To ensure that the multiply is performed atomically, interrupts are
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;* disabled upon routine entry. Interrupt state is restored upon exit.
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;*
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;* Registers used: R12, R13
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;*
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;* Macro arguments are the memory locations of the hardware registers.
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MOV.W r12, &\OP1 ; Load operand 1 into multiplier
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MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
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MOV.W &\RESULT, r12 ; Move result into return register
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.endm
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.macro mult1632 OP1, OP2, RESULT_LO, RESULT_HI
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;* * 16-bit hardware multiply with a 32-bit result:
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;* int32 = int16 * int16
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;* uint32 = uint16 * uint16
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;*
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;* - Operand 1 is in R12
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;* - Operand 2 is in R13
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;* - Result is in R12, R13
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;*
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;* To ensure that the multiply is performed atomically, interrupts are
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;* disabled upon routine entry. Interrupt state is restored upon exit.
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;*
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;* Registers used: R12, R13
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;*
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;* Macro arguments are the memory locations of the hardware registers.
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MOV.W r12, &\OP1 ; Load operand 1 into multiplier
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MOV.W r13, &\OP2 ; Load operand 2 which triggers MPY
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MOV.W &\RESULT_LO, r12 ; Move low result into return register
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MOV.W &\RESULT_HI, r13 ; Move high result into return register
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.endm
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.macro mult32 OP1, OP2, MAC_OP1, MAC_OP2, RESULT_LO, RESULT_HI
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;* * 32-bit hardware multiply with a 32-bit result using 16 multiply and accumulate:
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;* int32 = int32 * int32
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;*
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;* - Operand 1 is in R12, R13
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;* - Operand 2 is in R14, R15
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;* - Result is in R12, R13
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;*
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;* To ensure that the multiply is performed atomically, interrupts are
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;* disabled upon routine entry. Interrupt state is restored upon exit.
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;*
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;* Registers used: R12, R13, R14, R15
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;*
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;* Macro arguments are the memory locations of the hardware registers.
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MOV.W r12, &\OP1 ; Load operand 1 Low into multiplier
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MOV.W r14, &\OP2 ; Load operand 2 Low which triggers MPY
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MOV.W r12, &\MAC_OP1 ; Load operand 1 Low into mac
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MOV.W &\RESULT_LO, r12 ; Low 16-bits of result ready for return
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MOV.W &\RESULT_HI, &\RESULT_LO; MOV intermediate mpy high into low
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MOV.W r15, &\MAC_OP2 ; Load operand 2 High, trigger MAC
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MOV.W r13, &\MAC_OP1 ; Load operand 1 High
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MOV.W r14, &\MAC_OP2 ; Load operand 2 Lo, trigger MAC
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MOV.W &\RESULT_LO, r13 ; Upper 16-bits result ready for return
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.endm
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.macro mult32_hw OP1_LO OP1_HI OP2_LO OP2_HI RESULT_LO RESULT_HI
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;* * 32-bit hardware multiply with a 32-bit result
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;* int32 = int32 * int32
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;*
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;* - Operand 1 is in R12, R13
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;* - Operand 2 is in R14, R15
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;* - Result is in R12, R13
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;*
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;* To ensure that the multiply is performed atomically, interrupts are
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;* disabled upon routine entry. Interrupt state is restored upon exit.
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;*
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;* Registers used: R12, R13, R14, R15
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;*
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;* Macro arguments are the memory locations of the hardware registers.
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MOV.W r12, &\OP1_LO ; Load operand 1 Low into multiplier
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MOV.W r13, &\OP1_HI ; Load operand 1 High into multiplier
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MOV.W r14, &\OP2_LO ; Load operand 2 Low into multiplier
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MOV.W r15, &\OP2_HI ; Load operand 2 High, trigger MPY
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MOV.W &\RESULT_LO, r12 ; Ready low 16-bits for return
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MOV.W &\RESULT_HI, r13 ; Ready high 16-bits for return
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.endm
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.macro mult3264_hw OP1_LO OP1_HI OP2_LO OP2_HI RES0 RES1 RES2 RES3
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;* * 32-bit hardware multiply with a 64-bit result
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;* int64 = int32 * int32
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;* uint64 = uint32 * uint32
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;*
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;* - Operand 1 is in R12, R13
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;* - Operand 2 is in R14, R15
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;* - Result is in R12, R13, R14, R15
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;*
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;* To ensure that the multiply is performed atomically, interrupts are
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;* disabled upon routine entry. Interrupt state is restored upon exit.
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;*
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;* Registers used: R12, R13, R14, R15
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;*
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;* Macro arguments are the memory locations of the hardware registers.
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MOV.W r12, &\OP1_LO ; Load operand 1 Low into multiplier
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MOV.W r13, &\OP1_HI ; Load operand 1 High into multiplier
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MOV.W r14, &\OP2_LO ; Load operand 2 Low into multiplier
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MOV.W r15, &\OP2_HI ; Load operand 2 High, trigger MPY
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MOV.W &\RES0, R12 ; Ready low 16-bits for return
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MOV.W &\RES1, R13 ;
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MOV.W &\RES2, R14 ;
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MOV.W &\RES3, R15 ; Ready high 16-bits for return
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.endm
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;; First generation MSP430 hardware multiplies ....
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.set MPY_OP1, 0x0130
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.set MPY_OP1_S, 0x0132
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.set MAC_OP1, 0x0134
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.set MPY_OP2, 0x0138
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.set MAC_OP2, 0x0138
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.set RESULT_LO, 0x013A
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.set RESULT_HI, 0x013C
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start_func __mulhi2
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mult16 MPY_OP1, MPY_OP2, RESULT_LO
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end_func __mulhi2
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start_func __mulsihi2
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mult1632 MPY_OP1_S, MPY_OP2, RESULT_LO, RESULT_HI
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end_func __mulsihi2
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start_func __umulsihi2
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mult1632 MPY_OP1, MPY_OP2, RESULT_LO, RESULT_HI
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end_func __umulsihi2
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start_func __mulsi2
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mult32 MPY_OP1, MPY_OP2, MAC_OP1, MAC_OP2, RESULT_LO, RESULT_HI
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end_func __mulsi2
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start_func __mulsi2_hw32
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mult32_hw 0x0140, 0x0142, 0x0150, 0x0152, 0x0154, 0x0156
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end_func __mulsi2_hw32
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start_func __muldisi2_hw32
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mult3264_hw 0x0144, 0x146, 0x0150, 0x0152, 0x0154, 0x0156, 0x0158, 0x015A
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end_func __muldisi2_hw32
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start_func __umuldisi2_hw32
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mult3264_hw 0x0140, 0x142, 0x0150, 0x0152, 0x0154, 0x0156, 0x0158, 0x015A
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end_func __umuldisi2_hw32
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/* The F5xxx series of MCUs support the same 16-bit hardware
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multiply, but it is accessed from different memory registers. */
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start_func __mulhi2_f5
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mult16 0x04C0, 0x04C8, 0x04CA
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end_func __mulhi2_f5
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start_func __mulsihi2_f5
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mult1632 0x04C2, 0x04C8, 0x04CA, 0x04CC
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end_func __mulsihi2_f5
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start_func __umulsihi2_f5
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mult1632 0x04C0, 0x04C8, 0x04CA, 0x04CC
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end_func __umulsihi2_f5
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start_func __mulsi2_f5
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mult32_hw 0x04D0, 0x04D2, 0x04E0, 0x04E2, 0x04E4, 0x04E6
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end_func __mulsi2_f5
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start_func __muldisi2_f5
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mult3264_hw 0x04D4, 0x04D6, 0x04E0, 0x04E2, 0x04E4, 0x04E6, 0x04E8, 0x04EA
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end_func __muldisi2_f5
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start_func __umuldisi2_f5
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mult3264_hw 0x04D0, 0x04D2, 0x04E0, 0x04E2, 0x04E4, 0x04E6, 0x04E8, 0x04EA
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end_func __umuldisi2_f5
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