187 lines
6.4 KiB
C
187 lines
6.4 KiB
C
/* Synopsys DesignWare ARC SIMD include file.
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Copyright (C) 2007-2015 Free Software Foundation, Inc.
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Written by Saurabh Verma (saurabh.verma@celunite.com) on behalf os Synopsys
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Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* As a special exception, if you include this header file into source
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files compiled by GCC, this header file does not by itself cause
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the resulting executable to be covered by the GNU General Public
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License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General
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Public License. */
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#ifndef _ARC_SIMD_H
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#define _ARC_SIMD_H 1
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#ifndef __ARC_SIMD__
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#error Use the "-msimd" flag to enable ARC SIMD support
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#endif
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/* I0-I7 registers. */
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#define _IREG_I0 0
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#define _IREG_I1 1
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#define _IREG_I2 2
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#define _IREG_I3 3
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#define _IREG_I4 4
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#define _IREG_I5 5
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#define _IREG_I6 6
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#define _IREG_I7 7
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/* DMA configuration registers. */
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#define _DMA_REG_DR0 0
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#define _DMA_SDM_SRC_ADR_REG _DMA_REG_DR0
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#define _DMA_SDM_DEST_ADR_REG _DMA_REG_DR0
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#define _DMA_REG_DR1 1
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#define _DMA_SDM_STRIDE_REG _DMA_REG_DR1
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#define _DMA_REG_DR2 2
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#define _DMA_BLK_REG _DMA_REG_DR2
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#define _DMA_REG_DR3 3
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#define _DMA_LOC_REG _DMA_REG_DR3
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#define _DMA_REG_DR4 4
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#define _DMA_SYS_SRC_ADR_REG _DMA_REG_DR4
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#define _DMA_SYS_DEST_ADR_REG _DMA_REG_DR4
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#define _DMA_REG_DR5 5
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#define _DMA_SYS_STRIDE_REG _DMA_REG_DR5
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#define _DMA_REG_DR6 6
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#define _DMA_CFG_REG _DMA_REG_DR6
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#define _DMA_REG_DR7 7
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#define _DMA_FT_BASE_ADR_REG _DMA_REG_DR7
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/* Predefined types used in vector instructions. */
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typedef int __v4si __attribute__((vector_size(16)));
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typedef short __v8hi __attribute__((vector_size(16)));
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/* Synonyms */
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#define _vaddaw __builtin_arc_vaddaw
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#define _vaddw __builtin_arc_vaddw
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#define _vavb __builtin_arc_vavb
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#define _vavrb __builtin_arc_vavrb
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#define _vdifaw __builtin_arc_vdifaw
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#define _vdifw __builtin_arc_vdifw
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#define _vmaxaw __builtin_arc_vmaxaw
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#define _vmaxw __builtin_arc_vmaxw
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#define _vminaw __builtin_arc_vminaw
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#define _vminw __builtin_arc_vminw
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#define _vmulaw __builtin_arc_vmulaw
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#define _vmulfaw __builtin_arc_vmulfaw
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#define _vmulfw __builtin_arc_vmulfw
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#define _vmulw __builtin_arc_vmulw
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#define _vsubaw __builtin_arc_vsubaw
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#define _vsubw __builtin_arc_vsubw
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#define _vsummw __builtin_arc_vsummw
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#define _vand __builtin_arc_vand
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#define _vandaw __builtin_arc_vandaw
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#define _vbic __builtin_arc_vbic
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#define _vbicaw __builtin_arc_vbicaw
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#define _vor __builtin_arc_vor
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#define _vxor __builtin_arc_vxor
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#define _vxoraw __builtin_arc_vxoraw
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#define _veqw __builtin_arc_veqw
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#define _vlew __builtin_arc_vlew
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#define _vltw __builtin_arc_vltw
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#define _vnew __builtin_arc_vnew
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#define _vmr1aw __builtin_arc_vmr1aw
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#define _vmr1w __builtin_arc_vmr1w
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#define _vmr2aw __builtin_arc_vmr2aw
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#define _vmr2w __builtin_arc_vmr2w
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#define _vmr3aw __builtin_arc_vmr3aw
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#define _vmr3w __builtin_arc_vmr3w
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#define _vmr4aw __builtin_arc_vmr4aw
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#define _vmr4w __builtin_arc_vmr4w
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#define _vmr5aw __builtin_arc_vmr5aw
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#define _vmr5w __builtin_arc_vmr5w
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#define _vmr6aw __builtin_arc_vmr6aw
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#define _vmr6w __builtin_arc_vmr6w
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#define _vmr7aw __builtin_arc_vmr7aw
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#define _vmr7w __builtin_arc_vmr7w
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#define _vmrb __builtin_arc_vmrb
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#define _vh264f __builtin_arc_vh264f
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#define _vh264ft __builtin_arc_vh264ft
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#define _vh264fw __builtin_arc_vh264fw
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#define _vvc1f __builtin_arc_vvc1f
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#define _vvc1ft __builtin_arc_vvc1ft
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#define _vbaddw __builtin_arc_vbaddw
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#define _vbmaxw __builtin_arc_vbmaxw
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#define _vbminw __builtin_arc_vbminw
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#define _vbmulaw __builtin_arc_vbmulaw
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#define _vbmulfw __builtin_arc_vbmulfw
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#define _vbmulw __builtin_arc_vbmulw
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#define _vbrsubw __builtin_arc_vbrsubw
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#define _vbsubw __builtin_arc_vbsubw
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#define _vasrw __builtin_arc_vasrw
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#define _vsr8 __builtin_arc_vsr8
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#define _vsr8aw __builtin_arc_vsr8aw
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#define _vasrrwi __builtin_arc_vasrrwi
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#define _vasrsrwi __builtin_arc_vasrsrwi
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#define _vasrwi __builtin_arc_vasrwi
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#define _vasrpwbi __builtin_arc_vasrpwbi
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#define _vasrrpwbi __builtin_arc_vasrrpwbi
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#define _vsr8awi __builtin_arc_vsr8awi
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#define _vsr8i __builtin_arc_vsr8i
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#define _vmvaw __builtin_arc_vmvaw
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#define _vmvw __builtin_arc_vmvw
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#define _vmvzw __builtin_arc_vmvzw
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#define _vd6tapf __builtin_arc_vd6tapf
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#define _vmovaw __builtin_arc_vmovaw
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#define _vmovw __builtin_arc_vmovw
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#define _vmovzw __builtin_arc_vmovzw
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#define _vabsaw __builtin_arc_vabsaw
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#define _vabsw __builtin_arc_vabsw
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#define _vaddsuw __builtin_arc_vaddsuw
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#define _vsignw __builtin_arc_vsignw
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#define _vexch1 __builtin_arc_vexch1
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#define _vexch2 __builtin_arc_vexch2
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#define _vexch4 __builtin_arc_vexch4
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#define _vupbaw __builtin_arc_vupbaw
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#define _vupbw __builtin_arc_vupbw
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#define _vupsbaw __builtin_arc_vupsbaw
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#define _vupsbw __builtin_arc_vupsbw
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#define _vdirun __builtin_arc_vdirun
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#define _vdorun __builtin_arc_vdorun
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#define _vdiwr __builtin_arc_vdiwr
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#define _vdowr __builtin_arc_vdowr
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#define _vrec __builtin_arc_vrec
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#define _vrun __builtin_arc_vrun
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#define _vrecrun __builtin_arc_vrecrun
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#define _vendrec __builtin_arc_vendrec
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#define _vld32wh __builtin_arc_vld32wh
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#define _vld32wl __builtin_arc_vld32wl
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#define _vld64 __builtin_arc_vld64
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#define _vld32 __builtin_arc_vld32
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#define _vld64w __builtin_arc_vld64w
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#define _vld128 __builtin_arc_vld128
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#define _vst128 __builtin_arc_vst128
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#define _vst64 __builtin_arc_vst64
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#define _vst16_n __builtin_arc_vst16_n
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#define _vst32_n __builtin_arc_vst32_n
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#define _vinti __builtin_arc_vinti
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/* Additional synonyms to ease programming. */
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#define _setup_dma_in_channel_reg _vdiwr
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#define _setup_dma_out_channel_reg _vdowr
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#endif /* _ARC_SIMD_H */
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