134 lines
4.2 KiB
C++
134 lines
4.2 KiB
C++
//===-- sanitizer_atomic_clang.h --------------------------------*- C++ -*-===//
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of ThreadSanitizer/AddressSanitizer runtime.
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// Not intended for direct inclusion. Include sanitizer_atomic.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SANITIZER_ATOMIC_CLANG_H
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#define SANITIZER_ATOMIC_CLANG_H
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namespace __sanitizer {
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INLINE void atomic_signal_fence(memory_order) {
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__asm__ __volatile__("" ::: "memory");
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}
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INLINE void atomic_thread_fence(memory_order) {
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__sync_synchronize();
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}
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INLINE void proc_yield(int cnt) {
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__asm__ __volatile__("" ::: "memory");
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#if defined(__i386__) || defined(__x86_64__)
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for (int i = 0; i < cnt; i++)
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__asm__ __volatile__("pause");
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#endif
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__asm__ __volatile__("" ::: "memory");
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}
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template<typename T>
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INLINE typename T::Type atomic_load(
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const volatile T *a, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_consume
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| memory_order_acquire | memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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typename T::Type v;
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// FIXME:
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// 64-bit atomic operations are not atomic on 32-bit platforms.
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// The implementation lacks necessary memory fences on ARM/PPC.
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// We would like to use compiler builtin atomic operations,
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// but they are mostly broken:
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// - they lead to vastly inefficient code generation
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// (http://llvm.org/bugs/show_bug.cgi?id=17281)
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// - 64-bit atomic operations are not implemented on x86_32
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// (http://llvm.org/bugs/show_bug.cgi?id=15034)
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// - they are not implemented on ARM
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// error: undefined reference to '__atomic_load_4'
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if (mo == memory_order_relaxed) {
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v = a->val_dont_use;
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} else {
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atomic_signal_fence(memory_order_seq_cst);
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v = a->val_dont_use;
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atomic_signal_fence(memory_order_seq_cst);
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}
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return v;
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}
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template<typename T>
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INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_release
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| memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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if (mo == memory_order_relaxed) {
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a->val_dont_use = v;
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} else {
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atomic_signal_fence(memory_order_seq_cst);
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a->val_dont_use = v;
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atomic_signal_fence(memory_order_seq_cst);
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}
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if (mo == memory_order_seq_cst)
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atomic_thread_fence(memory_order_seq_cst);
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}
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template<typename T>
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INLINE typename T::Type atomic_fetch_add(volatile T *a,
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typename T::Type v, memory_order mo) {
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(void)mo;
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DCHECK(!((uptr)a % sizeof(*a)));
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return __sync_fetch_and_add(&a->val_dont_use, v);
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}
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template<typename T>
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INLINE typename T::Type atomic_fetch_sub(volatile T *a,
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typename T::Type v, memory_order mo) {
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(void)mo;
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DCHECK(!((uptr)a % sizeof(*a)));
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return __sync_fetch_and_add(&a->val_dont_use, -v);
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}
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template<typename T>
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INLINE typename T::Type atomic_exchange(volatile T *a,
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typename T::Type v, memory_order mo) {
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DCHECK(!((uptr)a % sizeof(*a)));
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if (mo & (memory_order_release | memory_order_acq_rel | memory_order_seq_cst))
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__sync_synchronize();
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v = __sync_lock_test_and_set(&a->val_dont_use, v);
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if (mo == memory_order_seq_cst)
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__sync_synchronize();
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return v;
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}
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template<typename T>
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INLINE bool atomic_compare_exchange_strong(volatile T *a,
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typename T::Type *cmp,
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typename T::Type xchg,
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memory_order mo) {
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typedef typename T::Type Type;
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Type cmpv = *cmp;
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Type prev = __sync_val_compare_and_swap(&a->val_dont_use, cmpv, xchg);
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if (prev == cmpv)
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return true;
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*cmp = prev;
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return false;
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}
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template<typename T>
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INLINE bool atomic_compare_exchange_weak(volatile T *a,
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typename T::Type *cmp,
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typename T::Type xchg,
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memory_order mo) {
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return atomic_compare_exchange_strong(a, cmp, xchg, mo);
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}
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} // namespace __sanitizer
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#undef ATOMIC_ORDER
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#endif // SANITIZER_ATOMIC_CLANG_H
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