88 lines
3.0 KiB
C
88 lines
3.0 KiB
C
/* Machine description for AArch64 architecture.
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Copyright (C) 2012-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#define CTR_IDC_SHIFT 28
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#define CTR_DIC_SHIFT 29
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void __aarch64_sync_cache_range (const void *, const void *);
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void
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__aarch64_sync_cache_range (const void *base, const void *end)
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{
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unsigned icache_lsize;
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unsigned dcache_lsize;
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static unsigned int cache_info = 0;
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const char *address;
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if (! cache_info)
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/* CTR_EL0 [3:0] contains log2 of icache line size in words.
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CTR_EL0 [19:16] contains log2 of dcache line size in words. */
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asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
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icache_lsize = 4 << (cache_info & 0xF);
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dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
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/* If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification is
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not required for instruction to data coherence. */
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if (((cache_info >> CTR_IDC_SHIFT) & 0x1) == 0x0) {
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/* Loop over the address range, clearing one cache line at once.
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Data cache must be flushed to unification first to make sure the
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instruction cache fetches the updated data. 'end' is exclusive,
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as per the GNU definition of __clear_cache. */
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/* Make the start address of the loop cache aligned. */
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address = (const char*) ((__UINTPTR_TYPE__) base
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& ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
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for (; address < (const char *) end; address += dcache_lsize)
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asm volatile ("dc\tcvau, %0"
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:
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: "r" (address)
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: "memory");
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}
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asm volatile ("dsb\tish" : : : "memory");
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/* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point of
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Unification is not required for instruction to data coherence. */
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if (((cache_info >> CTR_DIC_SHIFT) & 0x1) == 0x0) {
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/* Make the start address of the loop cache aligned. */
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address = (const char*) ((__UINTPTR_TYPE__) base
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& ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
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for (; address < (const char *) end; address += icache_lsize)
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asm volatile ("ic\tivau, %0"
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:
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: "r" (address)
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: "memory");
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asm volatile ("dsb\tish" : : : "memory");
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}
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asm volatile("isb" : : : "memory");
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}
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