gcc/libgcc/config/riscv/muldi3.S
Palmer Dabbelt 0bd99911ee RISC-V Port: libgcc
libgcc/ChangeLog:

2017-02-06  Palmer Dabbelt <palmer@dabbelt.com>

        * config.host: Add RISC-V tuples.
        * config/riscv/atomic.c: New file.
        * config/riscv/crti.S: Likewise.
        * config/riscv/crtn.S: Likewise.
        * config/riscv/div.S: Likewise.
        * config/riscv/linux-unwind.h: Likewise.
        * config/riscv/muldi3.S: Likewise.
        * config/riscv/multi3.S: Likewise.
        * config/riscv/save-restore.S: Likewise.
        * config/riscv/sfp-machine.h: Likewise.
        * config/riscv/t-elf: Likewise.
        * config/riscv/t-elf32: Likewise.
        * config/riscv/t-elf64: Likewise.
        * config/riscv/t-softfp32: Likewise.
        * config/riscv/t-softfp64: Likewise.

From-SVN: r245226
2017-02-06 21:38:51 +00:00

47 lines
1.3 KiB
ArmAsm

/* Integer multiplication routines for RISC-V.
Copyright (C) 2016-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.text
.align 2
#if __riscv_xlen == 32
/* Our RV64 64-bit routine is equivalent to our RV32 32-bit routine. */
# define __muldi3 __mulsi3
#endif
.globl __muldi3
__muldi3:
mv a2, a0
li a0, 0
.L1:
andi a3, a1, 1
beqz a3, .L2
add a0, a0, a2
.L2:
srli a1, a1, 1
slli a2, a2, 1
bnez a1, .L1
ret