6b9ce2b4eb
Unified syntax has been the official syntax for thumb1 assembly for over 10 years now. It's time we made preparations for that becoming the default in the assembler. But before we can start doing that we really need to clean up some laggards from the olden days. Libgcc support for thumb1 is one such example. This patch converts all of the legacy (disjoint) syntax that I could find over to unified code. The identification was done by using a trick version of gas that defaulted to unified mode which then faults if legacy syntax is encountered. The code produced was then compared against the old code to check for differences. One such difference does exist, but that is because in unified syntax 'movs rd, rn' is encoded as 'lsls rd, rn, #0', rather than 'adds rd, rn, #0'; but that is a deliberate change that was introduced because the lsls encoding more closely reflects the behaviour of 'movs' in arm state (where only some of the condition flags are modified). * config/arm/bpabi-v6m.S (aeabi_lcmp): Convert thumb1 code to unified syntax. (aeabi_ulcmp, aeabi_ldivmod, aeabi_uldivmod): Likewise. (aeabi_frsub, aeabi_cfcmpeq, aeabi_fcmpeq): Likewise. (aeabi_fcmp, aeabi_drsub, aeabi_cdrcmple): Likewise. (aeabi_cdcmpeq, aeabi_dcmpeq, aeabi_dcmp): Likewise. * config/arm/lib1funcs.S (Lend_fde): Convert thumb1 code to unified syntax. (divsi3, modsi3): Likewise. (clzdi2, ctzsi2): Likewise. * config/arm/libunwind.S (restore_core_regs): Convert thumb1 code to unified syntax. (UNWIND_WRAPPER): Likewise.
363 lines
11 KiB
ArmAsm
363 lines
11 KiB
ArmAsm
/* Support functions for the unwinder.
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Copyright (C) 2003-2020 Free Software Foundation, Inc.
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Contributed by Paul Brook
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 3, or (at your option) any
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* An executable stack is *not* required for these functions. */
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#if defined(__ELF__) && defined(__linux__)
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.section .note.GNU-stack,"",%progbits
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.previous
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#endif
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#ifdef __ARM_EABI__
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/* Some attributes that are common to all routines in this file. */
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/* Tag_ABI_align_needed: This code does not require 8-byte
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alignment from the caller. */
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/* .eabi_attribute 24, 0 -- default setting. */
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/* Tag_ABI_align_preserved: This code preserves 8-byte
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alignment in any callee. */
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.eabi_attribute 25, 1
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#endif /* __ARM_EABI__ */
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#ifndef __symbian__
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#include "lib1funcs.S"
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.macro UNPREFIX name
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.global SYM (\name)
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EQUIV SYM (\name), SYM (__\name)
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.endm
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#if (__ARM_ARCH == 4)
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/* Some coprocessors require armv5t. We know this code will never be run on
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other cpus. Tell gas to allow armv5t, but only mark the objects as armv4.
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*/
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.arch armv5t
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#ifdef __ARM_ARCH_4T__
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.object_arch armv4t
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#else
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.object_arch armv4
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#endif
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#endif
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#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1
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/* r0 points to a 16-word block. Upload these values to the actual core
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state. */
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FUNC_START restore_core_regs
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movs r1, r0
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adds r1, r1, #52
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ldmia r1!, {r3, r4, r5}
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subs r3, r3, #4
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mov ip, r3
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str r5, [r3]
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mov lr, r4
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/* Restore r8-r11. */
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movs r1, r0
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adds r1, r1, #32
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ldmia r1!, {r2, r3, r4, r5}
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mov r8, r2
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mov r9, r3
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mov sl, r4
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mov fp, r5
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movs r1, r0
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adds r1, r1, #8
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ldmia r1!, {r2, r3, r4, r5, r6, r7}
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ldr r1, [r0, #4]
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ldr r0, [r0]
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mov sp, ip
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pop {pc}
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FUNC_END restore_core_regs
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UNPREFIX restore_core_regs
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/* ARMV6M does not have coprocessors, so these should never be used. */
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FUNC_START gnu_Unwind_Restore_VFP
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RET
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/* Store VFR regsters d0-d15 to the address in r0. */
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FUNC_START gnu_Unwind_Save_VFP
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RET
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/* Load VFP registers d0-d15 from the address in r0.
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Use this to load from FSTMD format. */
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FUNC_START gnu_Unwind_Restore_VFP_D
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RET
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/* Store VFP registers d0-d15 to the address in r0.
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Use this to store in FLDMD format. */
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FUNC_START gnu_Unwind_Save_VFP_D
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RET
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/* Load VFP registers d16-d31 from the address in r0.
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Use this to load from FSTMD (=VSTM) format. Needs VFPv3. */
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FUNC_START gnu_Unwind_Restore_VFP_D_16_to_31
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RET
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/* Store VFP registers d16-d31 to the address in r0.
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Use this to store in FLDMD (=VLDM) format. Needs VFPv3. */
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FUNC_START gnu_Unwind_Save_VFP_D_16_to_31
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RET
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FUNC_START gnu_Unwind_Restore_WMMXD
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RET
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FUNC_START gnu_Unwind_Save_WMMXD
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RET
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FUNC_START gnu_Unwind_Restore_WMMXC
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RET
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FUNC_START gnu_Unwind_Save_WMMXC
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RET
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.macro UNWIND_WRAPPER name nargs
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FUNC_START \name
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/* Create a phase2_vrs structure. */
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/* Save r0 in the PC slot so we can use it as a scratch register. */
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push {r0}
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add r0, sp, #4
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push {r0, lr} /* Push original SP and LR. */
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/* Make space for r8-r12. */
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sub sp, sp, #20
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/* Save low registers. */
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push {r0, r1, r2, r3, r4, r5, r6, r7}
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/* Save high registers. */
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add r0, sp, #32
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mov r1, r8
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mov r2, r9
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mov r3, sl
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mov r4, fp
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mov r5, ip
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stmia r0!, {r1, r2, r3, r4, r5}
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/* Restore original low register values. */
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add r0, sp, #4
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ldmia r0!, {r1, r2, r3, r4, r5}
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/* Restore orginial r0. */
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ldr r0, [sp, #60]
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str r0, [sp]
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/* Demand-save flags, plus an extra word for alignment. */
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movs r3, #0
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push {r2, r3}
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/* Point r1 at the block. Pass r[0..nargs) unchanged. */
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add r\nargs, sp, #4
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bl SYM (__gnu\name)
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ldr r3, [sp, #64]
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add sp, sp, #72
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bx r3
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FUNC_END \name
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UNPREFIX \name
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.endm
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#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
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/* r0 points to a 16-word block. Upload these values to the actual core
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state. */
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ARM_FUNC_START restore_core_regs
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/* We must use sp as the base register when restoring sp. Push the
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last 3 registers onto the top of the current stack to achieve
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this. */
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add r1, r0, #52
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ldmia r1, {r3, r4, r5} /* {sp, lr, pc}. */
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#if defined(__thumb2__)
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/* Thumb-2 doesn't allow sp in a load-multiple instruction, so push
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the target address onto the target stack. This is safe as
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we're always returning to somewhere further up the call stack. */
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mov ip, r3
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mov lr, r4
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str r5, [ip, #-4]!
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#elif defined(__INTERWORKING__)
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/* Restore pc into ip. */
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mov r2, r5
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stmfd sp!, {r2, r3, r4}
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#else
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stmfd sp!, {r3, r4, r5}
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#endif
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/* Don't bother restoring ip. */
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ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp}
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#if defined(__thumb2__)
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/* Pop the return address off the target stack. */
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mov sp, ip
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pop {pc}
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#elif defined(__INTERWORKING__)
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/* Pop the three registers we pushed earlier. */
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ldmfd sp, {ip, sp, lr}
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bx ip
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#else
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ldmfd sp, {sp, lr, pc}
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#endif
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FUNC_END restore_core_regs
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UNPREFIX restore_core_regs
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/* Load VFP registers d0-d15 from the address in r0.
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Use this to load from FSTMX format. */
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ARM_FUNC_START gnu_Unwind_Restore_VFP
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/* Use the generic coprocessor form so that gas doesn't complain
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on soft-float targets. */
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ldc p11,cr0,[r0],{0x21} /* fldmiax r0, {d0-d15} */
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RET
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/* Store VFP registers d0-d15 to the address in r0.
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Use this to store in FSTMX format. */
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ARM_FUNC_START gnu_Unwind_Save_VFP
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/* Use the generic coprocessor form so that gas doesn't complain
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on soft-float targets. */
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stc p11,cr0,[r0],{0x21} /* fstmiax r0, {d0-d15} */
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RET
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/* Load VFP registers d0-d15 from the address in r0.
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Use this to load from FSTMD format. */
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ARM_FUNC_START gnu_Unwind_Restore_VFP_D
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ldc p11,cr0,[r0],{0x20} /* fldmiad r0, {d0-d15} */
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RET
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/* Store VFP registers d0-d15 to the address in r0.
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Use this to store in FLDMD format. */
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ARM_FUNC_START gnu_Unwind_Save_VFP_D
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stc p11,cr0,[r0],{0x20} /* fstmiad r0, {d0-d15} */
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RET
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/* Load VFP registers d16-d31 from the address in r0.
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Use this to load from FSTMD (=VSTM) format. Needs VFPv3. */
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ARM_FUNC_START gnu_Unwind_Restore_VFP_D_16_to_31
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ldcl p11,cr0,[r0],{0x20} /* vldm r0, {d16-d31} */
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RET
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/* Store VFP registers d16-d31 to the address in r0.
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Use this to store in FLDMD (=VLDM) format. Needs VFPv3. */
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ARM_FUNC_START gnu_Unwind_Save_VFP_D_16_to_31
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stcl p11,cr0,[r0],{0x20} /* vstm r0, {d16-d31} */
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RET
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ARM_FUNC_START gnu_Unwind_Restore_WMMXD
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/* Use the generic coprocessor form so that gas doesn't complain
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on non-iWMMXt targets. */
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ldcl p1, cr0, [r0], #8 /* wldrd wr0, [r0], #8 */
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ldcl p1, cr1, [r0], #8 /* wldrd wr1, [r0], #8 */
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ldcl p1, cr2, [r0], #8 /* wldrd wr2, [r0], #8 */
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ldcl p1, cr3, [r0], #8 /* wldrd wr3, [r0], #8 */
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ldcl p1, cr4, [r0], #8 /* wldrd wr4, [r0], #8 */
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ldcl p1, cr5, [r0], #8 /* wldrd wr5, [r0], #8 */
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ldcl p1, cr6, [r0], #8 /* wldrd wr6, [r0], #8 */
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ldcl p1, cr7, [r0], #8 /* wldrd wr7, [r0], #8 */
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ldcl p1, cr8, [r0], #8 /* wldrd wr8, [r0], #8 */
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ldcl p1, cr9, [r0], #8 /* wldrd wr9, [r0], #8 */
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ldcl p1, cr10, [r0], #8 /* wldrd wr10, [r0], #8 */
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ldcl p1, cr11, [r0], #8 /* wldrd wr11, [r0], #8 */
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ldcl p1, cr12, [r0], #8 /* wldrd wr12, [r0], #8 */
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ldcl p1, cr13, [r0], #8 /* wldrd wr13, [r0], #8 */
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ldcl p1, cr14, [r0], #8 /* wldrd wr14, [r0], #8 */
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ldcl p1, cr15, [r0], #8 /* wldrd wr15, [r0], #8 */
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RET
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ARM_FUNC_START gnu_Unwind_Save_WMMXD
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/* Use the generic coprocessor form so that gas doesn't complain
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on non-iWMMXt targets. */
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stcl p1, cr0, [r0], #8 /* wstrd wr0, [r0], #8 */
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stcl p1, cr1, [r0], #8 /* wstrd wr1, [r0], #8 */
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stcl p1, cr2, [r0], #8 /* wstrd wr2, [r0], #8 */
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stcl p1, cr3, [r0], #8 /* wstrd wr3, [r0], #8 */
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stcl p1, cr4, [r0], #8 /* wstrd wr4, [r0], #8 */
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stcl p1, cr5, [r0], #8 /* wstrd wr5, [r0], #8 */
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stcl p1, cr6, [r0], #8 /* wstrd wr6, [r0], #8 */
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stcl p1, cr7, [r0], #8 /* wstrd wr7, [r0], #8 */
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stcl p1, cr8, [r0], #8 /* wstrd wr8, [r0], #8 */
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stcl p1, cr9, [r0], #8 /* wstrd wr9, [r0], #8 */
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stcl p1, cr10, [r0], #8 /* wstrd wr10, [r0], #8 */
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stcl p1, cr11, [r0], #8 /* wstrd wr11, [r0], #8 */
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stcl p1, cr12, [r0], #8 /* wstrd wr12, [r0], #8 */
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stcl p1, cr13, [r0], #8 /* wstrd wr13, [r0], #8 */
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stcl p1, cr14, [r0], #8 /* wstrd wr14, [r0], #8 */
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stcl p1, cr15, [r0], #8 /* wstrd wr15, [r0], #8 */
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RET
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ARM_FUNC_START gnu_Unwind_Restore_WMMXC
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/* Use the generic coprocessor form so that gas doesn't complain
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on non-iWMMXt targets. */
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ldc2 p1, cr8, [r0], #4 /* wldrw wcgr0, [r0], #4 */
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ldc2 p1, cr9, [r0], #4 /* wldrw wcgr1, [r0], #4 */
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ldc2 p1, cr10, [r0], #4 /* wldrw wcgr2, [r0], #4 */
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ldc2 p1, cr11, [r0], #4 /* wldrw wcgr3, [r0], #4 */
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RET
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ARM_FUNC_START gnu_Unwind_Save_WMMXC
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/* Use the generic coprocessor form so that gas doesn't complain
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on non-iWMMXt targets. */
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stc2 p1, cr8, [r0], #4 /* wstrw wcgr0, [r0], #4 */
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stc2 p1, cr9, [r0], #4 /* wstrw wcgr1, [r0], #4 */
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stc2 p1, cr10, [r0], #4 /* wstrw wcgr2, [r0], #4 */
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stc2 p1, cr11, [r0], #4 /* wstrw wcgr3, [r0], #4 */
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RET
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/* Wrappers to save core registers, then call the real routine. */
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.macro UNWIND_WRAPPER name nargs
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ARM_FUNC_START \name
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/* Create a phase2_vrs structure. */
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/* Split reg push in two to ensure the correct value for sp. */
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#if defined(__thumb2__)
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mov ip, sp
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push {lr} /* PC is ignored. */
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push {ip, lr} /* Push original SP and LR. */
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#else
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stmfd sp!, {sp, lr, pc}
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#endif
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stmfd sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
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/* Demand-save flags, plus an extra word for alignment. */
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mov r3, #0
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stmfd sp!, {r2, r3}
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/* Point r1 at the block. Pass r[0..nargs) unchanged. */
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add r\nargs, sp, #4
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#if defined(__thumb__) && !defined(__thumb2__)
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/* Switch back to thumb mode to avoid interworking hassle. */
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adr ip, .L1_\name
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orr ip, ip, #1
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bx ip
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.thumb
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.L1_\name:
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bl SYM (__gnu\name) __PLT__
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ldr r3, [sp, #64]
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add sp, #72
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bx r3
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#else
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bl SYM (__gnu\name) __PLT__
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ldr lr, [sp, #64]
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add sp, sp, #72
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RET
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#endif
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FUNC_END \name
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UNPREFIX \name
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.endm
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#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */
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UNWIND_WRAPPER _Unwind_RaiseException 1
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UNWIND_WRAPPER _Unwind_Resume 1
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UNWIND_WRAPPER _Unwind_Resume_or_Rethrow 1
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UNWIND_WRAPPER _Unwind_ForcedUnwind 3
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UNWIND_WRAPPER _Unwind_Backtrace 2
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#endif /* ndef __symbian__ */
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