66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/* Machine description for AArch64 architecture.
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Copyright (C) 2012-2013 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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void
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__aarch64_sync_cache_range (const void *base, const void *end)
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{
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unsigned icache_lsize;
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unsigned dcache_lsize;
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static unsigned int cache_info = 0;
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const char *address;
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if (! cache_info)
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/* CTR_EL0 [3:0] contains log2 of icache line size in words.
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CTR_EL0 [19:16] contains log2 of dcache line size in words. */
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asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
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icache_lsize = 4 << (cache_info & 0xF);
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dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
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/* Loop over the address range, clearing one cache line at once.
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Data cache must be flushed to unification first to make sure the
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instruction cache fetches the updated data. 'end' is exclusive,
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as per the GNU definition of __clear_cache. */
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/* Make the start address of the loop cache aligned. */
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address = (const char*) ((__UINTPTR_TYPE__) base
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& ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
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for (address; address < (const char *) end; address += dcache_lsize)
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asm volatile ("dc\tcvau, %0"
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:
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: "r" (address)
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: "memory");
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asm volatile ("dsb\tish" : : : "memory");
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/* Make the start address of the loop cache aligned. */
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address = (const char*) ((__UINTPTR_TYPE__) base
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& ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
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for (address; address < (const char *) end; address += icache_lsize)
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asm volatile ("ic\tivau, %0"
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:
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: "r" (address)
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: "memory");
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asm volatile ("dsb\tish; isb" : : : "memory");
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}
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