137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
/*
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* Copyright (C) 2005-2013 Free Software Foundation, Inc.
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*
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* This file is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 3, or (at your option) any
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* later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Under Section 7 of GPL version 3, you are granted additional
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* permissions described in the GCC Runtime Library Exception, version
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* 3.1, as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License and
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* a copy of the GCC Runtime Library Exception along with this program;
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* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#define MXCSR_DAZ (1 << 6) /* Enable denormals are zero mode */
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#define MXCSR_FTZ (1 << 15) /* Enable flush to zero mode */
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#ifndef __x86_64__
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/* All 64-bit targets have SSE and DAZ;
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only check them explicitly for 32-bit ones. */
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#include "cpuid.h"
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#endif
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#if !defined __x86_64__ && defined __sun__ && defined __svr4__
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#include <signal.h>
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#include <ucontext.h>
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static volatile sig_atomic_t sigill_caught;
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static void
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sigill_hdlr (int sig __attribute((unused)),
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siginfo_t *sip __attribute__((unused)),
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ucontext_t *ucp)
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{
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sigill_caught = 1;
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/* Set PC to the instruction after the faulting one to skip over it,
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otherwise we enter an infinite loop. 3 is the size of the movaps
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instruction. */
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ucp->uc_mcontext.gregs[EIP] += 3;
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setcontext (ucp);
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}
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#endif
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static void __attribute__((constructor))
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#ifndef __x86_64__
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/* The i386 ABI only requires 4-byte stack alignment, so this is necessary
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to make sure the fxsave struct gets correct alignment.
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See PR27537 and PR28621. */
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__attribute__ ((force_align_arg_pointer))
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#endif
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set_fast_math (void)
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{
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#ifndef __x86_64__
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unsigned int eax, ebx, ecx, edx;
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if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
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return;
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if (edx & bit_SSE)
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{
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unsigned int mxcsr;
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#if defined __sun__ && defined __svr4__
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/* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions even
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if the CPU supports them. Programs receive SIGILL instead, so check
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for that at runtime. */
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struct sigaction act, oact;
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act.sa_handler = sigill_hdlr;
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sigemptyset (&act.sa_mask);
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/* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler. */
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act.sa_flags = SA_SIGINFO;
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sigaction (SIGILL, &act, &oact);
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/* We need a single SSE instruction here so the handler can safely skip
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over it. */
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__asm__ volatile ("movaps %xmm0,%xmm0");
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sigaction (SIGILL, &oact, NULL);
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if (sigill_caught)
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return;
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#endif /* __sun__ && __svr4__ */
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if (edx & bit_FXSAVE)
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{
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/* Check if DAZ is available. */
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struct
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{
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unsigned short cwd;
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unsigned short swd;
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unsigned short twd;
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unsigned short fop;
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unsigned int fip;
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unsigned int fcs;
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unsigned int foo;
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unsigned int fos;
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unsigned int mxcsr;
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unsigned int mxcsr_mask;
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unsigned int st_space[32];
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unsigned int xmm_space[32];
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unsigned int padding[56];
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} __attribute__ ((aligned (16))) fxsave;
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/* This is necessary since some implementations of FXSAVE
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do not modify reserved areas within the image. */
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fxsave.mxcsr_mask = 0;
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__builtin_ia32_fxsave (&fxsave);
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mxcsr = fxsave.mxcsr;
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if (fxsave.mxcsr_mask & MXCSR_DAZ)
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mxcsr |= MXCSR_DAZ;
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}
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else
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mxcsr = __builtin_ia32_stmxcsr ();
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mxcsr |= MXCSR_FTZ;
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__builtin_ia32_ldmxcsr (mxcsr);
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}
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#else
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unsigned int mxcsr = __builtin_ia32_stmxcsr ();
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mxcsr |= MXCSR_DAZ | MXCSR_FTZ;
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__builtin_ia32_ldmxcsr (mxcsr);
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#endif
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}
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