225 lines
9.4 KiB
C
225 lines
9.4 KiB
C
/* FreeBSD specific atomic operations for ARM EABI.
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Copyright (C) 2015-2019 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sys/types.h>
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#define HIDDEN __attribute__ ((visibility ("hidden")))
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#define ARM_VECTORS_HIGH 0xffff0000U
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#define ARM_TP_ADDRESS (ARM_VECTORS_HIGH + 0x1000)
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#define ARM_RAS_START (ARM_TP_ADDRESS + 4)
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void HIDDEN
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__sync_synchronize (void)
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{
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#if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
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|| defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6T2__) \
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|| defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) \
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|| defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
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#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
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__asm __volatile ("dmb" : : : "memory");
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#else
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__asm __volatile ("mcr p15, 0, r0, c7, c10, 5" : : : "memory");
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#endif
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#else
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__asm __volatile ("nop" : : : "memory");
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#endif
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}
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#if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
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|| defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6T2__) \
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|| defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) \
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|| defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
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/* These systems should be supported by the compiler. */
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#else /* __ARM_ARCH_5__ */
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#define SYNC_LOCK_TEST_AND_SET_N(N, TYPE, LDR, STR) \
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TYPE HIDDEN \
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__sync_lock_test_and_set_##N (TYPE *mem, TYPE val) \
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{ \
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unsigned int old, temp, ras_start; \
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\
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ras_start = ARM_RAS_START; \
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__asm volatile ( \
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/* Set up Restartable Atomic Sequence. */ \
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"1:" \
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"\tadr %2, 1b\n" \
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"\tstr %2, [%5]\n" \
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"\tadr %2, 2f\n" \
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"\tstr %2, [%5, #4]\n" \
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\
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"\t"LDR" %0, %4\n" /* Load old value. */ \
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"\t"STR" %3, %1\n" /* Store new value. */ \
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\
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/* Tear down Restartable Atomic Sequence. */ \
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"2:" \
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"\tmov %2, #0x00000000\n" \
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"\tstr %2, [%5]\n" \
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"\tmov %2, #0xffffffff\n" \
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"\tstr %2, [%5, #4]\n" \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (val), "m" (*mem), "r" (ras_start)); \
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return (old); \
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}
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#define SYNC_LOCK_RELEASE_N(N, TYPE) \
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void HIDDEN \
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__sync_lock_release_##N (TYPE *ptr) \
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{ \
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/* All writes before this point must be seen before we release \
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the lock itself. */ \
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__sync_synchronize (); \
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*ptr = 0; \
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}
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#define SYNC_VAL_CAS_N(N, TYPE, LDR, STREQ) \
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TYPE HIDDEN \
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__sync_val_compare_and_swap_##N (TYPE *mem, TYPE expected, \
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TYPE desired) \
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{ \
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unsigned int old, temp, ras_start; \
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\
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ras_start = ARM_RAS_START; \
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__asm volatile ( \
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/* Set up Restartable Atomic Sequence. */ \
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"1:" \
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"\tadr %2, 1b\n" \
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"\tstr %2, [%6]\n" \
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"\tadr %2, 2f\n" \
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"\tstr %2, [%6, #4]\n" \
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\
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"\t"LDR" %0, %5\n" /* Load old value. */ \
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"\tcmp %0, %3\n" /* Compare to expected value. */\
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"\t"STREQ" %4, %1\n" /* Store new value. */ \
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\
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/* Tear down Restartable Atomic Sequence. */ \
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"2:" \
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"\tmov %2, #0x00000000\n" \
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"\tstr %2, [%6]\n" \
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"\tmov %2, #0xffffffff\n" \
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"\tstr %2, [%6, #4]\n" \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (expected), "r" (desired), "m" (*mem), \
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"r" (ras_start)); \
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return (old); \
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}
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typedef unsigned char bool;
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#define SYNC_BOOL_CAS_N(N, TYPE) \
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bool HIDDEN \
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__sync_bool_compare_and_swap_##N (TYPE *ptr, TYPE oldval, \
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TYPE newval) \
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{ \
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TYPE actual_oldval \
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= __sync_val_compare_and_swap_##N (ptr, oldval, newval); \
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return (oldval == actual_oldval); \
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}
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#define SYNC_FETCH_AND_OP_N(N, TYPE, LDR, STR, NAME, OP) \
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TYPE HIDDEN \
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__sync_fetch_and_##NAME##_##N (TYPE *mem, TYPE val) \
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{ \
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unsigned int old, temp, ras_start; \
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\
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ras_start = ARM_RAS_START; \
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__asm volatile ( \
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/* Set up Restartable Atomic Sequence. */ \
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"1:" \
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"\tadr %2, 1b\n" \
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"\tstr %2, [%5]\n" \
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"\tadr %2, 2f\n" \
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"\tstr %2, [%5, #4]\n" \
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\
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"\t"LDR" %0, %4\n" /* Load old value. */ \
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"\t"OP" %2, %0, %3\n" /* Calculate new value. */ \
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"\t"STR" %2, %1\n" /* Store new value. */ \
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\
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/* Tear down Restartable Atomic Sequence. */ \
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"2:" \
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"\tmov %2, #0x00000000\n" \
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"\tstr %2, [%5]\n" \
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"\tmov %2, #0xffffffff\n" \
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"\tstr %2, [%5, #4]\n" \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (val), "m" (*mem), "r" (ras_start)); \
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return (old); \
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}
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#define SYNC_OP_AND_FETCH_N(N, TYPE, LDR, STR, NAME, OP) \
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TYPE HIDDEN \
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__sync_##NAME##_and_fetch_##N (TYPE *mem, TYPE val) \
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{ \
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unsigned int old, temp, ras_start, res; \
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\
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ras_start = ARM_RAS_START; \
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__asm volatile ( \
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/* Set up Restartable Atomic Sequence. */ \
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"1:" \
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"\tadr %2, 1b\n" \
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"\tstr %2, [%6]\n" \
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"\tadr %2, 2f\n" \
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"\tstr %2, [%6, #4]\n" \
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\
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"\t"LDR" %0, %5\n" /* Load old value. */ \
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"\t"OP" %3, %0, %4\n" /* Calculate new value. */ \
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"\t"STR" %3, %1\n" /* Store new value. */ \
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\
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/* Tear down Restartable Atomic Sequence. */ \
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"2:" \
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"\tmov %2, #0x00000000\n" \
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"\tstr %2, [%6]\n" \
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"\tmov %2, #0xffffffff\n" \
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"\tstr %2, [%6, #4]\n" \
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: "=&r" (old), "=m" (*mem), "=&r" (temp), "=&r" (res) \
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: "r" (val), "m" (*mem), "r" (ras_start)); \
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return (res); \
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}
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#define EMIT_ALL_OPS_N(N, TYPE, LDR, STR, STREQ) \
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SYNC_LOCK_TEST_AND_SET_N (N, TYPE, LDR, STR) \
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SYNC_LOCK_RELEASE_N (N, TYPE) \
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SYNC_VAL_CAS_N (N, TYPE, LDR, STREQ) \
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SYNC_BOOL_CAS_N (N, TYPE) \
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SYNC_FETCH_AND_OP_N (N, TYPE, LDR, STR, add, "add") \
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SYNC_FETCH_AND_OP_N (N, TYPE, LDR, STR, and, "and") \
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SYNC_FETCH_AND_OP_N (N, TYPE, LDR, STR, or, "orr") \
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SYNC_FETCH_AND_OP_N (N, TYPE, LDR, STR, sub, "sub") \
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SYNC_FETCH_AND_OP_N (N, TYPE, LDR, STR, xor, "eor") \
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SYNC_OP_AND_FETCH_N (N, TYPE, LDR, STR, add, "add") \
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SYNC_OP_AND_FETCH_N (N, TYPE, LDR, STR, and, "and") \
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SYNC_OP_AND_FETCH_N (N, TYPE, LDR, STR, or, "orr") \
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SYNC_OP_AND_FETCH_N (N, TYPE, LDR, STR, sub, "sub") \
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SYNC_OP_AND_FETCH_N (N, TYPE, LDR, STR, xor, "eor")
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EMIT_ALL_OPS_N (1, unsigned char, "ldrb", "strb", "streqb")
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EMIT_ALL_OPS_N (2, unsigned short, "ldrh", "strh", "streqh")
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EMIT_ALL_OPS_N (4, unsigned int, "ldr", "str", "streq")
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#endif
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