gcc/liboffloadmic/doc/doxygen/header.tex

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{\Large Intel\textsuperscript{\textregistered} Offload Runtime Library }\\
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{\large Generated by Doxygen $doxygenversion }\\
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{\small $datetime }\\
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{\bf FTC Optimization Notice}

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optimizations that are not unique to Intel microprocessors. These optimizations include SSE2,
SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the
availability, functionality, or effectiveness of any optimization on microprocessors not
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Microprocessor-dependent optimizations in this product are intended for use with Intel
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Intel microprocessors. Please refer to the applicable product User and Reference Guides for
more information regarding the specific instruction sets covered by this notice.

Notice revision \#20110804

\vspace*{0.5cm}

{\bf Trademarks}

Intel, Xeon, and Intel Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries.

This document is Copyright \textcopyright 2014, Intel Corporation. All rights reserved. 

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