114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
/* Copyright (C) 2012-2019 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@redhat.com>.
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This file is part of the GNU Atomic Library (libatomic).
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Libatomic is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libatomic is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#if HAVE_IFUNC
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#include <cpuid.h>
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#ifdef __x86_64__
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# define FEAT1_REGISTER ecx
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#else
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# define FEAT1_REGISTER edx
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#endif
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/* Value of the CPUID feature register FEAT1_REGISTER for the cmpxchg
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bit for IFUNC_COND1 below. */
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extern unsigned int __libat_feat1 HIDDEN;
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/* Initialize libat_feat1 and return its value. */
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unsigned int __libat_feat1_init (void) HIDDEN;
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/* Return the value of the relevant feature register for the relevant
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cmpxchg bit, or 0 if there is no CPUID support. */
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static inline unsigned int
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__attribute__ ((const))
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load_feat1 (void)
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{
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/* See the store in __libat_feat1_init. */
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unsigned int feat1 = __atomic_load_n (&__libat_feat1, __ATOMIC_RELAXED);
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if (feat1 == 0)
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/* Assume that initialization has not happened yet. This may get
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called repeatedly if the CPU does not have any feature bits at
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all. */
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feat1 = __libat_feat1_init ();
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return feat1;
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}
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#ifdef __x86_64__
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# define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG16B)
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#else
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# define IFUNC_COND_1 (load_feat1 () & bit_CMPXCHG8B)
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#endif
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#ifdef __x86_64__
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# define IFUNC_NCOND(N) (N == 16)
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#else
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# define IFUNC_NCOND(N) (N == 8)
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#endif
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#ifdef __x86_64__
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# undef MAYBE_HAVE_ATOMIC_CAS_16
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# define MAYBE_HAVE_ATOMIC_CAS_16 IFUNC_COND_1
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# undef MAYBE_HAVE_ATOMIC_EXCHANGE_16
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# define MAYBE_HAVE_ATOMIC_EXCHANGE_16 IFUNC_COND_1
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# undef MAYBE_HAVE_ATOMIC_LDST_16
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# define MAYBE_HAVE_ATOMIC_LDST_16 IFUNC_COND_1
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/* Since load and store are implemented with CAS, they are not fast. */
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# undef FAST_ATOMIC_LDST_16
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# define FAST_ATOMIC_LDST_16 0
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# if IFUNC_ALT == 1
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# undef HAVE_ATOMIC_CAS_16
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# define HAVE_ATOMIC_CAS_16 1
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# endif
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#else
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# undef MAYBE_HAVE_ATOMIC_CAS_8
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# define MAYBE_HAVE_ATOMIC_CAS_8 IFUNC_COND_1
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# undef MAYBE_HAVE_ATOMIC_EXCHANGE_8
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# define MAYBE_HAVE_ATOMIC_EXCHANGE_8 IFUNC_COND_1
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# undef MAYBE_HAVE_ATOMIC_LDST_8
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# define MAYBE_HAVE_ATOMIC_LDST_8 IFUNC_COND_1
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# if IFUNC_ALT == 1
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# undef HAVE_ATOMIC_CAS_8
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# define HAVE_ATOMIC_CAS_8 1
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# endif
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#endif
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#if defined(__x86_64__) && N == 16 && IFUNC_ALT == 1
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static inline bool
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atomic_compare_exchange_n (UTYPE *mptr, UTYPE *eptr, UTYPE newval,
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bool weak_p UNUSED, int sm UNUSED, int fm UNUSED)
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{
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UTYPE cmpval = *eptr;
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UTYPE oldval = __sync_val_compare_and_swap_16 (mptr, cmpval, newval);
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if (oldval == cmpval)
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return true;
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*eptr = oldval;
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return false;
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}
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# define atomic_compare_exchange_n atomic_compare_exchange_n
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#endif /* Have CAS 16 */
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#endif /* HAVE_IFUNC */
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#include_next <host-config.h>
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