9936155162
This patch changes the SVE FP<->FP and FP<->INT patterns so that they use unspecs rather than rtx codes, continuing the series to make the patterns work with predicates that might not be all-true. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete. * config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS) (UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New unspecs. (optab, su): Handle them. (SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators. * config/aarch64/aarch64-sve.md (<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with... (<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this. (*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with... (*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this. (*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with... (*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this. (*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with... (*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this. (vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of FIXUORS. (<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with... (<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this. (*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with... (*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this. (*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with... (*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this. (aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with... (aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this. (vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2. (vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2) (aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead of UNSPEC_FLOAT_CONVERT. (vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to aarch64_sve_extend<mode><Vwide>2. From-SVN: r274423 |
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