22c4c86949
gcc/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Tom de Vries <tom@codesourcery.com> Nathan Sidwell <nathan@codesourcery.com> Iain Sandoe <iain@codesourcery.com> Nathan Froyd <froydnj@codesourcery.com> Chao-ying Fu <fu@mips.com> * doc/extend.texi: (micromips, nomicromips, nocompression): Document new function attributes. * doc/invoke.texi (minterlink-compressed, mmicromips, m14k, m14ke, m14kec): Document new options. (minterlink-mips16): Update documentation. * doc/md.texi (ZC, ZD): Document new constraints. * configure.ac (gcc_cv_as_micromips): Check if linker supports the .set micromips directive. * configure: Regenerate. * config.in: Regenerate. * config/mips/mips-tables.opt: Regenerate. * config/mips/micromips.md: New file. * constraints.md (ZC, ZD): New constraints. * config/mips/predicates.md (movep_src_register): New predicate. (movep_src_operand): New predicate. (non_volatile_mem_operand): New predicate. * config/mips/mips.md (multimem): New type. (length): Differentiate between 17-bit and 18-bit branch offsets. (MOVEP1, MOVEP2): New mode iterator. (mov_<load>l): Use ZC constraint. (mov_<load>r): Likewise. (mov_<store>l): Likewise. (mov_<store>r): Likewise. (*branch_equality<mode>_inverted): Add microMIPS support. (*branch_equality<mode>): Likewise. (*jump_absolute): Likewise. (indirect_jump_<mode>): Likewise. (tablejump_<mode>): Likewise. (<optab>_internal): Likewise. (sibcall_internal): Likewise. (sibcall_value_internal): Likewise. (prefetch): Use constraint ZD. * config/mips/mips.opt (minterlink-compressed): New option. (minterlink-mips16): Now an alias for minterlink-compressed. (mmicromips): New option. * config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint. (compare_and_swap_12): Likewise. (sync_add<mode>): Likewise. (sync_<optab>_12): Likewise. (sync_old_<optab>_12): Likewise. (sync_new_<optab>_12): Likewise. (sync_nand_12): Likewise. (sync_old_nand_12): Likewise. (sync_new_nand_12): Likewise. (sync_sub<mode>): Likewise. (sync_old_add<mode>): Likewise. (sync_old_sub<mode>): Likewise. (sync_new_add<mode>): Likewise. (sync_new_sub<mode>): Likewise. (sync_<optab><mode>): Likewise. (sync_old_<optab><mode>): Likewise. (sync_new_<optab><mode>): Likewise. (sync_nand<mode>): Likewise. (sync_old_nand<mode>): Likewise. (sync_new_nand<mode>): Likewise. (sync_lock_test_and_set<mode>): Likewise. (test_and_set_12): Likewise. (atomic_compare_and_swap<mode>): Likewise. (atomic_exchange<mode>_llsc): Likewise. (atomic_fetch_add<mode>_llsc): Likewise. * config/mips/mips-cpus.def (m14kc, m14k): New processors. * config/mips/mips-protos.h (umips_output_save_restore): New prototype. (umips_save_restore_pattern_p): Likewise. (umips_load_store_pair_p): Likewise. (umips_output_load_store_pair): Likewise. (umips_movep_target_p): Likewise. (umips_12bit_offset_address_p): Likewise. * config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. Update all uses. (mips_attribute_table): Add micromips, nomicromips and nocompression. (mips_mips16_decl_p): Delete. (mips_nomips16_decl_p): Delete. (mips_get_compress_on_flags): New function. (mips_get_compress_off_flags): New function. (mips_get_compress_mode): New function. (mips_get_compress_on_name): New function. (mips_get_compress_off_name): New function. (mips_insert_attributes): Support multiple compression types. (mips_merge_decl_attributes): Likewise. (umips_12bit_offset_address_p): New function. (mips_start_function_definition): Emit .set micromips directive. (mips_call_may_need_jalx_p): New function. (mips_function_ok_for_sibcall): Add microMIPS support. (mips_print_operand_punctuation): Support short delay slots and compact jumps. (umips_swm_mask, umips_swm_encoding): New. (umips_build_save_restore): New function. (mips_for_each_saved_gpr_and_fpr): Add microMIPS support. (was_mips16_p): Remove. (old_compression_mode): New. (mips_set_compression_mode): New function. (mips_set_current_function): Add microMIPS support. (mips_option_override): Likewise. (umips_save_restore_pattern_p): New function. (umips_output_save_restore): New function. (umips_load_store_pair_p_1): New function. (umips_load_store_pair_p): New function. (umips_output_load_store_pair_1): New function. (umips_output_load_store_pair): New function. (umips_movep_target_p) New function. (mips_prepare_pch_save): Add microMIPS support. * config/mips/mips.h (TARGET_COMPRESSION): New. (TARGET_CPU_CPP_BUILTINS): Update macro to use new compression flags and to support microMIPS. (MIPS_ISA_LEVEL_SPEC): Add m14k processors. (MIPS_ARCH_FLOAT_SPEC): Likewise. (ISA_HAS_LWXS): Include TARGET_MICROMIPS. (ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS. (ASM_SPEC): Support mmicromips and mno-micromips. (M16STORE_REG_P): New macro. (MIPS_CALL): Support TARGET_MICROMIPS. (MICROMIPS_J): New macro. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. (UMIPS_12BIT_OFFSET_P): New macro. * config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS. (MULTILIB_DIRNAMES): Likewise. libgcc/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Chao-ying Fu <fu@mips.com> * config/mips/mips16.S: Don't build for microMIPS. * config/mips/linux-unwind.h: Handle microMIPS frame. * config/mips/crtn.S (fini, init): New labels. gcc/testsuite/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * gcc.target/mips/mips.exp: Add microMIPS support. * gcc.target/mips/umips-movep-2.c: New test. * gcc.target/mips/umips-lwp-2.c: New test. * gcc.target/mips/umips-swp-5.c: New test. * gcc.target/mips/umips-constraints-1.c: New test. * gcc.target/mips/umips-lwp-3.c: New test. * gcc.target/mips/umips-swp-6.c: New test. * gcc.target/mips/umips-constraints-2.c: New test. * gcc.target/mips/umips-save-restore-1.c: New test. * gcc.target/mips/umips-lwp-4.c: New test. * gcc.target/mips/umips-swp-7.c: New test. * gcc.target/mips/umips-save-restore-2.c: New test. * gcc.target/mips/umips-lwp-swp-volatile.c: New test. * gcc.target/mips/umips-lwp-5.c: New test. * gcc.target/mips/umips-save-restore-3.c: New test. * gcc.target/mips/umips-lwp-6.c: New test. * gcc.target/mips/umips-swp-1.c: New test. * gcc.target/mips/umips-lwp-7.c: New test. * gcc.target/mips/umips-swp-2.c: New test. * gcc.target/mips/umips-lwp-8.c: New test. * gcc.target/mips/umips-swp-3.c: New test. * gcc.target/mips/umips-movep-1.c: New test. * gcc.target/mips/umips-lwp-1.c: New test. * gcc.target/mips/umips-swp-4.c: New test. Co-Authored-By: Chao-ying Fu <fu@mips.com> Co-Authored-By: Iain Sandoe <iain@codesourcery.com> Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Maciej W. Rozycki <macro@codesourcery.com> Co-Authored-By: Nathan Froyd <froydnj@codesourcery.com> Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> Co-Authored-By: Richard Sandiford <rdsandiford@googlemail.com> Co-Authored-By: Tom de Vries <tom@codesourcery.com> From-SVN: r196828
126 lines
4.2 KiB
C
126 lines
4.2 KiB
C
/* DWARF2 EH unwinding support for MIPS Linux.
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Copyright (C) 2004-2013 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef inhibit_libc
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/* Do code reading to identify a signal frame, and set the frame
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state data appropriately. See unwind-dw2.c for the structs. */
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#include <signal.h>
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#include <asm/unistd.h>
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/* The third parameter to the signal handler points to something with
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* this structure defined in asm/ucontext.h, but the name clashes with
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* struct ucontext from sys/ucontext.h so this private copy is used. */
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typedef struct _sig_ucontext {
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unsigned long uc_flags;
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struct _sig_ucontext *uc_link;
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stack_t uc_stack;
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struct sigcontext uc_mcontext;
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sigset_t uc_sigmask;
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} _sig_ucontext_t;
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#define MD_FALLBACK_FRAME_STATE_FOR mips_fallback_frame_state
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static _Unwind_Reason_Code
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mips_fallback_frame_state (struct _Unwind_Context *context,
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_Unwind_FrameState *fs)
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{
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u_int32_t *pc = (u_int32_t *) context->ra;
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struct sigcontext *sc;
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_Unwind_Ptr new_cfa, reg_offset;
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int i;
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/* A MIPS16 or microMIPS frame. Signal frames always use the standard
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ISA encoding. */
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if ((_Unwind_Ptr) pc & 3)
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return _URC_END_OF_STACK;
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/* 24021061 li v0, 0x1061 (rt_sigreturn)*/
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/* 0000000c syscall */
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/* or */
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/* 24021017 li v0, 0x1017 (sigreturn) */
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/* 0000000c syscall */
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if (pc[1] != 0x0000000c)
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return _URC_END_OF_STACK;
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#if _MIPS_SIM == _ABIO32
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if (pc[0] == (0x24020000 | __NR_sigreturn))
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{
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struct sigframe {
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u_int32_t ass[4]; /* Argument save space for o32. */
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u_int32_t trampoline[2];
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struct sigcontext sigctx;
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} *rt_ = context->cfa;
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sc = &rt_->sigctx;
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}
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else
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#endif
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if (pc[0] == (0x24020000 | __NR_rt_sigreturn))
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{
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struct rt_sigframe {
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u_int32_t ass[4]; /* Argument save space for o32. */
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u_int32_t trampoline[2];
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siginfo_t info;
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_sig_ucontext_t uc;
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} *rt_ = context->cfa;
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sc = &rt_->uc.uc_mcontext;
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}
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else
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return _URC_END_OF_STACK;
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new_cfa = (_Unwind_Ptr) sc;
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_reg = STACK_POINTER_REGNUM;
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fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
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/* On o32 Linux, the register save slots in the sigcontext are
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eight bytes. We need the lower half of each register slot,
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so slide our view of the structure back four bytes. */
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#if _MIPS_SIM == _ABIO32 && defined __MIPSEB__
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reg_offset = 4;
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#else
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reg_offset = 0;
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#endif
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for (i = 0; i < 32; i++) {
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fs->regs.reg[i].how = REG_SAVED_OFFSET;
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fs->regs.reg[i].loc.offset
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= (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa;
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}
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/* "PC & -2" points to the faulting instruction, but the unwind code
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searches for "(ADDR & -2) - 1". (See MASK_RETURN_ADDR for the source
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of the -2 mask.) Adding 2 here ensures that "(ADDR & -2) - 1" is the
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address of the second byte of the faulting instruction.
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Note that setting fs->signal_frame would not work. As the comment
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above MASK_RETURN_ADDR explains, MIPS unwinders must earch for an
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odd-valued address. */
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fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET;
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fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset
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= (_Unwind_Ptr)(sc->sc_pc) + 2 - new_cfa;
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fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
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return _URC_NO_REASON;
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}
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#endif
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