8dc2499aa6
gotools/ * Makefile.am (go_cmd_cgo_files): Add ast_go118.go (check-go-tool): Copy golang.org/x/tools directories. * Makefile.in: Regenerate. Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/384695
584 lines
14 KiB
Go
584 lines
14 KiB
Go
// Copyright 2019 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ignore
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// mkpreempt generates the asyncPreempt functions for each
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// architecture.
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package main
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import (
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"flag"
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"fmt"
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"io"
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"log"
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"os"
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"strings"
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)
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// Copied from cmd/compile/internal/ssa/gen/*Ops.go
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var regNames386 = []string{
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"AX",
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"CX",
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"DX",
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"BX",
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"SP",
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"BP",
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"SI",
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"DI",
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"X0",
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"X1",
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"X2",
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"X3",
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"X4",
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"X5",
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"X6",
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"X7",
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}
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var regNamesAMD64 = []string{
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"AX",
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"CX",
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"DX",
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"BX",
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"SP",
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"BP",
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"SI",
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"DI",
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"R8",
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"R9",
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"R10",
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"R11",
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"R12",
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"R13",
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"R14",
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"R15",
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"X0",
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"X1",
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"X2",
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"X3",
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"X4",
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"X5",
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"X6",
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"X7",
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"X8",
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"X9",
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"X10",
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"X11",
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"X12",
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"X13",
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"X14",
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"X15",
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}
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var out io.Writer
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var arches = map[string]func(){
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"386": gen386,
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"amd64": genAMD64,
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"arm": genARM,
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"arm64": genARM64,
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"mips64x": func() { genMIPS(true) },
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"mipsx": func() { genMIPS(false) },
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"ppc64x": genPPC64,
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"riscv": genRISCV,
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"riscv64": genRISCV64,
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"s390x": genS390X,
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"wasm": genWasm,
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}
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var beLe = map[string]bool{"mips64x": true, "mipsx": true, "ppc64x": true}
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func main() {
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flag.Parse()
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if flag.NArg() > 0 {
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out = os.Stdout
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for _, arch := range flag.Args() {
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gen, ok := arches[arch]
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if !ok {
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log.Fatalf("unknown arch %s", arch)
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}
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header(arch)
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gen()
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}
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return
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}
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for arch, gen := range arches {
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f, err := os.Create(fmt.Sprintf("preempt_%s.s", arch))
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if err != nil {
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log.Fatal(err)
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}
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out = f
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header(arch)
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gen()
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if err := f.Close(); err != nil {
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log.Fatal(err)
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}
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}
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}
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func header(arch string) {
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fmt.Fprintf(out, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n")
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if beLe[arch] {
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base := arch[:len(arch)-1]
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fmt.Fprintf(out, "//go:build %s || %sle\n", base, base)
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}
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fmt.Fprintf(out, "#include \"go_asm.h\"\n")
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fmt.Fprintf(out, "#include \"textflag.h\"\n\n")
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fmt.Fprintf(out, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n")
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}
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func p(f string, args ...any) {
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fmted := fmt.Sprintf(f, args...)
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fmt.Fprintf(out, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t"))
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}
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func label(l string) {
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fmt.Fprintf(out, "%s\n", l)
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}
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type layout struct {
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stack int
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regs []regPos
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sp string // stack pointer register
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}
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type regPos struct {
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pos int
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op string
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reg string
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// If this register requires special save and restore, these
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// give those operations with a %d placeholder for the stack
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// offset.
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save, restore string
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}
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func (l *layout) add(op, reg string, size int) {
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l.regs = append(l.regs, regPos{op: op, reg: reg, pos: l.stack})
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l.stack += size
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}
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func (l *layout) addSpecial(save, restore string, size int) {
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l.regs = append(l.regs, regPos{save: save, restore: restore, pos: l.stack})
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l.stack += size
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}
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func (l *layout) save() {
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for _, reg := range l.regs {
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if reg.save != "" {
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p(reg.save, reg.pos)
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} else {
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p("%s %s, %d(%s)", reg.op, reg.reg, reg.pos, l.sp)
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}
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}
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}
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func (l *layout) restore() {
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for i := len(l.regs) - 1; i >= 0; i-- {
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reg := l.regs[i]
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if reg.restore != "" {
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p(reg.restore, reg.pos)
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} else {
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p("%s %d(%s), %s", reg.op, reg.pos, l.sp, reg.reg)
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}
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}
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}
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func gen386() {
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p("PUSHFL")
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// Save general purpose registers.
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var l = layout{sp: "SP"}
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for _, reg := range regNames386 {
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if reg == "SP" || strings.HasPrefix(reg, "X") {
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continue
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}
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l.add("MOVL", reg, 4)
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}
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softfloat := "GO386_softfloat"
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// Save SSE state only if supported.
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lSSE := layout{stack: l.stack, sp: "SP"}
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for i := 0; i < 8; i++ {
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lSSE.add("MOVUPS", fmt.Sprintf("X%d", i), 16)
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}
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p("ADJSP $%d", lSSE.stack)
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p("NOP SP")
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l.save()
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p("#ifndef %s", softfloat)
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lSSE.save()
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p("#endif")
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p("CALL ·asyncPreempt2(SB)")
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p("#ifndef %s", softfloat)
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lSSE.restore()
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p("#endif")
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l.restore()
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p("ADJSP $%d", -lSSE.stack)
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p("POPFL")
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p("RET")
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}
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func genAMD64() {
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// Assign stack offsets.
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var l = layout{sp: "SP"}
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for _, reg := range regNamesAMD64 {
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if reg == "SP" || reg == "BP" {
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continue
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}
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if !strings.HasPrefix(reg, "X") {
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l.add("MOVQ", reg, 8)
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}
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}
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lSSE := layout{stack: l.stack, sp: "SP"}
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for _, reg := range regNamesAMD64 {
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if strings.HasPrefix(reg, "X") {
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lSSE.add("MOVUPS", reg, 16)
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}
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}
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// TODO: MXCSR register?
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p("PUSHQ BP")
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p("MOVQ SP, BP")
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p("// Save flags before clobbering them")
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p("PUSHFQ")
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p("// obj doesn't understand ADD/SUB on SP, but does understand ADJSP")
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p("ADJSP $%d", lSSE.stack)
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p("// But vet doesn't know ADJSP, so suppress vet stack checking")
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p("NOP SP")
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l.save()
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// Apparently, the signal handling code path in darwin kernel leaves
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// the upper bits of Y registers in a dirty state, which causes
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// many SSE operations (128-bit and narrower) become much slower.
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// Clear the upper bits to get to a clean state. See issue #37174.
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// It is safe here as Go code don't use the upper bits of Y registers.
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p("#ifdef GOOS_darwin")
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p("CMPB internal∕cpu·X86+const_offsetX86HasAVX(SB), $0")
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p("JE 2(PC)")
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p("VZEROUPPER")
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p("#endif")
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lSSE.save()
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p("CALL ·asyncPreempt2(SB)")
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lSSE.restore()
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l.restore()
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p("ADJSP $%d", -lSSE.stack)
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p("POPFQ")
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p("POPQ BP")
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p("RET")
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}
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func genARM() {
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// Add integer registers R0-R12.
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// R13 (SP), R14 (LR), R15 (PC) are special and not saved here.
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var l = layout{sp: "R13", stack: 4} // add LR slot
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for i := 0; i <= 12; i++ {
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reg := fmt.Sprintf("R%d", i)
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if i == 10 {
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continue // R10 is g register, no need to save/restore
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}
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l.add("MOVW", reg, 4)
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}
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// Add flag register.
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l.addSpecial(
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"MOVW CPSR, R0\nMOVW R0, %d(R13)",
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"MOVW %d(R13), R0\nMOVW R0, CPSR",
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4)
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// Add floating point registers F0-F15 and flag register.
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var lfp = layout{stack: l.stack, sp: "R13"}
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lfp.addSpecial(
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"MOVW FPCR, R0\nMOVW R0, %d(R13)",
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"MOVW %d(R13), R0\nMOVW R0, FPCR",
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4)
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for i := 0; i <= 15; i++ {
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reg := fmt.Sprintf("F%d", i)
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lfp.add("MOVD", reg, 8)
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}
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p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR
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l.save()
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p("MOVB ·goarm(SB), R0\nCMP $6, R0\nBLT nofp") // test goarm, and skip FP registers if goarm=5.
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lfp.save()
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label("nofp:")
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p("CALL ·asyncPreempt2(SB)")
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p("MOVB ·goarm(SB), R0\nCMP $6, R0\nBLT nofp2") // test goarm, and skip FP registers if goarm=5.
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lfp.restore()
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label("nofp2:")
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l.restore()
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p("MOVW %d(R13), R14", lfp.stack) // sigctxt.pushCall pushes LR on stack, restore it
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p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
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p("UNDEF") // shouldn't get here
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}
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func genARM64() {
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// Add integer registers R0-R26
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// R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
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// and not saved here.
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var l = layout{sp: "RSP", stack: 8} // add slot to save PC of interrupted instruction
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for i := 0; i <= 26; i++ {
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if i == 18 {
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continue // R18 is not used, skip
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}
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reg := fmt.Sprintf("R%d", i)
|
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l.add("MOVD", reg, 8)
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}
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// Add flag registers.
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l.addSpecial(
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"MOVD NZCV, R0\nMOVD R0, %d(RSP)",
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"MOVD %d(RSP), R0\nMOVD R0, NZCV",
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8)
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l.addSpecial(
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"MOVD FPSR, R0\nMOVD R0, %d(RSP)",
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"MOVD %d(RSP), R0\nMOVD R0, FPSR",
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8)
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// TODO: FPCR? I don't think we'll change it, so no need to save.
|
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// Add floating point registers F0-F31.
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for i := 0; i <= 31; i++ {
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reg := fmt.Sprintf("F%d", i)
|
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l.add("FMOVD", reg, 8)
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}
|
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if l.stack%16 != 0 {
|
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l.stack += 8 // SP needs 16-byte alignment
|
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}
|
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|
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// allocate frame, save PC of interrupted instruction (in LR)
|
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p("MOVD R30, %d(RSP)", -l.stack)
|
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p("SUB $%d, RSP", l.stack)
|
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p("#ifdef GOOS_linux")
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p("MOVD R29, -8(RSP)") // save frame pointer (only used on Linux)
|
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p("SUB $8, RSP, R29") // set up new frame pointer
|
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p("#endif")
|
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// On iOS, save the LR again after decrementing SP. We run the
|
||
// signal handler on the G stack (as it doesn't support sigaltstack),
|
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// so any writes below SP may be clobbered.
|
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p("#ifdef GOOS_ios")
|
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p("MOVD R30, (RSP)")
|
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p("#endif")
|
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|
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l.save()
|
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p("CALL ·asyncPreempt2(SB)")
|
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l.restore()
|
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|
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p("MOVD %d(RSP), R30", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
|
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p("#ifdef GOOS_linux")
|
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p("MOVD -8(RSP), R29") // restore frame pointer
|
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p("#endif")
|
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p("MOVD (RSP), R27") // load PC to REGTMP
|
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p("ADD $%d, RSP", l.stack+16) // pop frame (including the space pushed by sigctxt.pushCall)
|
||
p("JMP (R27)")
|
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}
|
||
|
||
func genMIPS(_64bit bool) {
|
||
mov := "MOVW"
|
||
movf := "MOVF"
|
||
add := "ADD"
|
||
sub := "SUB"
|
||
r28 := "R28"
|
||
regsize := 4
|
||
softfloat := "GOMIPS_softfloat"
|
||
if _64bit {
|
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mov = "MOVV"
|
||
movf = "MOVD"
|
||
add = "ADDV"
|
||
sub = "SUBV"
|
||
r28 = "RSB"
|
||
regsize = 8
|
||
softfloat = "GOMIPS64_softfloat"
|
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}
|
||
|
||
// Add integer registers R1-R22, R24-R25, R28
|
||
// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,
|
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// and not saved here. R26 and R27 are reserved by kernel and not used.
|
||
var l = layout{sp: "R29", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
|
||
for i := 1; i <= 25; i++ {
|
||
if i == 23 {
|
||
continue // R23 is REGTMP
|
||
}
|
||
reg := fmt.Sprintf("R%d", i)
|
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l.add(mov, reg, regsize)
|
||
}
|
||
l.add(mov, r28, regsize)
|
||
l.addSpecial(
|
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mov+" HI, R1\n"+mov+" R1, %d(R29)",
|
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mov+" %d(R29), R1\n"+mov+" R1, HI",
|
||
regsize)
|
||
l.addSpecial(
|
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mov+" LO, R1\n"+mov+" R1, %d(R29)",
|
||
mov+" %d(R29), R1\n"+mov+" R1, LO",
|
||
regsize)
|
||
|
||
// Add floating point control/status register FCR31 (FCR0-FCR30 are irrelevant)
|
||
var lfp = layout{sp: "R29", stack: l.stack}
|
||
lfp.addSpecial(
|
||
mov+" FCR31, R1\n"+mov+" R1, %d(R29)",
|
||
mov+" %d(R29), R1\n"+mov+" R1, FCR31",
|
||
regsize)
|
||
// Add floating point registers F0-F31.
|
||
for i := 0; i <= 31; i++ {
|
||
reg := fmt.Sprintf("F%d", i)
|
||
lfp.add(movf, reg, regsize)
|
||
}
|
||
|
||
// allocate frame, save PC of interrupted instruction (in LR)
|
||
p(mov+" R31, -%d(R29)", lfp.stack)
|
||
p(sub+" $%d, R29", lfp.stack)
|
||
|
||
l.save()
|
||
p("#ifndef %s", softfloat)
|
||
lfp.save()
|
||
p("#endif")
|
||
p("CALL ·asyncPreempt2(SB)")
|
||
p("#ifndef %s", softfloat)
|
||
lfp.restore()
|
||
p("#endif")
|
||
l.restore()
|
||
|
||
p(mov+" %d(R29), R31", lfp.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
|
||
p(mov + " (R29), R23") // load PC to REGTMP
|
||
p(add+" $%d, R29", lfp.stack+regsize) // pop frame (including the space pushed by sigctxt.pushCall)
|
||
p("JMP (R23)")
|
||
}
|
||
|
||
func genPPC64() {
|
||
// Add integer registers R3-R29
|
||
// R0 (zero), R1 (SP), R30 (g) are special and not saved here.
|
||
// R2 (TOC pointer in PIC mode), R12 (function entry address in PIC mode) have been saved in sigctxt.pushCall.
|
||
// R31 (REGTMP) will be saved manually.
|
||
var l = layout{sp: "R1", stack: 32 + 8} // MinFrameSize on PPC64, plus one word for saving R31
|
||
for i := 3; i <= 29; i++ {
|
||
if i == 12 || i == 13 {
|
||
// R12 has been saved in sigctxt.pushCall.
|
||
// R13 is TLS pointer, not used by Go code. we must NOT
|
||
// restore it, otherwise if we parked and resumed on a
|
||
// different thread we'll mess up TLS addresses.
|
||
continue
|
||
}
|
||
reg := fmt.Sprintf("R%d", i)
|
||
l.add("MOVD", reg, 8)
|
||
}
|
||
l.addSpecial(
|
||
"MOVW CR, R31\nMOVW R31, %d(R1)",
|
||
"MOVW %d(R1), R31\nMOVFL R31, $0xff", // this is MOVW R31, CR
|
||
8) // CR is 4-byte wide, but just keep the alignment
|
||
l.addSpecial(
|
||
"MOVD XER, R31\nMOVD R31, %d(R1)",
|
||
"MOVD %d(R1), R31\nMOVD R31, XER",
|
||
8)
|
||
// Add floating point registers F0-F31.
|
||
for i := 0; i <= 31; i++ {
|
||
reg := fmt.Sprintf("F%d", i)
|
||
l.add("FMOVD", reg, 8)
|
||
}
|
||
// Add floating point control/status register FPSCR.
|
||
l.addSpecial(
|
||
"MOVFL FPSCR, F0\nFMOVD F0, %d(R1)",
|
||
"FMOVD %d(R1), F0\nMOVFL F0, FPSCR",
|
||
8)
|
||
|
||
p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR
|
||
p("MOVD LR, R31")
|
||
p("MOVDU R31, -%d(R1)", l.stack) // allocate frame, save PC of interrupted instruction (in LR)
|
||
|
||
l.save()
|
||
p("CALL ·asyncPreempt2(SB)")
|
||
l.restore()
|
||
|
||
p("MOVD %d(R1), R31", l.stack) // sigctxt.pushCall has pushed LR, R2, R12 (at interrupt) on stack, restore them
|
||
p("MOVD R31, LR")
|
||
p("MOVD %d(R1), R2", l.stack+8)
|
||
p("MOVD %d(R1), R12", l.stack+16)
|
||
p("MOVD (R1), R31") // load PC to CTR
|
||
p("MOVD R31, CTR")
|
||
p("MOVD 32(R1), R31") // restore R31
|
||
p("ADD $%d, R1", l.stack+32) // pop frame (including the space pushed by sigctxt.pushCall)
|
||
p("JMP (CTR)")
|
||
}
|
||
|
||
func genRISCV() {
|
||
p("// No async preemption on riscv - see issue 36711")
|
||
p("UNDEF")
|
||
}
|
||
|
||
func genRISCV64() {
|
||
// X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X27 (g), X31 (TMP) are special.
|
||
var l = layout{sp: "X2", stack: 8}
|
||
|
||
// Add integer registers (X5-X26, X28-30).
|
||
for i := 5; i < 31; i++ {
|
||
if i == 27 {
|
||
continue
|
||
}
|
||
reg := fmt.Sprintf("X%d", i)
|
||
l.add("MOV", reg, 8)
|
||
}
|
||
|
||
// Add floating point registers (F0-F31).
|
||
for i := 0; i <= 31; i++ {
|
||
reg := fmt.Sprintf("F%d", i)
|
||
l.add("MOVD", reg, 8)
|
||
}
|
||
|
||
p("MOV X1, -%d(X2)", l.stack)
|
||
p("ADD $-%d, X2", l.stack)
|
||
l.save()
|
||
p("CALL ·asyncPreempt2(SB)")
|
||
l.restore()
|
||
p("MOV %d(X2), X1", l.stack)
|
||
p("MOV (X2), X31")
|
||
p("ADD $%d, X2", l.stack+8)
|
||
p("JMP (X31)")
|
||
}
|
||
|
||
func genS390X() {
|
||
// Add integer registers R0-R12
|
||
// R13 (g), R14 (LR), R15 (SP) are special, and not saved here.
|
||
// Saving R10 (REGTMP) is not necessary, but it is saved anyway.
|
||
var l = layout{sp: "R15", stack: 16} // add slot to save PC of interrupted instruction and flags
|
||
l.addSpecial(
|
||
"STMG R0, R12, %d(R15)",
|
||
"LMG %d(R15), R0, R12",
|
||
13*8)
|
||
// Add floating point registers F0-F31.
|
||
for i := 0; i <= 15; i++ {
|
||
reg := fmt.Sprintf("F%d", i)
|
||
l.add("FMOVD", reg, 8)
|
||
}
|
||
|
||
// allocate frame, save PC of interrupted instruction (in LR) and flags (condition code)
|
||
p("IPM R10") // save flags upfront, as ADD will clobber flags
|
||
p("MOVD R14, -%d(R15)", l.stack)
|
||
p("ADD $-%d, R15", l.stack)
|
||
p("MOVW R10, 8(R15)") // save flags
|
||
|
||
l.save()
|
||
p("CALL ·asyncPreempt2(SB)")
|
||
l.restore()
|
||
|
||
p("MOVD %d(R15), R14", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
|
||
p("ADD $%d, R15", l.stack+8) // pop frame (including the space pushed by sigctxt.pushCall)
|
||
p("MOVWZ -%d(R15), R10", l.stack) // load flags to REGTMP
|
||
p("TMLH R10, $(3<<12)") // restore flags
|
||
p("MOVD -%d(R15), R10", l.stack+8) // load PC to REGTMP
|
||
p("JMP (R10)")
|
||
}
|
||
|
||
func genWasm() {
|
||
p("// No async preemption on wasm")
|
||
p("UNDEF")
|
||
}
|
||
|
||
func notImplemented() {
|
||
p("// Not implemented yet")
|
||
p("JMP ·abort(SB)")
|
||
}
|