132 lines
4.2 KiB
ArmAsm
132 lines
4.2 KiB
ArmAsm
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
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Copyright (C) 2012-2020 Free Software Foundation, Inc.
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Contributed by Andes Technology Corporation.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
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.align 1
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.weak _SDA_BASE_ /* For reset handler only. */
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.weak _FP_BASE_ /* For reset handler only. */
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.weak _nds32_init_mem /* User defined memory initialization function. */
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.globl _start
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.globl _nds32_reset_4b
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.type _nds32_reset_4b, @function
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_nds32_reset_4b:
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_start:
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#ifdef NDS32_EXT_EX9
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.no_ex9_begin
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#endif
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/* Handle NMI and warm boot if any of them exists. */
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beqz $sp, 1f /* Reset, NMI or warm boot? */
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/* Either NMI or warm boot; save all regs. */
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/* Preserve registers for context-switching. */
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#ifdef __NDS32_REDUCED_REGS__
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/* For 16-reg mode. */
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smw.adm $r0, [$sp], $r10, #0x0
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smw.adm $r15, [$sp], $r15, #0xf
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#else
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/* For 32-reg mode. */
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smw.adm $r0, [$sp], $r27, #0xf
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#endif
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#ifdef NDS32_EXT_IFC
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mfusr $r1, $IFC_LP
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smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
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stack 8-byte alignment. */
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#endif
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la $gp, _SDA_BASE_ /* Init GP for small data access. */
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move $r0, $sp /* Init parameter. */
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mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */
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andi $r1, $r1, #0xf
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addi $r1, $r1, #-1
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beqz $r1, 2f /* Warm boot if true. */
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l.w $r15, _nds32_nmih /* Load NMI handler. */
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j 3f
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2:
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l.w $r15, _nds32_wrh /* Load warm boot handler. */
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3:
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beqz $r15, 1f /* If no handler, do cold boot. */
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jral $r15 /* Call handler. */
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bnez $r0, 1f /* If fail to resume, do cold boot. */
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/* Restore registers for context-switching. */
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#ifdef NDS32_EXT_IFC
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lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
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stack 8-byte alignment. */
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mtusr $r1, $IFC_LP
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#endif
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#ifdef __NDS32_REDUCED_REGS__
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/* For 16-reg mode. */
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lmw.bim $r15, [$sp], $r15, #0xf
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lmw.bim $r0, [$sp], $r10, #0x0
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#else
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/* For 32-reg mode. */
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lmw.bim $r0, [$sp], $r27, #0xf
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#endif
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iret /* Resume operation. */
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1: /* Cold boot. */
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/* With vector ID feature, set default vector size to 4B. */
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/* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
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mfsr $r0, $IVB
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li $r1, #0xc000
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or $r0, $r0, $r1
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xor $r0, $r0, $r1
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mtsr $r0, $IVB
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dsb
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la $gp, _SDA_BASE_ /* Init $gp. */
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la $fp, _FP_BASE_ /* Init $fp. */
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la $sp, _stack /* Init $sp. */
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#ifdef NDS32_EXT_EX9
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/*
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* Initialize the table base of EX9 instruction
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* ex9 generation needs to disable before the ITB is set
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*/
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mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
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srli $r0, $r0, 24
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andi $r0, $r0, 0x1
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beqz $r0, 4f /* Zero means HW does not support EX9. */
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la $r0, _ITB_BASE_ /* Init $ITB. */
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mtusr $r0, $ITB
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.no_ex9_end
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4:
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#endif
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la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
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may written by C language. */
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beqz $r15, 6f
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jral $r15
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6:
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l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
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jral $r15
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/* Reset handler() should never return in a RTOS or non-OS system.
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In case it does return, an exception will be generated.
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This exception will be caught either by default break handler or by EDM.
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Default break handle may just do an infinite loop.
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EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
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5:
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break #0x7fff
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.size _nds32_reset_4b, .-_nds32_reset_4b
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