133 lines
4.1 KiB
ArmAsm
133 lines
4.1 KiB
ArmAsm
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
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Copyright (C) 2012-2016 Free Software Foundation, Inc.
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Contributed by Andes Technology Corporation.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "save_mac_regs.inc"
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#include "save_fpu_regs.inc"
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#include "save_fpu_regs_00.inc"
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#include "save_fpu_regs_01.inc"
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#include "save_fpu_regs_02.inc"
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#include "save_fpu_regs_03.inc"
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#include "save_all.inc"
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#include "save_partial.inc"
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#include "adj_intr_lvl.inc"
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#include "restore_mac_regs.inc"
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#include "restore_fpu_regs_00.inc"
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#include "restore_fpu_regs_01.inc"
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#include "restore_fpu_regs_02.inc"
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#include "restore_fpu_regs_03.inc"
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#include "restore_fpu_regs.inc"
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#include "restore_all.inc"
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#include "restore_partial.inc"
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.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
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.align 1
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/*
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First Level Handlers
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1. First Level Handlers are invokded in vector section via jump instruction
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with specific names for different configurations.
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2. Naming Format: _nds32_e_SR_NT for exception handlers.
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_nds32_i_SR_NT for interrupt handlers.
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2.1 All upper case letters are replaced with specific lower case letters encodings.
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2.2 SR: Saved Registers
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sa: Save All regs (context)
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ps: Partial Save (all caller-saved regs)
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2.3 NT: Nested Type
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ns: nested
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nn: not nested
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nr: nested ready
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*/
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/*
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This is original 16-byte vector size version.
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*/
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#ifdef NDS32_SAVE_ALL_REGS
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#if defined(NDS32_NESTED)
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.globl _nds32_i_sa_ns
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.type _nds32_i_sa_ns, @function
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_nds32_i_sa_ns:
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#elif defined(NDS32_NESTED_READY)
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.globl _nds32_i_sa_nr
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.type _nds32_i_sa_nr, @function
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_nds32_i_sa_nr:
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#else /* Not nested handler. */
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.globl _nds32_i_sa_nn
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.type _nds32_i_sa_nn, @function
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_nds32_i_sa_nn:
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#endif /* endif for Nest Type */
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#else /* not NDS32_SAVE_ALL_REGS */
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#if defined(NDS32_NESTED)
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.globl _nds32_i_ps_ns
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.type _nds32_i_ps_ns, @function
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_nds32_i_ps_ns:
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#elif defined(NDS32_NESTED_READY)
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.globl _nds32_i_ps_nr
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.type _nds32_i_ps_nr, @function
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_nds32_i_ps_nr:
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#else /* Not nested handler. */
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.globl _nds32_i_ps_nn
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.type _nds32_i_ps_nn, @function
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_nds32_i_ps_nn:
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#endif /* endif for Nest Type */
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#endif /* not NDS32_SAVE_ALL_REGS */
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/*
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This is 16-byte vector size version.
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The vector id was restored into $r0 in vector by compiler.
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*/
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#ifdef NDS32_SAVE_ALL_REGS
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SAVE_ALL
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#else
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SAVE_PARTIAL
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#endif
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/* Prepare to call 2nd level handler. */
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la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
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lw $r2, [$r2 + $r0 << #2]
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ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
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jral $r2
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/* Restore used registers. */
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#ifdef NDS32_SAVE_ALL_REGS
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RESTORE_ALL
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#else
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RESTORE_PARTIAL
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#endif
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iret
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#ifdef NDS32_SAVE_ALL_REGS
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#if defined(NDS32_NESTED)
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.size _nds32_i_sa_ns, .-_nds32_i_sa_ns
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#elif defined(NDS32_NESTED_READY)
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.size _nds32_i_sa_nr, .-_nds32_i_sa_nr
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#else /* Not nested handler. */
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.size _nds32_i_sa_nn, .-_nds32_i_sa_nn
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#endif /* endif for Nest Type */
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#else /* not NDS32_SAVE_ALL_REGS */
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#if defined(NDS32_NESTED)
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.size _nds32_i_ps_ns, .-_nds32_i_ps_ns
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#elif defined(NDS32_NESTED_READY)
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.size _nds32_i_ps_nr, .-_nds32_i_ps_nr
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#else /* Not nested handler. */
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.size _nds32_i_ps_nn, .-_nds32_i_ps_nn
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#endif /* endif for Nest Type */
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#endif /* not NDS32_SAVE_ALL_REGS */
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