356 lines
11 KiB
C
356 lines
11 KiB
C
/* Linux-specific atomic operations for PA Linux.
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Copyright (C) 2008-2016 Free Software Foundation, Inc.
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Based on code contributed by CodeSourcery for ARM EABI Linux.
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Modifications for PA Linux by Helge Deller <deller@gmx.de>
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#define EFAULT 14
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#define EBUSY 16
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#define ENOSYS 251
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/* All PA-RISC implementations supported by linux have strongly
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ordered loads and stores. Only cache flushes and purges can be
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delayed. The data cache implementations are all globally
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coherent. Thus, there is no need to synchonize memory accesses.
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GCC automatically issues a asm memory barrier when it encounters
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a __sync_synchronize builtin. Thus, we do not need to define this
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builtin.
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We implement byte, short and int versions of each atomic operation
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using the kernel helper defined below. There is no support for
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64-bit operations yet. */
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/* Determine kernel LWS function call (0=32-bit, 1=64-bit userspace). */
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#define LWS_CAS (sizeof(long) == 4 ? 0 : 1)
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/* Kernel helper for compare-and-exchange a 32-bit value. */
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static inline long
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__kernel_cmpxchg (int *mem, int oldval, int newval)
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{
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register unsigned long lws_mem asm("r26") = (unsigned long) (mem);
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register int lws_old asm("r25") = oldval;
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register int lws_new asm("r24") = newval;
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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asm volatile ( "ble 0xb0(%%sr2, %%r0) \n\t"
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"ldi %2, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno)
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: "i" (LWS_CAS), "r" (lws_mem), "r" (lws_old), "r" (lws_new)
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: "r1", "r20", "r22", "r23", "r29", "r31", "memory"
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);
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if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
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__builtin_trap ();
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/* If the kernel LWS call succeeded (lws_errno == 0), lws_ret contains
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the old value from memory. If this value is equal to OLDVAL, the
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new value was written to memory. If not, return -EBUSY. */
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if (!lws_errno && lws_ret != oldval)
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lws_errno = -EBUSY;
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return lws_errno;
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}
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static inline long
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__kernel_cmpxchg2 (void *mem, const void *oldval, const void *newval,
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int val_size)
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{
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register unsigned long lws_mem asm("r26") = (unsigned long) (mem);
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register unsigned long lws_old asm("r25") = (unsigned long) oldval;
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register unsigned long lws_new asm("r24") = (unsigned long) newval;
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register int lws_size asm("r23") = val_size;
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register long lws_ret asm("r28");
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register long lws_errno asm("r21");
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asm volatile ( "ble 0xb0(%%sr2, %%r0) \n\t"
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"ldi %6, %%r20 \n\t"
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: "=r" (lws_ret), "=r" (lws_errno), "+r" (lws_mem),
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"+r" (lws_old), "+r" (lws_new), "+r" (lws_size)
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: "i" (2)
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: "r1", "r20", "r22", "r29", "r31", "fr4", "memory"
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);
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/* If the kernel LWS call is successful, lws_ret contains 0. */
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if (__builtin_expect (lws_ret == 0, 1))
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return 0;
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if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0))
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__builtin_trap ();
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/* If the kernel LWS call fails with no error, return -EBUSY */
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if (__builtin_expect (!lws_errno, 0))
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return -EBUSY;
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return lws_errno;
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}
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#define HIDDEN __attribute__ ((visibility ("hidden")))
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/* Big endian masks */
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#define INVERT_MASK_1 24
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#define INVERT_MASK_2 16
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#define MASK_1 0xffu
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#define MASK_2 0xffffu
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#define FETCH_AND_OP_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX) \
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TYPE HIDDEN \
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__sync_fetch_and_##OP##_##WIDTH (TYPE *ptr, TYPE val) \
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{ \
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TYPE tmp, newval; \
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long failure; \
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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newval = PFX_OP (tmp INF_OP val); \
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
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} while (failure != 0); \
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\
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return tmp; \
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}
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FETCH_AND_OP_2 (add, , +, long long, 8, 3)
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FETCH_AND_OP_2 (sub, , -, long long, 8, 3)
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FETCH_AND_OP_2 (or, , |, long long, 8, 3)
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FETCH_AND_OP_2 (and, , &, long long, 8, 3)
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FETCH_AND_OP_2 (xor, , ^, long long, 8, 3)
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FETCH_AND_OP_2 (nand, ~, &, long long, 8, 3)
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FETCH_AND_OP_2 (add, , +, short, 2, 1)
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FETCH_AND_OP_2 (sub, , -, short, 2, 1)
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FETCH_AND_OP_2 (or, , |, short, 2, 1)
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FETCH_AND_OP_2 (and, , &, short, 2, 1)
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FETCH_AND_OP_2 (xor, , ^, short, 2, 1)
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FETCH_AND_OP_2 (nand, ~, &, short, 2, 1)
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FETCH_AND_OP_2 (add, , +, signed char, 1, 0)
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FETCH_AND_OP_2 (sub, , -, signed char, 1, 0)
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FETCH_AND_OP_2 (or, , |, signed char, 1, 0)
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FETCH_AND_OP_2 (and, , &, signed char, 1, 0)
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FETCH_AND_OP_2 (xor, , ^, signed char, 1, 0)
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FETCH_AND_OP_2 (nand, ~, &, signed char, 1, 0)
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#define OP_AND_FETCH_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX) \
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TYPE HIDDEN \
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__sync_##OP##_and_fetch_##WIDTH (TYPE *ptr, TYPE val) \
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{ \
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TYPE tmp, newval; \
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long failure; \
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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newval = PFX_OP (tmp INF_OP val); \
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failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX); \
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} while (failure != 0); \
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\
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return PFX_OP (tmp INF_OP val); \
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}
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OP_AND_FETCH_2 (add, , +, long long, 8, 3)
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OP_AND_FETCH_2 (sub, , -, long long, 8, 3)
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OP_AND_FETCH_2 (or, , |, long long, 8, 3)
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OP_AND_FETCH_2 (and, , &, long long, 8, 3)
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OP_AND_FETCH_2 (xor, , ^, long long, 8, 3)
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OP_AND_FETCH_2 (nand, ~, &, long long, 8, 3)
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OP_AND_FETCH_2 (add, , +, short, 2, 1)
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OP_AND_FETCH_2 (sub, , -, short, 2, 1)
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OP_AND_FETCH_2 (or, , |, short, 2, 1)
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OP_AND_FETCH_2 (and, , &, short, 2, 1)
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OP_AND_FETCH_2 (xor, , ^, short, 2, 1)
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OP_AND_FETCH_2 (nand, ~, &, short, 2, 1)
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OP_AND_FETCH_2 (add, , +, signed char, 1, 0)
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OP_AND_FETCH_2 (sub, , -, signed char, 1, 0)
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OP_AND_FETCH_2 (or, , |, signed char, 1, 0)
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OP_AND_FETCH_2 (and, , &, signed char, 1, 0)
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OP_AND_FETCH_2 (xor, , ^, signed char, 1, 0)
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OP_AND_FETCH_2 (nand, ~, &, signed char, 1, 0)
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#define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \
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int HIDDEN \
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__sync_fetch_and_##OP##_4 (int *ptr, int val) \
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{ \
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int tmp; \
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long failure; \
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
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} while (failure != 0); \
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\
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return tmp; \
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}
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FETCH_AND_OP_WORD (add, , +)
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FETCH_AND_OP_WORD (sub, , -)
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FETCH_AND_OP_WORD (or, , |)
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FETCH_AND_OP_WORD (and, , &)
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FETCH_AND_OP_WORD (xor, , ^)
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FETCH_AND_OP_WORD (nand, ~, &)
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#define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \
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int HIDDEN \
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__sync_##OP##_and_fetch_4 (int *ptr, int val) \
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{ \
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int tmp; \
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long failure; \
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\
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do { \
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tmp = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val)); \
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} while (failure != 0); \
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\
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return PFX_OP (tmp INF_OP val); \
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}
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OP_AND_FETCH_WORD (add, , +)
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OP_AND_FETCH_WORD (sub, , -)
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OP_AND_FETCH_WORD (or, , |)
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OP_AND_FETCH_WORD (and, , &)
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OP_AND_FETCH_WORD (xor, , ^)
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OP_AND_FETCH_WORD (nand, ~, &)
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typedef unsigned char bool;
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#define COMPARE_AND_SWAP_2(TYPE, WIDTH, INDEX) \
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TYPE HIDDEN \
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__sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
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TYPE newval) \
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{ \
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TYPE actual_oldval; \
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long fail; \
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\
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while (1) \
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{ \
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actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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\
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if (__builtin_expect (oldval != actual_oldval, 0)) \
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return actual_oldval; \
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\
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fail = __kernel_cmpxchg2 (ptr, &actual_oldval, &newval, INDEX); \
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\
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if (__builtin_expect (!fail, 1)) \
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return actual_oldval; \
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} \
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} \
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\
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bool HIDDEN \
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__sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \
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TYPE newval) \
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{ \
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long failure = __kernel_cmpxchg2 (ptr, &oldval, &newval, INDEX); \
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return (failure == 0); \
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}
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COMPARE_AND_SWAP_2 (long long, 8, 3)
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COMPARE_AND_SWAP_2 (short, 2, 1)
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COMPARE_AND_SWAP_2 (char, 1, 0)
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int HIDDEN
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__sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval)
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{
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long fail;
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int actual_oldval;
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while (1)
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{
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actual_oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
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if (__builtin_expect (oldval != actual_oldval, 0))
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return actual_oldval;
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fail = __kernel_cmpxchg (ptr, actual_oldval, newval);
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if (__builtin_expect (!fail, 1))
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return actual_oldval;
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}
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}
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bool HIDDEN
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__sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval)
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{
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long failure = __kernel_cmpxchg (ptr, oldval, newval);
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return (failure == 0);
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}
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#define SYNC_LOCK_TEST_AND_SET_2(TYPE, WIDTH, INDEX) \
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TYPE HIDDEN \
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__sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \
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{ \
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TYPE oldval; \
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long failure; \
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\
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do { \
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg2 (ptr, &oldval, &val, INDEX); \
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} while (failure != 0); \
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\
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return oldval; \
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}
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SYNC_LOCK_TEST_AND_SET_2 (long long, 8, 3)
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SYNC_LOCK_TEST_AND_SET_2 (short, 2, 1)
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SYNC_LOCK_TEST_AND_SET_2 (signed char, 1, 0)
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int HIDDEN
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__sync_lock_test_and_set_4 (int *ptr, int val)
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{
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long failure;
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int oldval;
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do {
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
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failure = __kernel_cmpxchg (ptr, oldval, val);
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} while (failure != 0);
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return oldval;
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}
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#define SYNC_LOCK_RELEASE_2(TYPE, WIDTH, INDEX) \
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void HIDDEN \
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__sync_lock_release_##WIDTH (TYPE *ptr) \
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{ \
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TYPE oldval, zero = 0; \
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long failure; \
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\
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do { \
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST); \
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failure = __kernel_cmpxchg2 (ptr, &oldval, &zero, INDEX); \
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} while (failure != 0); \
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}
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SYNC_LOCK_RELEASE_2 (long long, 8, 3)
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SYNC_LOCK_RELEASE_2 (short, 2, 1)
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SYNC_LOCK_RELEASE_2 (signed char, 1, 0)
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void HIDDEN
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__sync_lock_release_4 (int *ptr)
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{
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long failure;
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int oldval;
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do {
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oldval = __atomic_load_n (ptr, __ATOMIC_SEQ_CST);
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failure = __kernel_cmpxchg (ptr, oldval, 0);
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} while (failure != 0);
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}
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