845 lines
18 KiB
ArmAsm
845 lines
18 KiB
ArmAsm
/* Assembly functions for the Xtensa version of libgcc1.
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Copyright (C) 2001-2020 Free Software Foundation, Inc.
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Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "xtensa-config.h"
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/* Define macros for the ABS and ADDX* instructions to handle cases
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where they are not included in the Xtensa processor configuration. */
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.macro do_abs dst, src, tmp
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#if XCHAL_HAVE_ABS
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abs \dst, \src
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#else
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neg \tmp, \src
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movgez \tmp, \src, \src
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mov \dst, \tmp
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#endif
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.endm
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.macro do_addx2 dst, as, at, tmp
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#if XCHAL_HAVE_ADDX
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addx2 \dst, \as, \at
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#else
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slli \tmp, \as, 1
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add \dst, \tmp, \at
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#endif
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.endm
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.macro do_addx4 dst, as, at, tmp
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#if XCHAL_HAVE_ADDX
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addx4 \dst, \as, \at
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#else
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slli \tmp, \as, 2
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add \dst, \tmp, \at
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#endif
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.endm
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.macro do_addx8 dst, as, at, tmp
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#if XCHAL_HAVE_ADDX
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addx8 \dst, \as, \at
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#else
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slli \tmp, \as, 3
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add \dst, \tmp, \at
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#endif
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.endm
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/* Define macros for leaf function entry and return, supporting either the
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standard register windowed ABI or the non-windowed call0 ABI. These
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macros do not allocate any extra stack space, so they only work for
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leaf functions that do not need to spill anything to the stack. */
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.macro leaf_entry reg, size
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#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
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entry \reg, \size
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#else
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/* do nothing */
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#endif
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.endm
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.macro leaf_return
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#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
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retw
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#else
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ret
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#endif
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.endm
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#ifdef L_mulsi3
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.align 4
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.global __mulsi3
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.type __mulsi3, @function
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__mulsi3:
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leaf_entry sp, 16
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#if XCHAL_HAVE_MUL32
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mull a2, a2, a3
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#elif XCHAL_HAVE_MUL16
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or a4, a2, a3
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srai a4, a4, 16
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bnez a4, .LMUL16
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mul16u a2, a2, a3
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leaf_return
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.LMUL16:
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srai a4, a2, 16
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srai a5, a3, 16
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mul16u a7, a4, a3
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mul16u a6, a5, a2
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mul16u a4, a2, a3
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add a7, a7, a6
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slli a7, a7, 16
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add a2, a7, a4
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#elif XCHAL_HAVE_MAC16
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mul.aa.hl a2, a3
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mula.aa.lh a2, a3
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rsr a5, ACCLO
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umul.aa.ll a2, a3
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rsr a4, ACCLO
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slli a5, a5, 16
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add a2, a4, a5
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#else /* !MUL32 && !MUL16 && !MAC16 */
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/* Multiply one bit at a time, but unroll the loop 4x to better
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exploit the addx instructions and avoid overhead.
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Peel the first iteration to save a cycle on init. */
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/* Avoid negative numbers. */
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xor a5, a2, a3 /* Top bit is 1 if one input is negative. */
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do_abs a3, a3, a6
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do_abs a2, a2, a6
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/* Swap so the second argument is smaller. */
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sub a7, a2, a3
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mov a4, a3
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movgez a4, a2, a7 /* a4 = max (a2, a3) */
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movltz a3, a2, a7 /* a3 = min (a2, a3) */
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movi a2, 0
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extui a6, a3, 0, 1
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movnez a2, a4, a6
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do_addx2 a7, a4, a2, a7
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extui a6, a3, 1, 1
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movnez a2, a7, a6
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do_addx4 a7, a4, a2, a7
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extui a6, a3, 2, 1
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movnez a2, a7, a6
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do_addx8 a7, a4, a2, a7
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extui a6, a3, 3, 1
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movnez a2, a7, a6
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bgeui a3, 16, .Lmult_main_loop
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neg a3, a2
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movltz a2, a3, a5
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leaf_return
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.align 4
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.Lmult_main_loop:
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srli a3, a3, 4
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slli a4, a4, 4
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add a7, a4, a2
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extui a6, a3, 0, 1
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movnez a2, a7, a6
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do_addx2 a7, a4, a2, a7
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extui a6, a3, 1, 1
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movnez a2, a7, a6
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do_addx4 a7, a4, a2, a7
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extui a6, a3, 2, 1
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movnez a2, a7, a6
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do_addx8 a7, a4, a2, a7
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extui a6, a3, 3, 1
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movnez a2, a7, a6
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bgeui a3, 16, .Lmult_main_loop
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neg a3, a2
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movltz a2, a3, a5
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#endif /* !MUL32 && !MUL16 && !MAC16 */
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leaf_return
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.size __mulsi3, . - __mulsi3
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#endif /* L_mulsi3 */
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#ifdef L_umulsidi3
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#if !XCHAL_HAVE_MUL16 && !XCHAL_HAVE_MUL32 && !XCHAL_HAVE_MAC16
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#define XCHAL_NO_MUL 1
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#endif
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.align 4
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.global __umulsidi3
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.type __umulsidi3, @function
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__umulsidi3:
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#if __XTENSA_CALL0_ABI__
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leaf_entry sp, 32
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addi sp, sp, -32
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s32i a12, sp, 16
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s32i a13, sp, 20
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s32i a14, sp, 24
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s32i a15, sp, 28
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#elif XCHAL_NO_MUL
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/* This is not really a leaf function; allocate enough stack space
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to allow CALL12s to a helper function. */
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leaf_entry sp, 48
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#else
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leaf_entry sp, 16
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#endif
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#ifdef __XTENSA_EB__
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#define wh a2
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#define wl a3
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#else
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#define wh a3
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#define wl a2
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#endif /* __XTENSA_EB__ */
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/* This code is taken from the mulsf3 routine in ieee754-sf.S.
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See more comments there. */
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#if XCHAL_HAVE_MUL32_HIGH
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mull a6, a2, a3
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muluh wh, a2, a3
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mov wl, a6
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#else /* ! MUL32_HIGH */
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#if __XTENSA_CALL0_ABI__ && XCHAL_NO_MUL
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/* a0 and a8 will be clobbered by calling the multiply function
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but a8 is not used here and need not be saved. */
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s32i a0, sp, 0
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#endif
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#if XCHAL_HAVE_MUL16 || XCHAL_HAVE_MUL32
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#define a2h a4
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#define a3h a5
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/* Get the high halves of the inputs into registers. */
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srli a2h, a2, 16
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srli a3h, a3, 16
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#define a2l a2
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#define a3l a3
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#if XCHAL_HAVE_MUL32 && !XCHAL_HAVE_MUL16
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/* Clear the high halves of the inputs. This does not matter
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for MUL16 because the high bits are ignored. */
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extui a2, a2, 0, 16
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extui a3, a3, 0, 16
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#endif
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#endif /* MUL16 || MUL32 */
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#if XCHAL_HAVE_MUL16
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#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
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mul16u dst, xreg ## xhalf, yreg ## yhalf
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#elif XCHAL_HAVE_MUL32
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#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
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mull dst, xreg ## xhalf, yreg ## yhalf
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#elif XCHAL_HAVE_MAC16
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/* The preprocessor insists on inserting a space when concatenating after
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a period in the definition of do_mul below. These macros are a workaround
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using underscores instead of periods when doing the concatenation. */
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#define umul_aa_ll umul.aa.ll
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#define umul_aa_lh umul.aa.lh
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#define umul_aa_hl umul.aa.hl
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#define umul_aa_hh umul.aa.hh
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#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
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umul_aa_ ## xhalf ## yhalf xreg, yreg; \
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rsr dst, ACCLO
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#else /* no multiply hardware */
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#define set_arg_l(dst, src) \
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extui dst, src, 0, 16
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#define set_arg_h(dst, src) \
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srli dst, src, 16
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#if __XTENSA_CALL0_ABI__
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#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
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set_arg_ ## xhalf (a13, xreg); \
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set_arg_ ## yhalf (a14, yreg); \
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call0 .Lmul_mulsi3; \
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mov dst, a12
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#else
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#define do_mul(dst, xreg, xhalf, yreg, yhalf) \
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set_arg_ ## xhalf (a14, xreg); \
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set_arg_ ## yhalf (a15, yreg); \
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call12 .Lmul_mulsi3; \
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mov dst, a14
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#endif /* __XTENSA_CALL0_ABI__ */
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#endif /* no multiply hardware */
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/* Add pp1 and pp2 into a6 with carry-out in a9. */
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do_mul(a6, a2, l, a3, h) /* pp 1 */
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do_mul(a11, a2, h, a3, l) /* pp 2 */
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movi a9, 0
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add a6, a6, a11
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bgeu a6, a11, 1f
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addi a9, a9, 1
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1:
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/* Shift the high half of a9/a6 into position in a9. Note that
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this value can be safely incremented without any carry-outs. */
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ssai 16
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src a9, a9, a6
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/* Compute the low word into a6. */
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do_mul(a11, a2, l, a3, l) /* pp 0 */
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sll a6, a6
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add a6, a6, a11
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bgeu a6, a11, 1f
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addi a9, a9, 1
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1:
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/* Compute the high word into wh. */
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do_mul(wh, a2, h, a3, h) /* pp 3 */
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add wh, wh, a9
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mov wl, a6
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#endif /* !MUL32_HIGH */
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#if __XTENSA_CALL0_ABI__ && XCHAL_NO_MUL
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/* Restore the original return address. */
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l32i a0, sp, 0
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#endif
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#if __XTENSA_CALL0_ABI__
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l32i a12, sp, 16
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l32i a13, sp, 20
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l32i a14, sp, 24
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l32i a15, sp, 28
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addi sp, sp, 32
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#endif
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leaf_return
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#if XCHAL_NO_MUL
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/* For Xtensa processors with no multiply hardware, this simplified
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version of _mulsi3 is used for multiplying 16-bit chunks of
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the floating-point mantissas. When using CALL0, this function
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uses a custom ABI: the inputs are passed in a13 and a14, the
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result is returned in a12, and a8 and a15 are clobbered. */
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.align 4
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.Lmul_mulsi3:
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leaf_entry sp, 16
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.macro mul_mulsi3_body dst, src1, src2, tmp1, tmp2
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movi \dst, 0
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1: add \tmp1, \src2, \dst
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extui \tmp2, \src1, 0, 1
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movnez \dst, \tmp1, \tmp2
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do_addx2 \tmp1, \src2, \dst, \tmp1
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extui \tmp2, \src1, 1, 1
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movnez \dst, \tmp1, \tmp2
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do_addx4 \tmp1, \src2, \dst, \tmp1
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extui \tmp2, \src1, 2, 1
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movnez \dst, \tmp1, \tmp2
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do_addx8 \tmp1, \src2, \dst, \tmp1
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extui \tmp2, \src1, 3, 1
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movnez \dst, \tmp1, \tmp2
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srli \src1, \src1, 4
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slli \src2, \src2, 4
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bnez \src1, 1b
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.endm
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#if __XTENSA_CALL0_ABI__
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mul_mulsi3_body a12, a13, a14, a15, a8
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#else
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/* The result will be written into a2, so save that argument in a4. */
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mov a4, a2
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mul_mulsi3_body a2, a4, a3, a5, a6
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#endif
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leaf_return
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#endif /* XCHAL_NO_MUL */
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.size __umulsidi3, . - __umulsidi3
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#endif /* L_umulsidi3 */
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/* Define a macro for the NSAU (unsigned normalize shift amount)
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instruction, which computes the number of leading zero bits,
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to handle cases where it is not included in the Xtensa processor
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configuration. */
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.macro do_nsau cnt, val, tmp, a
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#if XCHAL_HAVE_NSA
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nsau \cnt, \val
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#else
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mov \a, \val
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movi \cnt, 0
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extui \tmp, \a, 16, 16
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bnez \tmp, 0f
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movi \cnt, 16
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slli \a, \a, 16
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0:
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extui \tmp, \a, 24, 8
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bnez \tmp, 1f
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addi \cnt, \cnt, 8
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slli \a, \a, 8
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1:
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movi \tmp, __nsau_data
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extui \a, \a, 24, 8
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add \tmp, \tmp, \a
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l8ui \tmp, \tmp, 0
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add \cnt, \cnt, \tmp
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#endif /* !XCHAL_HAVE_NSA */
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.endm
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#ifdef L_clz
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.section .rodata
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.align 4
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.global __nsau_data
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.type __nsau_data, @object
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__nsau_data:
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#if !XCHAL_HAVE_NSA
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.byte 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4
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.byte 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3
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.byte 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
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.byte 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
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.byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
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.byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
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.byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
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.byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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#endif /* !XCHAL_HAVE_NSA */
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.size __nsau_data, . - __nsau_data
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.hidden __nsau_data
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#endif /* L_clz */
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#ifdef L_clzsi2
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.align 4
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.global __clzsi2
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.type __clzsi2, @function
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__clzsi2:
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leaf_entry sp, 16
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do_nsau a2, a2, a3, a4
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leaf_return
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.size __clzsi2, . - __clzsi2
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#endif /* L_clzsi2 */
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#ifdef L_ctzsi2
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.align 4
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.global __ctzsi2
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.type __ctzsi2, @function
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__ctzsi2:
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leaf_entry sp, 16
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neg a3, a2
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and a3, a3, a2
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do_nsau a2, a3, a4, a5
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neg a2, a2
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addi a2, a2, 31
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leaf_return
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|
.size __ctzsi2, . - __ctzsi2
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#endif /* L_ctzsi2 */
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#ifdef L_ffssi2
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.align 4
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.global __ffssi2
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.type __ffssi2, @function
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__ffssi2:
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leaf_entry sp, 16
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neg a3, a2
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and a3, a3, a2
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do_nsau a2, a3, a4, a5
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neg a2, a2
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addi a2, a2, 32
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leaf_return
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.size __ffssi2, . - __ffssi2
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#endif /* L_ffssi2 */
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#ifdef L_udivsi3
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.align 4
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.global __udivsi3
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.type __udivsi3, @function
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__udivsi3:
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leaf_entry sp, 16
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#if XCHAL_HAVE_DIV32
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quou a2, a2, a3
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#else
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bltui a3, 2, .Lle_one /* check if the divisor <= 1 */
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mov a6, a2 /* keep dividend in a6 */
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do_nsau a5, a6, a2, a7 /* dividend_shift = nsau (dividend) */
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do_nsau a4, a3, a2, a7 /* divisor_shift = nsau (divisor) */
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bgeu a5, a4, .Lspecial
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sub a4, a4, a5 /* count = divisor_shift - dividend_shift */
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ssl a4
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sll a3, a3 /* divisor <<= count */
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movi a2, 0 /* quotient = 0 */
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/* test-subtract-and-shift loop; one quotient bit on each iteration */
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lloopend
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#endif /* XCHAL_HAVE_LOOPS */
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.Lloop:
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bltu a6, a3, .Lzerobit
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sub a6, a6, a3
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addi a2, a2, 1
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.Lzerobit:
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slli a2, a2, 1
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srli a3, a3, 1
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#if !XCHAL_HAVE_LOOPS
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addi a4, a4, -1
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bnez a4, .Lloop
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lloopend:
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bltu a6, a3, .Lreturn
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addi a2, a2, 1 /* increment quotient if dividend >= divisor */
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.Lreturn:
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leaf_return
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.Lle_one:
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beqz a3, .Lerror /* if divisor == 1, return the dividend */
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leaf_return
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.Lspecial:
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/* return dividend >= divisor */
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bltu a6, a3, .Lreturn0
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movi a2, 1
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leaf_return
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.Lerror:
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/* Divide by zero: Use an illegal instruction to force an exception.
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The subsequent "DIV0" string can be recognized by the exception
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handler to identify the real cause of the exception. */
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ill
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.ascii "DIV0"
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.Lreturn0:
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movi a2, 0
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#endif /* XCHAL_HAVE_DIV32 */
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leaf_return
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.size __udivsi3, . - __udivsi3
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#endif /* L_udivsi3 */
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#ifdef L_divsi3
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.align 4
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.global __divsi3
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.type __divsi3, @function
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__divsi3:
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leaf_entry sp, 16
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#if XCHAL_HAVE_DIV32
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quos a2, a2, a3
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#else
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xor a7, a2, a3 /* sign = dividend ^ divisor */
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do_abs a6, a2, a4 /* udividend = abs (dividend) */
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do_abs a3, a3, a4 /* udivisor = abs (divisor) */
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bltui a3, 2, .Lle_one /* check if udivisor <= 1 */
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do_nsau a5, a6, a2, a8 /* udividend_shift = nsau (udividend) */
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do_nsau a4, a3, a2, a8 /* udivisor_shift = nsau (udivisor) */
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bgeu a5, a4, .Lspecial
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sub a4, a4, a5 /* count = udivisor_shift - udividend_shift */
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ssl a4
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sll a3, a3 /* udivisor <<= count */
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movi a2, 0 /* quotient = 0 */
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/* test-subtract-and-shift loop; one quotient bit on each iteration */
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lloopend
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#endif /* XCHAL_HAVE_LOOPS */
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.Lloop:
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bltu a6, a3, .Lzerobit
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sub a6, a6, a3
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addi a2, a2, 1
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.Lzerobit:
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slli a2, a2, 1
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srli a3, a3, 1
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#if !XCHAL_HAVE_LOOPS
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addi a4, a4, -1
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bnez a4, .Lloop
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lloopend:
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bltu a6, a3, .Lreturn
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addi a2, a2, 1 /* increment if udividend >= udivisor */
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.Lreturn:
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neg a5, a2
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movltz a2, a5, a7 /* return (sign < 0) ? -quotient : quotient */
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leaf_return
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.Lle_one:
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beqz a3, .Lerror
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neg a2, a6 /* if udivisor == 1, then return... */
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movgez a2, a6, a7 /* (sign < 0) ? -udividend : udividend */
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leaf_return
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.Lspecial:
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bltu a6, a3, .Lreturn0 /* if dividend < divisor, return 0 */
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movi a2, 1
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movi a4, -1
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movltz a2, a4, a7 /* else return (sign < 0) ? -1 : 1 */
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leaf_return
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.Lerror:
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/* Divide by zero: Use an illegal instruction to force an exception.
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The subsequent "DIV0" string can be recognized by the exception
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handler to identify the real cause of the exception. */
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ill
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.ascii "DIV0"
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.Lreturn0:
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movi a2, 0
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#endif /* XCHAL_HAVE_DIV32 */
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leaf_return
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.size __divsi3, . - __divsi3
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#endif /* L_divsi3 */
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#ifdef L_umodsi3
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.align 4
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.global __umodsi3
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.type __umodsi3, @function
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__umodsi3:
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leaf_entry sp, 16
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#if XCHAL_HAVE_DIV32
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remu a2, a2, a3
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#else
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bltui a3, 2, .Lle_one /* check if the divisor is <= 1 */
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do_nsau a5, a2, a6, a7 /* dividend_shift = nsau (dividend) */
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do_nsau a4, a3, a6, a7 /* divisor_shift = nsau (divisor) */
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bgeu a5, a4, .Lspecial
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sub a4, a4, a5 /* count = divisor_shift - dividend_shift */
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ssl a4
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sll a3, a3 /* divisor <<= count */
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/* test-subtract-and-shift loop */
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lloopend
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#endif /* XCHAL_HAVE_LOOPS */
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.Lloop:
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bltu a2, a3, .Lzerobit
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sub a2, a2, a3
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.Lzerobit:
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srli a3, a3, 1
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#if !XCHAL_HAVE_LOOPS
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addi a4, a4, -1
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bnez a4, .Lloop
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lloopend:
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.Lspecial:
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bltu a2, a3, .Lreturn
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sub a2, a2, a3 /* subtract once more if dividend >= divisor */
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.Lreturn:
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leaf_return
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.Lle_one:
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bnez a3, .Lreturn0
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/* Divide by zero: Use an illegal instruction to force an exception.
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The subsequent "DIV0" string can be recognized by the exception
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handler to identify the real cause of the exception. */
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ill
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.ascii "DIV0"
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.Lreturn0:
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movi a2, 0
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#endif /* XCHAL_HAVE_DIV32 */
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leaf_return
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.size __umodsi3, . - __umodsi3
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#endif /* L_umodsi3 */
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#ifdef L_modsi3
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.align 4
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.global __modsi3
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.type __modsi3, @function
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__modsi3:
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leaf_entry sp, 16
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#if XCHAL_HAVE_DIV32
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rems a2, a2, a3
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#else
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mov a7, a2 /* save original (signed) dividend */
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do_abs a2, a2, a4 /* udividend = abs (dividend) */
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do_abs a3, a3, a4 /* udivisor = abs (divisor) */
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bltui a3, 2, .Lle_one /* check if udivisor <= 1 */
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do_nsau a5, a2, a6, a8 /* udividend_shift = nsau (udividend) */
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do_nsau a4, a3, a6, a8 /* udivisor_shift = nsau (udivisor) */
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bgeu a5, a4, .Lspecial
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sub a4, a4, a5 /* count = udivisor_shift - udividend_shift */
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ssl a4
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sll a3, a3 /* udivisor <<= count */
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/* test-subtract-and-shift loop */
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lloopend
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#endif /* XCHAL_HAVE_LOOPS */
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.Lloop:
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bltu a2, a3, .Lzerobit
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sub a2, a2, a3
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.Lzerobit:
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srli a3, a3, 1
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#if !XCHAL_HAVE_LOOPS
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addi a4, a4, -1
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bnez a4, .Lloop
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lloopend:
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.Lspecial:
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bltu a2, a3, .Lreturn
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sub a2, a2, a3 /* subtract again if udividend >= udivisor */
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.Lreturn:
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bgez a7, .Lpositive
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neg a2, a2 /* if (dividend < 0), return -udividend */
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.Lpositive:
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leaf_return
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.Lle_one:
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bnez a3, .Lreturn0
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/* Divide by zero: Use an illegal instruction to force an exception.
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The subsequent "DIV0" string can be recognized by the exception
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handler to identify the real cause of the exception. */
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ill
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.ascii "DIV0"
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.Lreturn0:
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movi a2, 0
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#endif /* XCHAL_HAVE_DIV32 */
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leaf_return
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.size __modsi3, . - __modsi3
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#endif /* L_modsi3 */
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#ifdef __XTENSA_EB__
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#define uh a2
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#define ul a3
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#else
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#define uh a3
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#define ul a2
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#endif /* __XTENSA_EB__ */
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#ifdef L_ashldi3
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.align 4
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.global __ashldi3
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.type __ashldi3, @function
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__ashldi3:
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leaf_entry sp, 16
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ssl a4
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bgei a4, 32, .Llow_only
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src uh, uh, ul
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sll ul, ul
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leaf_return
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.Llow_only:
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sll uh, ul
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movi ul, 0
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leaf_return
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.size __ashldi3, . - __ashldi3
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#endif /* L_ashldi3 */
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#ifdef L_ashrdi3
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.align 4
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.global __ashrdi3
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.type __ashrdi3, @function
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__ashrdi3:
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leaf_entry sp, 16
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ssr a4
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bgei a4, 32, .Lhigh_only
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src ul, uh, ul
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sra uh, uh
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leaf_return
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.Lhigh_only:
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sra ul, uh
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srai uh, uh, 31
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leaf_return
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.size __ashrdi3, . - __ashrdi3
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#endif /* L_ashrdi3 */
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#ifdef L_lshrdi3
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.align 4
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.global __lshrdi3
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.type __lshrdi3, @function
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__lshrdi3:
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leaf_entry sp, 16
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ssr a4
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bgei a4, 32, .Lhigh_only1
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src ul, uh, ul
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srl uh, uh
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leaf_return
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.Lhigh_only1:
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srl ul, uh
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movi uh, 0
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leaf_return
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.size __lshrdi3, . - __lshrdi3
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#endif /* L_lshrdi3 */
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#include "ieee754-df.S"
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#include "ieee754-sf.S"
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