492 lines
12 KiB
C
492 lines
12 KiB
C
/* Get CPU type and Features for x86 processors.
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Copyright (C) 2012-2016 Free Software Foundation, Inc.
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Contributed by Sriraman Tallam (tmsriram@google.com)
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "cpuid.h"
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#include "tsystem.h"
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#include "auto-target.h"
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#ifdef HAVE_INIT_PRIORITY
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#define CONSTRUCTOR_PRIORITY (101)
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#else
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#define CONSTRUCTOR_PRIORITY
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#endif
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int __cpu_indicator_init (void)
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__attribute__ ((constructor CONSTRUCTOR_PRIORITY));
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/* Processor Vendor and Models. */
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enum processor_vendor
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{
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VENDOR_INTEL = 1,
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VENDOR_AMD,
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VENDOR_OTHER,
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VENDOR_MAX
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};
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/* Any new types or subtypes have to be inserted at the end. */
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enum processor_types
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{
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INTEL_BONNELL = 1,
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INTEL_CORE2,
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INTEL_COREI7,
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AMDFAM10H,
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AMDFAM15H,
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INTEL_SILVERMONT,
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INTEL_KNL,
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AMD_BTVER1,
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AMD_BTVER2,
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AMDFAM17H,
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CPU_TYPE_MAX
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};
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enum processor_subtypes
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{
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INTEL_COREI7_NEHALEM = 1,
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INTEL_COREI7_WESTMERE,
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INTEL_COREI7_SANDYBRIDGE,
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AMDFAM10H_BARCELONA,
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AMDFAM10H_SHANGHAI,
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AMDFAM10H_ISTANBUL,
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AMDFAM15H_BDVER1,
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AMDFAM15H_BDVER2,
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AMDFAM15H_BDVER3,
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AMDFAM15H_BDVER4,
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AMDFAM17H_ZNVER1,
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INTEL_COREI7_IVYBRIDGE,
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INTEL_COREI7_HASWELL,
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INTEL_COREI7_BROADWELL,
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INTEL_COREI7_SKYLAKE,
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INTEL_COREI7_SKYLAKE_AVX512,
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CPU_SUBTYPE_MAX
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};
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/* ISA Features supported. New features have to be inserted at the end. */
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enum processor_features
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{
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FEATURE_CMOV = 0,
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FEATURE_MMX,
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FEATURE_POPCNT,
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FEATURE_SSE,
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FEATURE_SSE2,
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FEATURE_SSE3,
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FEATURE_SSSE3,
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FEATURE_SSE4_1,
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FEATURE_SSE4_2,
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FEATURE_AVX,
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FEATURE_AVX2,
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FEATURE_SSE4_A,
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FEATURE_FMA4,
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FEATURE_XOP,
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FEATURE_FMA,
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FEATURE_AVX512F,
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FEATURE_BMI,
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FEATURE_BMI2,
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FEATURE_AES,
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FEATURE_PCLMUL,
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FEATURE_AVX512VL,
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FEATURE_AVX512BW,
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FEATURE_AVX512DQ,
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FEATURE_AVX512CD,
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FEATURE_AVX512ER,
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FEATURE_AVX512PF,
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FEATURE_AVX512VBMI,
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FEATURE_AVX512IFMA
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};
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struct __processor_model
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{
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unsigned int __cpu_vendor;
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unsigned int __cpu_type;
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unsigned int __cpu_subtype;
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unsigned int __cpu_features[1];
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} __cpu_model = { };
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/* Get the specific type of AMD CPU. */
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static void
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get_amd_cpu (unsigned int family, unsigned int model)
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{
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switch (family)
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{
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/* AMD Family 10h. */
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case 0x10:
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__cpu_model.__cpu_type = AMDFAM10H;
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switch (model)
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{
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case 0x2:
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/* Barcelona. */
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__cpu_model.__cpu_subtype = AMDFAM10H_BARCELONA;
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break;
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case 0x4:
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/* Shanghai. */
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__cpu_model.__cpu_subtype = AMDFAM10H_SHANGHAI;
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break;
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case 0x8:
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/* Istanbul. */
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__cpu_model.__cpu_subtype = AMDFAM10H_ISTANBUL;
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break;
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default:
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break;
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}
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break;
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/* AMD Family 14h "btver1". */
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case 0x14:
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__cpu_model.__cpu_type = AMD_BTVER1;
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break;
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/* AMD Family 15h "Bulldozer". */
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case 0x15:
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__cpu_model.__cpu_type = AMDFAM15H;
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/* Bulldozer version 1. */
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if ( model <= 0xf)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER1;
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/* Bulldozer version 2 "Piledriver" */
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if (model >= 0x10 && model <= 0x2f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER2;
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/* Bulldozer version 3 "Steamroller" */
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if (model >= 0x30 && model <= 0x4f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER3;
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/* Bulldozer version 4 "Excavator" */
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if (model >= 0x60 && model <= 0x7f)
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__cpu_model.__cpu_subtype = AMDFAM15H_BDVER4;
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break;
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/* AMD Family 16h "btver2" */
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case 0x16:
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__cpu_model.__cpu_type = AMD_BTVER2;
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break;
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case 0x17:
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__cpu_model.__cpu_type = AMDFAM17H;
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/* AMD family 17h version 1. */
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if (model <= 0x1f)
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__cpu_model.__cpu_subtype = AMDFAM17H_ZNVER1;
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break;
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default:
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break;
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}
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}
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/* Get the specific type of Intel CPU. */
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static void
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get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
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{
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/* Parse family and model only if brand ID is 0. */
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if (brand_id == 0)
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{
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switch (family)
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{
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case 0x5:
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/* Pentium. */
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break;
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case 0x6:
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switch (model)
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{
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case 0x1c:
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case 0x26:
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/* Bonnell. */
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__cpu_model.__cpu_type = INTEL_BONNELL;
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break;
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Silvermont. */
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__cpu_model.__cpu_type = INTEL_SILVERMONT;
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break;
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case 0x57:
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/* Knights Landing. */
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__cpu_model.__cpu_type = INTEL_KNL;
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break;
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case 0x1a:
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case 0x1e:
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case 0x1f:
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case 0x2e:
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/* Nehalem. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_NEHALEM;
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break;
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case 0x25:
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case 0x2c:
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case 0x2f:
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/* Westmere. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_WESTMERE;
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break;
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case 0x2a:
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case 0x2d:
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/* Sandy Bridge. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_SANDYBRIDGE;
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break;
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case 0x3a:
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case 0x3e:
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/* Ivy Bridge. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_IVYBRIDGE;
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break;
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case 0x3c:
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case 0x3f:
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case 0x45:
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case 0x46:
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/* Haswell. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_HASWELL;
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break;
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case 0x3d:
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case 0x47:
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case 0x4f:
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case 0x56:
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/* Broadwell. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_BROADWELL;
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break;
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case 0x4e:
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case 0x5e:
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/* Skylake. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
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break;
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case 0x55:
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/* Skylake with AVX-512 support. */
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
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break;
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case 0x17:
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case 0x1d:
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/* Penryn. */
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case 0x0f:
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/* Merom. */
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__cpu_model.__cpu_type = INTEL_CORE2;
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break;
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default:
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break;
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}
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break;
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default:
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/* We have no idea. */
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break;
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}
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}
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}
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/* ECX and EDX are output of CPUID at level one. MAX_CPUID_LEVEL is
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the max possible level of CPUID insn. */
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static void
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get_available_features (unsigned int ecx, unsigned int edx,
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int max_cpuid_level)
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{
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unsigned int features = 0;
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if (edx & bit_CMOV)
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features |= (1 << FEATURE_CMOV);
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if (edx & bit_MMX)
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features |= (1 << FEATURE_MMX);
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if (edx & bit_SSE)
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features |= (1 << FEATURE_SSE);
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if (edx & bit_SSE2)
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features |= (1 << FEATURE_SSE2);
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if (ecx & bit_POPCNT)
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features |= (1 << FEATURE_POPCNT);
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if (ecx & bit_AES)
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features |= (1 << FEATURE_AES);
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if (ecx & bit_PCLMUL)
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features |= (1 << FEATURE_PCLMUL);
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if (ecx & bit_SSE3)
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features |= (1 << FEATURE_SSE3);
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if (ecx & bit_SSSE3)
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features |= (1 << FEATURE_SSSE3);
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if (ecx & bit_SSE4_1)
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features |= (1 << FEATURE_SSE4_1);
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if (ecx & bit_SSE4_2)
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features |= (1 << FEATURE_SSE4_2);
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if (ecx & bit_AVX)
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features |= (1 << FEATURE_AVX);
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if (ecx & bit_FMA)
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features |= (1 << FEATURE_FMA);
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/* Get Advanced Features at level 7 (eax = 7, ecx = 0). */
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if (max_cpuid_level >= 7)
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{
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unsigned int eax, ebx, ecx, edx;
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__cpuid_count (7, 0, eax, ebx, ecx, edx);
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if (ebx & bit_BMI)
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features |= (1 << FEATURE_BMI);
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if (ebx & bit_AVX2)
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features |= (1 << FEATURE_AVX2);
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if (ebx & bit_BMI2)
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features |= (1 << FEATURE_BMI2);
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if (ebx & bit_AVX512F)
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features |= (1 << FEATURE_AVX512F);
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if (ebx & bit_AVX512VL)
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features |= (1 << FEATURE_AVX512VL);
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if (ebx & bit_AVX512BW)
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features |= (1 << FEATURE_AVX512BW);
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if (ebx & bit_AVX512DQ)
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features |= (1 << FEATURE_AVX512DQ);
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if (ebx & bit_AVX512CD)
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features |= (1 << FEATURE_AVX512CD);
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if (ebx & bit_AVX512PF)
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features |= (1 << FEATURE_AVX512PF);
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if (ebx & bit_AVX512ER)
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features |= (1 << FEATURE_AVX512ER);
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if (ebx & bit_AVX512IFMA)
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features |= (1 << FEATURE_AVX512IFMA);
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if (ecx & bit_AVX512VBMI)
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features |= (1 << FEATURE_AVX512VBMI);
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}
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unsigned int ext_level;
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unsigned int eax, ebx;
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/* Check cpuid level of extended features. */
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__cpuid (0x80000000, ext_level, ebx, ecx, edx);
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if (ext_level > 0x80000000)
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{
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__cpuid (0x80000001, eax, ebx, ecx, edx);
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if (ecx & bit_SSE4a)
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features |= (1 << FEATURE_SSE4_A);
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if (ecx & bit_FMA4)
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features |= (1 << FEATURE_FMA4);
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if (ecx & bit_XOP)
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features |= (1 << FEATURE_XOP);
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}
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__cpu_model.__cpu_features[0] = features;
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}
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/* A noinline function calling __get_cpuid. Having many calls to
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cpuid in one function in 32-bit mode causes GCC to complain:
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"can't find a register in class CLOBBERED_REGS". This is
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related to PR rtl-optimization 44174. */
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static int __attribute__ ((noinline))
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__get_cpuid_output (unsigned int __level,
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unsigned int *__eax, unsigned int *__ebx,
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unsigned int *__ecx, unsigned int *__edx)
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{
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return __get_cpuid (__level, __eax, __ebx, __ecx, __edx);
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}
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/* A constructor function that is sets __cpu_model and __cpu_features with
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the right values. This needs to run only once. This constructor is
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given the highest priority and it should run before constructors without
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the priority set. However, it still runs after ifunc initializers and
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needs to be called explicitly there. */
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int __attribute__ ((constructor CONSTRUCTOR_PRIORITY))
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__cpu_indicator_init (void)
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{
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unsigned int eax, ebx, ecx, edx;
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int max_level = 5;
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unsigned int vendor;
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unsigned int model, family, brand_id;
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unsigned int extended_model, extended_family;
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/* This function needs to run just once. */
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if (__cpu_model.__cpu_vendor)
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return 0;
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/* Assume cpuid insn present. Run in level 0 to get vendor id. */
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if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx))
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{
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__cpu_model.__cpu_vendor = VENDOR_OTHER;
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return -1;
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}
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vendor = ebx;
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max_level = eax;
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if (max_level < 1)
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{
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__cpu_model.__cpu_vendor = VENDOR_OTHER;
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return -1;
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}
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if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx))
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{
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__cpu_model.__cpu_vendor = VENDOR_OTHER;
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return -1;
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}
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model = (eax >> 4) & 0x0f;
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family = (eax >> 8) & 0x0f;
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brand_id = ebx & 0xff;
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extended_model = (eax >> 12) & 0xf0;
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extended_family = (eax >> 20) & 0xff;
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if (vendor == signature_INTEL_ebx)
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{
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/* Adjust model and family for Intel CPUS. */
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if (family == 0x0f)
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{
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family += extended_family;
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model += extended_model;
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}
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else if (family == 0x06)
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model += extended_model;
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/* Get CPU type. */
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get_intel_cpu (family, model, brand_id);
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/* Find available features. */
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get_available_features (ecx, edx, max_level);
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__cpu_model.__cpu_vendor = VENDOR_INTEL;
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}
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else if (vendor == signature_AMD_ebx)
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{
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/* Adjust model and family for AMD CPUS. */
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if (family == 0x0f)
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{
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family += extended_family;
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model += extended_model;
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}
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/* Get CPU type. */
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get_amd_cpu (family, model);
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/* Find available features. */
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get_available_features (ecx, edx, max_level);
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__cpu_model.__cpu_vendor = VENDOR_AMD;
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}
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else
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__cpu_model.__cpu_vendor = VENDOR_OTHER;
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gcc_assert (__cpu_model.__cpu_vendor < VENDOR_MAX);
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gcc_assert (__cpu_model.__cpu_type < CPU_TYPE_MAX);
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gcc_assert (__cpu_model.__cpu_subtype < CPU_SUBTYPE_MAX);
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return 0;
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}
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#if defined SHARED && defined USE_ELF_SYMVER
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__asm__ (".symver __cpu_indicator_init, __cpu_indicator_init@GCC_4.8.0");
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__asm__ (".symver __cpu_model, __cpu_model@GCC_4.8.0");
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#endif
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