4c7726b172
* Makefile.am, acinclude.m4, configure.in: Imported GC 6.1 Alpha 1 and merged local changes. From-SVN: r46283
482 lines
18 KiB
C
482 lines
18 KiB
C
/*
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* Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
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* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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* Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
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*
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*
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* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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*
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* Permission is hereby granted to use or copy this program
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* for any purpose, provided the above notices are retained on all copies.
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* Permission to modify the code and to distribute modified code is granted,
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* provided the above notices are retained, and a notice that the code was
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* modified is included with the above copyright notice.
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*/
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#ifndef GC_LOCKS_H
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#define GC_LOCKS_H
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/*
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* Mutual exclusion between allocator/collector routines.
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* Needed if there is more than one allocator thread.
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* FASTLOCK() is assumed to try to acquire the lock in a cheap and
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* dirty way that is acceptable for a few instructions, e.g. by
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* inhibiting preemption. This is assumed to have succeeded only
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* if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
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* FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
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* If signals cannot be tolerated with the FASTLOCK held, then
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* FASTLOCK should disable signals. The code executed under
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* FASTLOCK is otherwise immune to interruption, provided it is
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* not restarted.
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* DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
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* and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
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* (There is currently no equivalent for FASTLOCK.)
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*
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* In the PARALLEL_MARK case, we also need to define a number of
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* other inline finctions here:
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* GC_bool GC_compare_and_exchange( volatile GC_word *addr,
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* GC_word old, GC_word new )
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* GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
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* void GC_memory_barrier( )
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*
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*/
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# ifdef THREADS
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void GC_noop1 GC_PROTO((word));
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# ifdef PCR_OBSOLETE /* Faster, but broken with multiple lwp's */
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# include "th/PCR_Th.h"
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# include "th/PCR_ThCrSec.h"
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extern struct PCR_Th_MLRep GC_allocate_ml;
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# define DCL_LOCK_STATE PCR_sigset_t GC_old_sig_mask
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# define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
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# define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
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# define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
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# define FASTLOCK() PCR_ThCrSec_EnterSys()
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/* Here we cheat (a lot): */
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# define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
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/* TRUE if nobody currently holds the lock */
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# define FASTUNLOCK() PCR_ThCrSec_ExitSys()
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# endif
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# ifdef PCR
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# include <base/PCR_Base.h>
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# include <th/PCR_Th.h>
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extern PCR_Th_ML GC_allocate_ml;
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# define DCL_LOCK_STATE \
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PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
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# define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
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# define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
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# define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
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# define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
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# define FASTUNLOCK() {\
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if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
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# endif
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# ifdef SRC_M3
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extern GC_word RT0u__inCritical;
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# define LOCK() RT0u__inCritical++
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# define UNLOCK() RT0u__inCritical--
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# endif
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# ifdef GC_SOLARIS_THREADS
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# include <thread.h>
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# include <signal.h>
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extern mutex_t GC_allocate_ml;
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# define LOCK() mutex_lock(&GC_allocate_ml);
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# define UNLOCK() mutex_unlock(&GC_allocate_ml);
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# endif
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/* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock */
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/* acquisition and release. We need this for correct operation of the */
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/* incremental GC. */
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# ifdef __GNUC__
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# if defined(I386)
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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int oldval;
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/* Note: the "xchg" instruction does not need a "lock" prefix */
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__asm__ __volatile__("xchgl %0, %1"
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: "=r"(oldval), "=m"(*(addr))
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: "0"(1), "m"(*(addr)) : "memory");
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return oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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# endif
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# if defined(IA64)
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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long oldval, n = 1;
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__asm__ __volatile__("xchg4 %0=%1,%2"
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: "=r"(oldval), "=m"(*addr)
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: "r"(n), "1"(*addr) : "memory");
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return oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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/* Should this handle post-increment addressing?? */
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inline static void GC_clear(volatile unsigned int *addr) {
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__asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
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}
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# define GC_CLEAR_DEFINED
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# endif
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# ifdef SPARC
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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int oldval;
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__asm__ __volatile__("ldstub %1,%0"
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: "=r"(oldval), "=m"(*addr)
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: "m"(*addr) : "memory");
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return oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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# endif
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# ifdef M68K
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/* Contributed by Tony Mantler. I'm not sure how well it was */
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/* tested. */
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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char oldval; /* this must be no longer than 8 bits */
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/* The return value is semi-phony. */
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/* 'tas' sets bit 7 while the return */
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/* value pretends bit 0 was set */
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__asm__ __volatile__(
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"tas %1@; sne %0; negb %0"
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: "=d" (oldval)
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: "a" (addr) : "memory");
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return oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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# endif
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# if defined(POWERPC)
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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int oldval;
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int temp = 1; // locked value
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__asm__ __volatile__(
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"1:\tlwarx %0,0,%3\n" // load and reserve
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"\tcmpwi %0, 0\n" // if load is
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"\tbne 2f\n" // non-zero, return already set
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"\tstwcx. %2,0,%1\n" // else store conditional
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"\tbne- 1b\n" // retry if lost reservation
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"2:\t\n" // oldval is zero if we set
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: "=&r"(oldval), "=p"(addr)
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: "r"(temp), "1"(addr)
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: "memory");
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return (int)oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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inline static void GC_clear(volatile unsigned int *addr) {
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__asm__ __volatile__("eieio" ::: "memory");
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*(addr) = 0;
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}
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# define GC_CLEAR_DEFINED
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# endif
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# if defined(ALPHA)
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inline static int GC_test_and_set(volatile unsigned int * addr)
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{
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unsigned long oldvalue;
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unsigned long temp;
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__asm__ __volatile__(
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"1: ldl_l %0,%1\n"
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" and %0,%3,%2\n"
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" bne %2,2f\n"
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" xor %0,%3,%0\n"
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" stl_c %0,%1\n"
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" beq %0,3f\n"
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" mb\n"
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"2:\n"
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".section .text2,\"ax\"\n"
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"3: br 1b\n"
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".previous"
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:"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
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:"Ir" (1), "m" (*addr)
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:"memory");
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return oldvalue;
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}
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# define GC_TEST_AND_SET_DEFINED
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/* Should probably also define GC_clear, since it needs */
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/* a memory barrier ?? */
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# endif /* ALPHA */
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# ifdef ARM32
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inline static int GC_test_and_set(volatile unsigned int *addr) {
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int oldval;
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/* SWP on ARM is very similar to XCHG on x86. Doesn't lock the
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* bus because there are no SMP ARM machines. If/when there are,
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* this code will likely need to be updated. */
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/* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
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__asm__ __volatile__("swp %0, %1, [%2]"
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: "=r"(oldval)
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: "r"(1), "r"(addr)
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: "memory");
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return oldval;
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}
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# define GC_TEST_AND_SET_DEFINED
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# endif /* ARM32 */
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# endif /* __GNUC__ */
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# if (defined(ALPHA) && !defined(__GNUC__))
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# define GC_test_and_set(addr) __cxx_test_and_set_atomic(addr, 1)
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# define GC_TEST_AND_SET_DEFINED
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# endif
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# if defined(MSWIN32)
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# define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
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# define GC_TEST_AND_SET_DEFINED
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# endif
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# ifdef MIPS
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# if __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
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|| !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
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# define GC_test_and_set(addr, v) test_and_set(addr,v)
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# else
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# define GC_test_and_set(addr, v) __test_and_set(addr,v)
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# define GC_clear(addr) __lock_release(addr);
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# define GC_CLEAR_DEFINED
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# endif
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# define GC_TEST_AND_SET_DEFINED
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# endif /* MIPS */
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# if 0 /* defined(HP_PA) */
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/* The official recommendation seems to be to not use ldcw from */
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/* user mode. Since multithreaded incremental collection doesn't */
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/* work anyway on HP_PA, this shouldn't be a major loss. */
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/* "set" means 0 and "clear" means 1 here. */
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# define GC_test_and_set(addr) !GC_test_and_clear(addr);
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# define GC_TEST_AND_SET_DEFINED
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# define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
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/* The above needs a memory barrier! */
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# define GC_CLEAR_DEFINED
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# endif
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# if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
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# ifdef __GNUC__
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inline static void GC_clear(volatile unsigned int *addr) {
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/* Try to discourage gcc from moving anything past this. */
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__asm__ __volatile__(" " : : : "memory");
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*(addr) = 0;
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}
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# else
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/* The function call in the following should prevent the */
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/* compiler from moving assignments to below the UNLOCK. */
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# define GC_clear(addr) GC_noop1((word)(addr)); \
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*((volatile unsigned int *)(addr)) = 0;
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# endif
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# define GC_CLEAR_DEFINED
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# endif /* !GC_CLEAR_DEFINED */
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# if !defined(GC_TEST_AND_SET_DEFINED)
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# define USE_PTHREAD_LOCKS
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# endif
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# if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
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&& !defined(GC_IRIX_THREADS)
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# define NO_THREAD (pthread_t)(-1)
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# include <pthread.h>
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# if defined(PARALLEL_MARK)
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/* We need compare-and-swap to update mark bits, where it's */
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/* performance critical. If USE_MARK_BYTES is defined, it is */
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/* no longer needed for this purpose. However we use it in */
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/* either case to implement atomic fetch-and-add, though that's */
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/* less performance critical, and could perhaps be done with */
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/* a lock. */
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# if defined(GENERIC_COMPARE_AND_SWAP)
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/* Probably not useful, except for debugging. */
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/* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we */
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/* minimize its use. */
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extern pthread_mutex_t GC_compare_and_swap_lock;
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/* Note that if GC_word updates are not atomic, a concurrent */
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/* reader should acquire GC_compare_and_swap_lock. On */
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/* currently supported platforms, such updates are atomic. */
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extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
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GC_word old, GC_word new_val);
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# endif /* GENERIC_COMPARE_AND_SWAP */
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# if defined(I386)
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# if !defined(GENERIC_COMPARE_AND_SWAP)
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/* Returns TRUE if the comparison succeeded. */
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inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
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GC_word old,
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GC_word new_val)
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{
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char result;
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__asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
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: "=m"(*(addr)), "=r"(result)
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: "r" (new_val), "0"(*(addr)), "a"(old) : "memory");
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return (GC_bool) result;
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}
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# endif /* !GENERIC_COMPARE_AND_SWAP */
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inline static void GC_memory_write_barrier()
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{
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/* We believe the processor ensures at least processor */
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/* consistent ordering. Thus a compiler barrier */
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/* should suffice. */
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__asm__ __volatile__("" : : : "memory");
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}
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# endif /* I386 */
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# if defined(IA64)
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# if !defined(GENERIC_COMPARE_AND_SWAP)
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inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
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GC_word old, GC_word new_val)
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{
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unsigned long oldval;
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__asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.rel %0=%1,%2,ar.ccv"
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: "=r"(oldval), "=m"(*addr)
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: "r"(new_val), "1"(*addr), "r"(old) : "memory");
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return (oldval == old);
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}
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# endif /* !GENERIC_COMPARE_AND_SWAP */
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# if 0
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/* Shouldn't be needed; we use volatile stores instead. */
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inline static void GC_memory_write_barrier()
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{
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__asm__ __volatile__("mf" : : : "memory");
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}
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# endif /* 0 */
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# endif /* IA64 */
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# if !defined(GENERIC_COMPARE_AND_SWAP)
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/* Returns the original value of *addr. */
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inline static GC_word GC_atomic_add(volatile GC_word *addr,
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GC_word how_much)
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{
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GC_word old;
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do {
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old = *addr;
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} while (!GC_compare_and_exchange(addr, old, old+how_much));
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return old;
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}
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# else /* GENERIC_COMPARE_AND_SWAP */
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/* So long as a GC_word can be atomically updated, it should */
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/* be OK to read *addr without a lock. */
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extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
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# endif /* GENERIC_COMPARE_AND_SWAP */
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# endif /* PARALLEL_MARK */
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# if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
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/* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
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/* be held for long periods, if it is held at all. Thus spinning */
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/* and sleeping for fixed periods are likely to result in */
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/* significant wasted time. We thus rely mostly on queued locks. */
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# define USE_SPIN_LOCK
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extern volatile unsigned int GC_allocate_lock;
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extern void GC_lock(void);
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/* Allocation lock holder. Only set if acquired by client through */
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/* GC_call_with_alloc_lock. */
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# ifdef GC_ASSERTIONS
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# define LOCK() \
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{ if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
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SET_LOCK_HOLDER(); }
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# define UNLOCK() \
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{ GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
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GC_clear(&GC_allocate_lock); }
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# else
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# define LOCK() \
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{ if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
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# define UNLOCK() \
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GC_clear(&GC_allocate_lock)
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# endif /* !GC_ASSERTIONS */
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# if 0
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/* Another alternative for OSF1 might be: */
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# include <sys/mman.h>
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extern msemaphore GC_allocate_semaphore;
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# define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
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!= 0) GC_lock(); else GC_allocate_lock = 1; }
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/* The following is INCORRECT, since the memory model is too weak. */
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/* Is this true? Presumably msem_unlock has the right semantics? */
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/* - HB */
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# define UNLOCK() { GC_allocate_lock = 0; \
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msem_unlock(&GC_allocate_semaphore, 0); }
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# endif /* 0 */
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# else /* THREAD_LOCAL_ALLOC || USE_PTHREAD_LOCKS */
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# ifndef USE_PTHREAD_LOCKS
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# define USE_PTHREAD_LOCKS
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# endif
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# endif /* THREAD_LOCAL_ALLOC */
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# ifdef USE_PTHREAD_LOCKS
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# include <pthread.h>
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extern pthread_mutex_t GC_allocate_ml;
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# ifdef GC_ASSERTIONS
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# define LOCK() \
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{ GC_lock(); \
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SET_LOCK_HOLDER(); }
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# define UNLOCK() \
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{ GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
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pthread_mutex_unlock(&GC_allocate_ml); }
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# else /* !GC_ASSERTIONS */
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# define LOCK() \
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{ if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
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# define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
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# endif /* !GC_ASSERTIONS */
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# endif /* USE_PTHREAD_LOCKS */
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# define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
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# define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
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# define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
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extern VOLATILE GC_bool GC_collecting;
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# define ENTER_GC() GC_collecting = 1;
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# define EXIT_GC() GC_collecting = 0;
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extern void GC_lock(void);
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extern pthread_t GC_lock_holder;
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# ifdef GC_ASSERTIONS
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extern pthread_t GC_mark_lock_holder;
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# endif
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# endif /* GC_PTHREADS with linux_threads.c implementation */
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# if defined(GC_IRIX_THREADS)
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# include <pthread.h>
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/* This probably should never be included, but I can't test */
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/* on Irix anymore. */
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# include <mutex.h>
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extern unsigned long GC_allocate_lock;
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/* This is not a mutex because mutexes that obey the (optional) */
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/* POSIX scheduling rules are subject to convoys in high contention */
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/* applications. This is basically a spin lock. */
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extern pthread_t GC_lock_holder;
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extern void GC_lock(void);
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/* Allocation lock holder. Only set if acquired by client through */
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/* GC_call_with_alloc_lock. */
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# define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
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# define NO_THREAD (pthread_t)(-1)
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# define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
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# define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
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# define LOCK() { if (GC_test_and_set(&GC_allocate_lock, 1)) GC_lock(); }
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# define UNLOCK() GC_clear(&GC_allocate_lock);
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extern VOLATILE GC_bool GC_collecting;
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# define ENTER_GC() \
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{ \
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GC_collecting = 1; \
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}
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# define EXIT_GC() GC_collecting = 0;
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# endif /* GC_IRIX_THREADS */
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# ifdef GC_WIN32_THREADS
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# include <windows.h>
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GC_API CRITICAL_SECTION GC_allocate_ml;
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# define LOCK() EnterCriticalSection(&GC_allocate_ml);
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# define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
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# endif
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# ifndef SET_LOCK_HOLDER
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|
# define SET_LOCK_HOLDER()
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# define UNSET_LOCK_HOLDER()
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# define I_HOLD_LOCK() FALSE
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|
/* Used on platforms were locks can be reacquired, */
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|
/* so it doesn't matter if we lie. */
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# endif
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# else /* !THREADS */
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# define LOCK()
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|
# define UNLOCK()
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|
# endif /* !THREADS */
|
|
# ifndef SET_LOCK_HOLDER
|
|
# define SET_LOCK_HOLDER()
|
|
# define UNSET_LOCK_HOLDER()
|
|
# define I_HOLD_LOCK() FALSE
|
|
/* Used on platforms were locks can be reacquired, */
|
|
/* so it doesn't matter if we lie. */
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|
# endif
|
|
# ifndef ENTER_GC
|
|
# define ENTER_GC()
|
|
# define EXIT_GC()
|
|
# endif
|
|
|
|
# ifndef DCL_LOCK_STATE
|
|
# define DCL_LOCK_STATE
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|
# endif
|
|
# ifndef FASTLOCK
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|
# define FASTLOCK() LOCK()
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|
# define FASTLOCK_SUCCEEDED() TRUE
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|
# define FASTUNLOCK() UNLOCK()
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# endif
|
|
|
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#endif /* GC_LOCKS_H */
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