c2047754c3
Compiler changes:
* Change map assignment to use mapassign and assign value directly.
* Change string iteration to use decoderune, faster for ASCII strings.
* Change makeslice to take int, and use makeslice64 for larger values.
* Add new noverflow field to hmap struct used for maps.
Unresolved problems, to be fixed later:
* Commented out test in go/types/sizes_test.go that doesn't compile.
* Commented out reflect.TestStructOf test for padding after zero-sized field.
Reviewed-on: https://go-review.googlesource.com/35231
gotools/:
Updates for Go 1.8rc1.
* Makefile.am (go_cmd_go_files): Add bug.go.
(s-zdefaultcc): Write defaultPkgConfig.
* Makefile.in: Rebuild.
From-SVN: r244456
62 lines
1.9 KiB
Go
62 lines
1.9 KiB
Go
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build ignore_for_gccgo
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// +build ppc64 ppc64le
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package runtime
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import (
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"runtime/internal/sys"
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)
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const (
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// ISA level
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// Go currently requires POWER5 as a minimum for ppc64, so we need
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// to check for ISA 2.03 and beyond.
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_PPC_FEATURE_POWER5_PLUS = 0x00020000 // ISA 2.03 (POWER5+)
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_PPC_FEATURE_ARCH_2_05 = 0x00001000 // ISA 2.05 (POWER6)
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_PPC_FEATURE_POWER6_EXT = 0x00000200 // mffgpr/mftgpr extension (POWER6x)
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_PPC_FEATURE_ARCH_2_06 = 0x00000100 // ISA 2.06 (POWER7)
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_PPC_FEATURE2_ARCH_2_07 = 0x80000000 // ISA 2.07 (POWER8)
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// Standalone capabilities
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_PPC_FEATURE_HAS_ALTIVEC = 0x10000000 // SIMD/Vector unit
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_PPC_FEATURE_HAS_VSX = 0x00000080 // Vector scalar unit
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)
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type facilities struct {
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_ [sys.CacheLineSize]byte
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isPOWER5x bool // ISA 2.03
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isPOWER6 bool // ISA 2.05
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isPOWER6x bool // ISA 2.05 + mffgpr/mftgpr extension
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isPOWER7 bool // ISA 2.06
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isPOWER8 bool // ISA 2.07
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hasVMX bool // Vector unit
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hasVSX bool // Vector scalar unit
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_ [sys.CacheLineSize]byte
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}
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// cpu can be tested at runtime in go assembler code to check for
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// a certain ISA level or hardware capability, for example:
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// ·cpu+facilities_hasVSX(SB) for checking the availability of VSX
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// or
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// ·cpu+facilities_isPOWER7(SB) for checking if the processor implements
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// ISA 2.06 instructions.
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var cpu facilities
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func archauxv(tag, val uintptr) {
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switch tag {
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case _AT_HWCAP:
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cpu.isPOWER5x = val&_PPC_FEATURE_POWER5_PLUS != 0
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cpu.isPOWER6 = val&_PPC_FEATURE_ARCH_2_05 != 0
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cpu.isPOWER6x = val&_PPC_FEATURE_POWER6_EXT != 0
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cpu.isPOWER7 = val&_PPC_FEATURE_ARCH_2_06 != 0
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cpu.hasVMX = val&_PPC_FEATURE_HAS_ALTIVEC != 0
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cpu.hasVSX = val&_PPC_FEATURE_HAS_VSX != 0
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case _AT_HWCAP2:
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cpu.isPOWER8 = val&_PPC_FEATURE2_ARCH_2_07 != 0
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}
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}
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