4d0cdd0ce6
2016-10-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * coretypes.h: Move MEMMODEL_* macros and enum memmodel definition into ... * memmodel.h: This file. * alias.c, asan.c, auto-inc-dec.c, bb-reorder.c, bt-load.c, caller-save.c, calls.c, ccmp.c, cfgbuild.c, cfgcleanup.c, cfgexpand.c, cfgloopanal.c, cfgrtl.c, cilk-common.c, combine.c, combine-stack-adj.c, common/config/aarch64/aarch64-common.c, common/config/arm/arm-common.c, common/config/bfin/bfin-common.c, common/config/c6x/c6x-common.c, common/config/i386/i386-common.c, common/config/ia64/ia64-common.c, common/config/nvptx/nvptx-common.c, compare-elim.c, config/aarch64/aarch64-builtins.c, config/aarch64/aarch64-c.c, config/aarch64/cortex-a57-fma-steering.c, config/arc/arc.c, config/arc/arc-c.c, config/arm/arm-builtins.c, config/arm/arm-c.c, config/avr/avr.c, config/avr/avr-c.c, config/avr/avr-log.c, config/bfin/bfin.c, config/c6x/c6x.c, config/cr16/cr16.c, config/cris/cris.c, config/darwin-c.c, config/darwin.c, config/epiphany/epiphany.c, config/epiphany/mode-switch-use.c, config/epiphany/resolve-sw-modes.c, config/fr30/fr30.c, config/frv/frv.c, config/ft32/ft32.c, config/h8300/h8300.c, config/i386/i386-c.c, config/i386/winnt.c, config/iq2000/iq2000.c, config/lm32/lm32.c, config/m32c/m32c.c, config/m32r/m32r.c, config/m68k/m68k.c, config/mcore/mcore.c, config/microblaze/microblaze.c, config/mmix/mmix.c, config/mn10300/mn10300.c, config/moxie/moxie.c, config/msp430/msp430.c, config/nds32/nds32-cost.c, config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c, config/nds32/nds32-memory-manipulation.c, config/nds32/nds32-predicates.c, config/nds32/nds32.c, config/nios2/nios2.c, config/nvptx/nvptx.c, config/pa/pa.c, config/pdp11/pdp11.c, config/rl78/rl78.c, config/rs6000/rs6000-c.c, config/rx/rx.c, config/s390/s390-c.c, config/s390/s390.c, config/sh/sh.c, config/sh/sh-c.c, config/sh/sh-mem.cc, config/sh/sh_treg_combine.cc, config/sol2.c, config/spu/spu.c, config/stormy16/stormy16.c, config/tilegx/tilegx.c, config/tilepro/tilepro.c, config/v850/v850.c, config/vax/vax.c, config/visium/visium.c, config/vms/vms-c.c, config/xtensa/xtensa.c, coverage.c, cppbuiltin.c, cprop.c, cse.c, cselib.c, dbxout.c, dce.c, df-core.c, df-problems.c, df-scan.c, dojump.c, dse.c, dwarf2asm.c, dwarf2cfi.c, dwarf2out.c, emit-rtl.c, except.c, explow.c, expmed.c, expr.c, final.c, fold-const.c, function.c, fwprop.c, gcse.c, ggc-page.c, haifa-sched.c, hsa-brig.c, hsa-gen.c, hw-doloop.c, ifcvt.c, init-regs.c, internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c, ira-emit.c, ira-lives.c, ira.c, jump.c, loop-doloop.c, loop-invariant.c, loop-iv.c, loop-unroll.c, lower-subreg.c, lra.c, lra-assigns.c, lra-coalesce.c, lra-constraints.c, lra-eliminations.c, lra-lives.c, lra-remat.c, lra-spills.c, mode-switching.c, modulo-sched.c, omp-low.c, passes.c, postreload-gcse.c, postreload.c, predict.c, print-rtl-function.c, recog.c, ree.c, reg-stack.c, regcprop.c, reginfo.c, regrename.c, reload.c, reload1.c, reorg.c, resource.c, rtl-chkp.c, rtl-tests.c, rtlanal.c, rtlhooks.c, sched-deps.c, sched-rgn.c, sdbout.c, sel-sched-ir.c, sel-sched.c, shrink-wrap.c, simplify-rtx.c, stack-ptr-mod.c, stmt.c, stor-layout.c, target-globals.c, targhooks.c, toplev.c, tree-nested.c, tree-outof-ssa.c, tree-profile.c, tree-ssa-coalesce.c, tree-ssa-ifcombine.c, tree-ssa-loop-ivopts.c, tree-ssa-loop.c, tree-ssa-reassoc.c, tree-ssa-sccvn.c, tree-vect-data-refs.c, ubsan.c, valtrack.c, var-tracking.c, varasm.c: Include memmodel.h. * genattrtab.c (write_header): Include memmodel.h in generated file. * genautomata.c (main): Likewise. * gengtype.c (open_base_files): Likewise. * genopinit.c (main): Likewise. * genconditions.c (write_header): Include memmodel.h earlier in generated file. * genemit.c (main): Likewise. * genoutput.c (output_prologue): Likewise. * genpeep.c (main): Likewise. * genpreds.c (write_insn_preds_c): Likewise. * genrecog.c (write_header): Likewise. * Makefile.in (PLUGIN_HEADERS): Include memmodel.h gcc/ada/ * gcc-interface/utils2.c: Include memmodel.h. gcc/c-family/ * c-cppbuiltin.c: Include memmodel.h. * c-opts.c: Likewise. * c-pragma.c: Likewise. * c-warn.c: Likewise. gcc/c/ * c-typeck.c: Include memmodel.h. gcc/cp/ * decl2.c: Include memmodel.h. * rtti.c: Likewise. gcc/fortran/ * trans-intrinsic.c: Include memmodel.h. gcc/go/ * go-backend.c: Include memmodel.h. libgcc/ * libgcov-profiler.c: Replace MEMMODEL_* macros by their __ATOMIC_* equivalent. * config/tilepro/atomic.c: Likewise and stop casting model to enum memmodel. From-SVN: r241121
523 lines
14 KiB
C
523 lines
14 KiB
C
/* Natural loop analysis code for GNU compiler.
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Copyright (C) 2002-2016 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "backend.h"
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#include "rtl.h"
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#include "tree.h"
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#include "predict.h"
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#include "memmodel.h"
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#include "emit-rtl.h"
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#include "cfgloop.h"
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#include "explow.h"
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#include "expr.h"
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#include "graphds.h"
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#include "params.h"
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struct target_cfgloop default_target_cfgloop;
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#if SWITCHABLE_TARGET
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struct target_cfgloop *this_target_cfgloop = &default_target_cfgloop;
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#endif
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/* Checks whether BB is executed exactly once in each LOOP iteration. */
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bool
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just_once_each_iteration_p (const struct loop *loop, const_basic_block bb)
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{
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/* It must be executed at least once each iteration. */
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if (!dominated_by_p (CDI_DOMINATORS, loop->latch, bb))
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return false;
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/* And just once. */
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if (bb->loop_father != loop)
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return false;
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/* But this was not enough. We might have some irreducible loop here. */
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if (bb->flags & BB_IRREDUCIBLE_LOOP)
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return false;
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return true;
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}
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/* Marks blocks and edges that are part of non-recognized loops; i.e. we
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throw away all latch edges and mark blocks inside any remaining cycle.
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Everything is a bit complicated due to fact we do not want to do this
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for parts of cycles that only "pass" through some loop -- i.e. for
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each cycle, we want to mark blocks that belong directly to innermost
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loop containing the whole cycle.
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LOOPS is the loop tree. */
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#define LOOP_REPR(LOOP) ((LOOP)->num + last_basic_block_for_fn (cfun))
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#define BB_REPR(BB) ((BB)->index + 1)
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bool
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mark_irreducible_loops (void)
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{
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basic_block act;
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struct graph_edge *ge;
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edge e;
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edge_iterator ei;
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int src, dest;
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unsigned depth;
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struct graph *g;
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int num = number_of_loops (cfun);
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struct loop *cloop;
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bool irred_loop_found = false;
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int i;
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gcc_assert (current_loops != NULL);
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/* Reset the flags. */
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FOR_BB_BETWEEN (act, ENTRY_BLOCK_PTR_FOR_FN (cfun),
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EXIT_BLOCK_PTR_FOR_FN (cfun), next_bb)
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{
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act->flags &= ~BB_IRREDUCIBLE_LOOP;
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FOR_EACH_EDGE (e, ei, act->succs)
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e->flags &= ~EDGE_IRREDUCIBLE_LOOP;
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}
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/* Create the edge lists. */
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g = new_graph (last_basic_block_for_fn (cfun) + num);
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FOR_BB_BETWEEN (act, ENTRY_BLOCK_PTR_FOR_FN (cfun),
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EXIT_BLOCK_PTR_FOR_FN (cfun), next_bb)
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FOR_EACH_EDGE (e, ei, act->succs)
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{
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/* Ignore edges to exit. */
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if (e->dest == EXIT_BLOCK_PTR_FOR_FN (cfun))
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continue;
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src = BB_REPR (act);
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dest = BB_REPR (e->dest);
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/* Ignore latch edges. */
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if (e->dest->loop_father->header == e->dest
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&& e->dest->loop_father->latch == act)
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continue;
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/* Edges inside a single loop should be left where they are. Edges
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to subloop headers should lead to representative of the subloop,
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but from the same place.
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Edges exiting loops should lead from representative
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of the son of nearest common ancestor of the loops in that
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act lays. */
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if (e->dest->loop_father->header == e->dest)
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dest = LOOP_REPR (e->dest->loop_father);
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if (!flow_bb_inside_loop_p (act->loop_father, e->dest))
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{
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depth = 1 + loop_depth (find_common_loop (act->loop_father,
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e->dest->loop_father));
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if (depth == loop_depth (act->loop_father))
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cloop = act->loop_father;
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else
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cloop = (*act->loop_father->superloops)[depth];
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src = LOOP_REPR (cloop);
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}
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add_edge (g, src, dest)->data = e;
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}
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/* Find the strongly connected components. */
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graphds_scc (g, NULL);
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/* Mark the irreducible loops. */
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for (i = 0; i < g->n_vertices; i++)
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for (ge = g->vertices[i].succ; ge; ge = ge->succ_next)
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{
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edge real = (edge) ge->data;
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/* edge E in graph G is irreducible if it connects two vertices in the
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same scc. */
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/* All edges should lead from a component with higher number to the
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one with lower one. */
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gcc_assert (g->vertices[ge->src].component >= g->vertices[ge->dest].component);
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if (g->vertices[ge->src].component != g->vertices[ge->dest].component)
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continue;
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real->flags |= EDGE_IRREDUCIBLE_LOOP;
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irred_loop_found = true;
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if (flow_bb_inside_loop_p (real->src->loop_father, real->dest))
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real->src->flags |= BB_IRREDUCIBLE_LOOP;
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}
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free_graph (g);
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loops_state_set (LOOPS_HAVE_MARKED_IRREDUCIBLE_REGIONS);
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return irred_loop_found;
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}
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/* Counts number of insns inside LOOP. */
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int
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num_loop_insns (const struct loop *loop)
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{
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basic_block *bbs, bb;
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unsigned i, ninsns = 0;
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rtx_insn *insn;
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bbs = get_loop_body (loop);
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for (i = 0; i < loop->num_nodes; i++)
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{
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bb = bbs[i];
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FOR_BB_INSNS (bb, insn)
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if (NONDEBUG_INSN_P (insn))
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ninsns++;
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}
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free (bbs);
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if (!ninsns)
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ninsns = 1; /* To avoid division by zero. */
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return ninsns;
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}
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/* Counts number of insns executed on average per iteration LOOP. */
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int
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average_num_loop_insns (const struct loop *loop)
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{
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basic_block *bbs, bb;
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unsigned i, binsns, ninsns, ratio;
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rtx_insn *insn;
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ninsns = 0;
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bbs = get_loop_body (loop);
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for (i = 0; i < loop->num_nodes; i++)
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{
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bb = bbs[i];
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binsns = 0;
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FOR_BB_INSNS (bb, insn)
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if (NONDEBUG_INSN_P (insn))
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binsns++;
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ratio = loop->header->frequency == 0
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? BB_FREQ_MAX
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: (bb->frequency * BB_FREQ_MAX) / loop->header->frequency;
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ninsns += binsns * ratio;
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}
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free (bbs);
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ninsns /= BB_FREQ_MAX;
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if (!ninsns)
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ninsns = 1; /* To avoid division by zero. */
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return ninsns;
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}
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/* Returns expected number of iterations of LOOP, according to
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measured or guessed profile. No bounding is done on the
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value. */
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gcov_type
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expected_loop_iterations_unbounded (const struct loop *loop,
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bool *read_profile_p)
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{
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edge e;
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edge_iterator ei;
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gcov_type expected;
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if (read_profile_p)
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*read_profile_p = false;
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/* If we have no profile at all, use AVG_LOOP_NITER. */
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if (profile_status_for_fn (cfun) == PROFILE_ABSENT)
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expected = PARAM_VALUE (PARAM_AVG_LOOP_NITER);
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else if (loop->latch && (loop->latch->count || loop->header->count))
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{
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gcov_type count_in, count_latch;
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count_in = 0;
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count_latch = 0;
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FOR_EACH_EDGE (e, ei, loop->header->preds)
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if (e->src == loop->latch)
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count_latch = e->count;
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else
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count_in += e->count;
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if (count_in == 0)
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expected = count_latch * 2;
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else
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{
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expected = (count_latch + count_in - 1) / count_in;
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if (read_profile_p)
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*read_profile_p = true;
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}
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}
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else
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{
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int freq_in, freq_latch;
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freq_in = 0;
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freq_latch = 0;
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FOR_EACH_EDGE (e, ei, loop->header->preds)
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if (flow_bb_inside_loop_p (loop, e->src))
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freq_latch += EDGE_FREQUENCY (e);
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else
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freq_in += EDGE_FREQUENCY (e);
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if (freq_in == 0)
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{
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/* If we have no profile at all, use AVG_LOOP_NITER iterations. */
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if (!freq_latch)
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expected = PARAM_VALUE (PARAM_AVG_LOOP_NITER);
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else
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expected = freq_latch * 2;
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}
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else
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expected = (freq_latch + freq_in - 1) / freq_in;
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}
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HOST_WIDE_INT max = get_max_loop_iterations_int (loop);
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if (max != -1 && max < expected)
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return max;
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return expected;
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}
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/* Returns expected number of LOOP iterations. The returned value is bounded
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by REG_BR_PROB_BASE. */
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unsigned
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expected_loop_iterations (struct loop *loop)
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{
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gcov_type expected = expected_loop_iterations_unbounded (loop);
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return (expected > REG_BR_PROB_BASE ? REG_BR_PROB_BASE : expected);
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}
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/* Returns the maximum level of nesting of subloops of LOOP. */
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unsigned
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get_loop_level (const struct loop *loop)
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{
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const struct loop *ploop;
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unsigned mx = 0, l;
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for (ploop = loop->inner; ploop; ploop = ploop->next)
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{
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l = get_loop_level (ploop);
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if (l >= mx)
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mx = l + 1;
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}
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return mx;
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}
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/* Initialize the constants for computing set costs. */
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void
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init_set_costs (void)
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{
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int speed;
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rtx_insn *seq;
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rtx reg1 = gen_raw_REG (SImode, LAST_VIRTUAL_REGISTER + 1);
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rtx reg2 = gen_raw_REG (SImode, LAST_VIRTUAL_REGISTER + 2);
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rtx addr = gen_raw_REG (Pmode, LAST_VIRTUAL_REGISTER + 3);
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rtx mem = validize_mem (gen_rtx_MEM (SImode, addr));
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unsigned i;
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target_avail_regs = 0;
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target_clobbered_regs = 0;
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)
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&& !fixed_regs[i])
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{
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target_avail_regs++;
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if (call_used_regs[i])
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target_clobbered_regs++;
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}
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target_res_regs = 3;
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for (speed = 0; speed < 2; speed++)
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{
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crtl->maybe_hot_insn_p = speed;
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/* Set up the costs for using extra registers:
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1) If not many free registers remain, we should prefer having an
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additional move to decreasing the number of available registers.
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(TARGET_REG_COST).
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2) If no registers are available, we need to spill, which may require
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storing the old value to memory and loading it back
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(TARGET_SPILL_COST). */
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start_sequence ();
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emit_move_insn (reg1, reg2);
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seq = get_insns ();
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end_sequence ();
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target_reg_cost [speed] = seq_cost (seq, speed);
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start_sequence ();
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emit_move_insn (mem, reg1);
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emit_move_insn (reg2, mem);
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seq = get_insns ();
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end_sequence ();
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target_spill_cost [speed] = seq_cost (seq, speed);
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}
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default_rtl_profile ();
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}
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/* Estimates cost of increased register pressure caused by making N_NEW new
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registers live around the loop. N_OLD is the number of registers live
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around the loop. If CALL_P is true, also take into account that
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call-used registers may be clobbered in the loop body, reducing the
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number of available registers before we spill. */
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unsigned
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estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
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bool call_p)
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{
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unsigned cost;
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unsigned regs_needed = n_new + n_old;
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unsigned available_regs = target_avail_regs;
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|
|
/* If there is a call in the loop body, the call-clobbered registers
|
|
are not available for loop invariants. */
|
|
if (call_p)
|
|
available_regs = available_regs - target_clobbered_regs;
|
|
|
|
/* If we have enough registers, we should use them and not restrict
|
|
the transformations unnecessarily. */
|
|
if (regs_needed + target_res_regs <= available_regs)
|
|
return 0;
|
|
|
|
if (regs_needed <= available_regs)
|
|
/* If we are close to running out of registers, try to preserve
|
|
them. */
|
|
cost = target_reg_cost [speed] * n_new;
|
|
else
|
|
/* If we run out of registers, it is very expensive to add another
|
|
one. */
|
|
cost = target_spill_cost [speed] * n_new;
|
|
|
|
if (optimize && (flag_ira_region == IRA_REGION_ALL
|
|
|| flag_ira_region == IRA_REGION_MIXED)
|
|
&& number_of_loops (cfun) <= (unsigned) IRA_MAX_LOOPS_NUM)
|
|
/* IRA regional allocation deals with high register pressure
|
|
better. So decrease the cost (to do more accurate the cost
|
|
calculation for IRA, we need to know how many registers lives
|
|
through the loop transparently). */
|
|
cost /= 2;
|
|
|
|
return cost;
|
|
}
|
|
|
|
/* Sets EDGE_LOOP_EXIT flag for all loop exits. */
|
|
|
|
void
|
|
mark_loop_exit_edges (void)
|
|
{
|
|
basic_block bb;
|
|
edge e;
|
|
|
|
if (number_of_loops (cfun) <= 1)
|
|
return;
|
|
|
|
FOR_EACH_BB_FN (bb, cfun)
|
|
{
|
|
edge_iterator ei;
|
|
|
|
FOR_EACH_EDGE (e, ei, bb->succs)
|
|
{
|
|
if (loop_outer (bb->loop_father)
|
|
&& loop_exit_edge_p (bb->loop_father, e))
|
|
e->flags |= EDGE_LOOP_EXIT;
|
|
else
|
|
e->flags &= ~EDGE_LOOP_EXIT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return exit edge if loop has only one exit that is likely
|
|
to be executed on runtime (i.e. it is not EH or leading
|
|
to noreturn call. */
|
|
|
|
edge
|
|
single_likely_exit (struct loop *loop)
|
|
{
|
|
edge found = single_exit (loop);
|
|
vec<edge> exits;
|
|
unsigned i;
|
|
edge ex;
|
|
|
|
if (found)
|
|
return found;
|
|
exits = get_loop_exit_edges (loop);
|
|
FOR_EACH_VEC_ELT (exits, i, ex)
|
|
{
|
|
if (ex->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
|
|
continue;
|
|
/* The constant of 5 is set in a way so noreturn calls are
|
|
ruled out by this test. The static branch prediction algorithm
|
|
will not assign such a low probability to conditionals for usual
|
|
reasons. */
|
|
if (profile_status_for_fn (cfun) != PROFILE_ABSENT
|
|
&& ex->probability < 5 && !ex->count)
|
|
continue;
|
|
if (!found)
|
|
found = ex;
|
|
else
|
|
{
|
|
exits.release ();
|
|
return NULL;
|
|
}
|
|
}
|
|
exits.release ();
|
|
return found;
|
|
}
|
|
|
|
|
|
/* Gets basic blocks of a LOOP. Header is the 0-th block, rest is in dfs
|
|
order against direction of edges from latch. Specially, if
|
|
header != latch, latch is the 1-st block. */
|
|
|
|
vec<basic_block>
|
|
get_loop_hot_path (const struct loop *loop)
|
|
{
|
|
basic_block bb = loop->header;
|
|
vec<basic_block> path = vNULL;
|
|
bitmap visited = BITMAP_ALLOC (NULL);
|
|
|
|
while (true)
|
|
{
|
|
edge_iterator ei;
|
|
edge e;
|
|
edge best = NULL;
|
|
|
|
path.safe_push (bb);
|
|
bitmap_set_bit (visited, bb->index);
|
|
FOR_EACH_EDGE (e, ei, bb->succs)
|
|
if ((!best || e->probability > best->probability)
|
|
&& !loop_exit_edge_p (loop, e)
|
|
&& !bitmap_bit_p (visited, e->dest->index))
|
|
best = e;
|
|
if (!best || best->dest == loop->header)
|
|
break;
|
|
bb = best->dest;
|
|
}
|
|
BITMAP_FREE (visited);
|
|
return path;
|
|
}
|