140 lines
3.6 KiB
ArmAsm
140 lines
3.6 KiB
ArmAsm
/* CMSE wrapper function used to save, clear and restore callee saved registers
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for cmse_nonsecure_call's.
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Copyright (C) 2016-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 3, or (at your option) any
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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.syntax unified
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#ifdef __ARM_PCS_VFP
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# if __ARM_FP & 0x8
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.fpu fpv5-d16
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# else
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.fpu fpv4-sp-d16
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# endif
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#endif
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.thumb
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.global __gnu_cmse_nonsecure_call
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__gnu_cmse_nonsecure_call:
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#if defined(__ARM_ARCH_8M_MAIN__)
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push {r5-r11,lr}
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mov r7, r4
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mov r8, r4
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mov r9, r4
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mov r10, r4
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mov r11, r4
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mov ip, r4
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/* Save and clear callee-saved registers only if we are dealing with hard float
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ABI. The unused caller-saved registers have already been cleared by GCC
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generated code. */
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#ifdef __ARM_PCS_VFP
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vpush.f64 {d8-d15}
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mov r5, #0
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vmov d8, r5, r5
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#if __ARM_FP & 0x04
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vmov s18, s19, r5, r5
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vmov s20, s21, r5, r5
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vmov s22, s23, r5, r5
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vmov s24, s25, r5, r5
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vmov s26, s27, r5, r5
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vmov s28, s29, r5, r5
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vmov s30, s31, r5, r5
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#elif __ARM_FP & 0x08
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vmov.f64 d9, d8
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vmov.f64 d10, d8
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vmov.f64 d11, d8
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vmov.f64 d12, d8
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vmov.f64 d13, d8
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vmov.f64 d14, d8
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vmov.f64 d15, d8
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#else
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#error "Half precision implementation not supported."
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#endif
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/* Clear the cumulative exception-status bits (0-4,7) and the
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condition code bits (28-31) of the FPSCR. */
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vmrs r5, fpscr
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movw r6, #65376
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movt r6, #4095
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ands r5, r6
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vmsr fpscr, r5
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/* We are not dealing with hard float ABI, so we can safely use the vlstm and
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vlldm instructions without needing to preserve the registers used for
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argument passing. */
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#else
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sub sp, sp, #0x88 /* Reserve stack space to save all floating point
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registers, including FPSCR. */
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vlstm sp /* Lazy store and clearance of d0-d16 and FPSCR. */
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#endif /* __ARM_PCS_VFP */
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/* Make sure to clear the 'GE' bits of the APSR register if 32-bit SIMD
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instructions are available. */
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#if defined(__ARM_FEATURE_SIMD32)
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msr APSR_nzcvqg, r4
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#else
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msr APSR_nzcvq, r4
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#endif
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mov r5, r4
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mov r6, r4
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blxns r4
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#ifdef __ARM_PCS_VFP
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vpop.f64 {d8-d15}
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#else
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vlldm sp /* Lazy restore of d0-d16 and FPSCR. */
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add sp, sp, #0x88 /* Free space used to save floating point registers. */
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#endif /* __ARM_PCS_VFP */
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pop {r5-r11, pc}
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#elif defined (__ARM_ARCH_8M_BASE__)
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push {r5-r7, lr}
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mov r5, r8
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mov r6, r9
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mov r7, r10
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push {r5-r7}
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mov r5, r11
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push {r5}
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mov r5, r4
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mov r6, r4
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mov r7, r4
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mov r8, r4
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mov r9, r4
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mov r10, r4
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mov r11, r4
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mov ip, r4
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msr APSR_nzcvq, r4
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blxns r4
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pop {r5}
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mov r11, r5
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pop {r5-r7}
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mov r10, r7
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mov r9, r6
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mov r8, r5
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pop {r5-r7, pc}
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#else
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#error "This should only be used for armv8-m base- and mainline."
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#endif
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