eac8675225
aarch64's *add<mode>3_poly_1 has a pattern with the constraints: "=...,r,&r" "...,0,rk" "...,Uai,Uat" i.e. the penultimate alternative requires operands 0 and 1 to match, but the final alternative does not allow them to match. The register allocators dealt with this correctly, and so used different input and output registers for instructions with Uat operands. However, constrain_operands carried the penultimate alternative's matching rule over to the final alternative, so it would essentially ignore the earlyclobber. This in turn allowed postreload to convert a correct Uat pairing into an incorrect one. The fix is simple: recompute the matching information for each alternative. gcc/ PR rtl-optimization/97144 * recog.c (constrain_operands): Initialize matching_operand for each alternative, rather than only doing it once. gcc/testsuite/ PR rtl-optimization/97144 * gcc.c-torture/compile/pr97144.c: New test. * gcc.target/aarch64/sve/pr97144.c: Likewise.
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