180 lines
5.1 KiB
Plaintext
180 lines
5.1 KiB
Plaintext
; Copyright (C) 2021-2022 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; <http://www.gnu.org/licenses/>.
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;
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; Variables (macros) that should be exported by loongarch.opt:
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; la_opt_switches,
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; la_opt_abi_base, la_opt_abi_ext,
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; la_opt_cpu_arch, la_opt_cpu_tune,
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; la_opt_fpu,
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; la_cmodel.
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HeaderInclude
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config/loongarch/loongarch-opts.h
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HeaderInclude
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config/loongarch/loongarch-str.h
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Variable
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HOST_WIDE_INT la_opt_switches = 0
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; ISA related options
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;; Base ISA
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Enum
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Name(isa_base) Type(int)
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Basic ISAs of LoongArch:
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EnumValue
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Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
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;; ISA extensions / adjustments
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Enum
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Name(isa_ext_fpu) Type(int)
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FPU types of LoongArch:
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EnumValue
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Enum(isa_ext_fpu) String(@@STR_ISA_EXT_NOFPU@@) Value(ISA_EXT_NOFPU)
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EnumValue
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Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU32@@) Value(ISA_EXT_FPU32)
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EnumValue
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Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64)
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m@@OPTSTR_ISA_EXT_FPU@@=
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Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) Init(M_OPTION_NOT_SEEN)
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-m@@OPTSTR_ISA_EXT_FPU@@=FPU Generate code for the given FPU.
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m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@
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Target RejectNegative Alias(m@@OPTSTR_ISA_EXT_FPU@@=,@@STR_ISA_EXT_NOFPU@@)
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m@@OPTSTR_SOFT_FLOAT@@
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Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_SOFTF) Negative(m@@OPTSTR_SINGLE_FLOAT@@)
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Prevent the use of all hardware floating-point instructions.
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m@@OPTSTR_SINGLE_FLOAT@@
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Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F32) Negative(m@@OPTSTR_DOUBLE_FLOAT@@)
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Restrict the use of hardware floating-point instructions to 32-bit operations.
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m@@OPTSTR_DOUBLE_FLOAT@@
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Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(m@@OPTSTR_SOFT_FLOAT@@)
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Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
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;; Base target models (implies ISA & tune parameters)
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Enum
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Name(cpu_type) Type(int)
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LoongArch CPU types:
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EnumValue
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Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE)
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EnumValue
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Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
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EnumValue
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Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
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m@@OPTSTR_ARCH@@=
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Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPTION_NOT_SEEN)
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-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA.
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m@@OPTSTR_TUNE@@=
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Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) Init(M_OPTION_NOT_SEEN)
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-m@@OPTSTR_TUNE@@=PROCESSOR Generate optimized code for PROCESSOR.
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; ABI related options
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; (ISA constraints on ABI are handled dynamically)
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;; Base ABI
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Enum
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Name(abi_base) Type(int)
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Base ABI types for LoongArch:
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EnumValue
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Enum(abi_base) String(@@STR_ABI_BASE_LP64D@@) Value(ABI_BASE_LP64D)
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EnumValue
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Enum(abi_base) String(@@STR_ABI_BASE_LP64F@@) Value(ABI_BASE_LP64F)
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EnumValue
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Enum(abi_base) String(@@STR_ABI_BASE_LP64S@@) Value(ABI_BASE_LP64S)
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m@@OPTSTR_ABI_BASE@@=
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Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_OPTION_NOT_SEEN)
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-m@@OPTSTR_ABI_BASE@@=BASEABI Generate code that conforms to the given BASEABI.
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;; ABI Extension
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Variable
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int la_opt_abi_ext = M_OPTION_NOT_SEEN
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mbranch-cost=
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Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
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-mbranch-cost=COST Set the cost of branches to roughly COST instructions.
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mcheck-zero-division
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Target Mask(CHECK_ZERO_DIV)
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Trap on integer divide by zero.
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mcond-move-int
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Target Var(TARGET_COND_MOVE_INT) Init(1)
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Conditional moves for integral are enabled.
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mcond-move-float
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Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
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Conditional moves for float are enabled.
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mmemcpy
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Target Mask(MEMCPY)
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Prevent optimizing block moves, which is also the default behavior of -Os.
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mstrict-align
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Target Var(TARGET_STRICT_ALIGN) Init(0)
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Do not generate unaligned memory accesses.
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mmax-inline-memcpy-size=
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Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024)
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-mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024.
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; The code model option names for -mcmodel.
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Enum
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Name(cmodel) Type(int)
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The code model option names for -mcmodel:
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EnumValue
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Enum(cmodel) String(@@STR_CMODEL_NORMAL@@) Value(CMODEL_NORMAL)
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EnumValue
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Enum(cmodel) String(@@STR_CMODEL_TINY@@) Value(CMODEL_TINY)
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EnumValue
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Enum(cmodel) String(@@STR_CMODEL_TS@@) Value(CMODEL_TINY_STATIC)
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EnumValue
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Enum(cmodel) String(@@STR_CMODEL_LARGE@@) Value(CMODEL_LARGE)
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EnumValue
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Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME)
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mcmodel=
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Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL)
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Specify the code model.
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