152 lines
4.2 KiB
C
152 lines
4.2 KiB
C
/* LoongArch definitions.
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Copyright (C) 2021-2022 Free Software Foundation, Inc.
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Contributed by Loongson Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* Definition of standard codes for:
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- base architecture types (isa_base),
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- ISA extensions (isa_ext),
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- base ABI types (abi_base),
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- ABI extension types (abi_ext).
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- code models (cmodel)
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- other command-line switches (switch)
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These values are primarily used for implementing option handling
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logic in "loongarch.opt", "loongarch-driver.c" and "loongarch-opt.c".
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As for the result of this option handling process, the following
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scheme is adopted to represent the final configuration:
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- The target ABI is encoded with a tuple (abi_base, abi_ext)
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using the code defined below.
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- The target ISA is encoded with a "struct loongarch_isa" defined
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in loongarch-cpu.h.
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- The target microarchitecture is represented with a cpu model
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index defined in loongarch-cpu.h.
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*/
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#ifndef LOONGARCH_DEF_H
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#define LOONGARCH_DEF_H
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#include "loongarch-tune.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* enum isa_base */
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extern const char* loongarch_isa_base_strings[];
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#define ISA_BASE_LA64V100 0
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#define N_ISA_BASE_TYPES 1
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/* enum isa_ext_* */
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extern const char* loongarch_isa_ext_strings[];
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#define ISA_EXT_NOFPU 0
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#define ISA_EXT_FPU32 1
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#define ISA_EXT_FPU64 2
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#define N_ISA_EXT_FPU_TYPES 3
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#define N_ISA_EXT_TYPES 3
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/* enum abi_base */
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extern const char* loongarch_abi_base_strings[];
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#define ABI_BASE_LP64D 0
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#define ABI_BASE_LP64F 1
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#define ABI_BASE_LP64S 2
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#define N_ABI_BASE_TYPES 3
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/* enum abi_ext */
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extern const char* loongarch_abi_ext_strings[];
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#define ABI_EXT_BASE 0
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#define N_ABI_EXT_TYPES 1
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/* enum cmodel */
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extern const char* loongarch_cmodel_strings[];
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#define CMODEL_NORMAL 0
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#define CMODEL_TINY 1
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#define CMODEL_TINY_STATIC 2
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#define CMODEL_LARGE 3
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#define CMODEL_EXTREME 4
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#define N_CMODEL_TYPES 5
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/* enum switches */
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/* The "SW_" codes represent command-line switches (options that
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accept no parameters). Definition for other switches that affects
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the target ISA / ABI configuration will also be appended here
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in the future. */
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extern const char* loongarch_switch_strings[];
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#define SW_SOFT_FLOAT 0
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#define SW_SINGLE_FLOAT 1
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#define SW_DOUBLE_FLOAT 2
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#define N_SWITCH_TYPES 3
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/* The common default value for variables whose assignments
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are triggered by command-line options. */
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#define M_OPTION_NOT_SEEN -1
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#define M_OPT_ABSENT(opt_enum) ((opt_enum) == M_OPTION_NOT_SEEN)
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/* Internal representation of the target. */
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struct loongarch_isa
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{
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unsigned char base; /* ISA_BASE_ */
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unsigned char fpu; /* ISA_EXT_FPU_ */
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};
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struct loongarch_abi
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{
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unsigned char base; /* ABI_BASE_ */
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unsigned char ext; /* ABI_EXT_ */
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};
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struct loongarch_target
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{
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struct loongarch_isa isa;
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struct loongarch_abi abi;
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unsigned char cpu_arch; /* CPU_ */
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unsigned char cpu_tune; /* same */
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unsigned char cpu_native; /* same */
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unsigned char cmodel; /* CMODEL_ */
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};
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/* CPU properties. */
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/* index */
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#define CPU_NATIVE 0
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#define CPU_LOONGARCH64 1
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#define CPU_LA464 2
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#define N_ARCH_TYPES 3
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#define N_TUNE_TYPES 3
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/* parallel tables. */
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extern const char* loongarch_cpu_strings[];
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extern struct loongarch_isa loongarch_cpu_default_isa[];
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extern int loongarch_cpu_issue_rate[];
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extern int loongarch_cpu_multipass_dfa_lookahead[];
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extern struct loongarch_cache loongarch_cpu_cache[];
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extern struct loongarch_rtx_cost_data loongarch_cpu_rtx_cost_data[];
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#ifdef __cplusplus
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}
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#endif
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#endif /* LOONGARCH_DEF_H */
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